DTS: Update the device-tree files to Linux 5.5
This commit is contained in:
manu
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@ -12,7 +12,6 @@ $(obj)/%.example.dts: $(src)/%.yaml FORCE
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$(call if_changed,chk_binding)
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DT_TMP_SCHEMA := processed-schema.yaml
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extra-y += $(DT_TMP_SCHEMA)
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quiet_cmd_mk_schema = SCHEMA $@
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cmd_mk_schema = $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) -o $@ $(real-prereqs)
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@ -26,8 +25,12 @@ DT_DOCS = $(shell \
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DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS))
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ifeq ($(CHECK_DTBS),)
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extra-y += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
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extra-y += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
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endif
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$(obj)/$(DT_TMP_SCHEMA): $(DT_SCHEMA_FILES) FORCE
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$(call if_changed,mk_schema)
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extra-y += $(DT_TMP_SCHEMA)
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@ -94,7 +94,7 @@ properties:
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- amlogic,p212
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- hwacom,amazetv
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- khadas,vim
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- libretech,cc
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- libretech,aml-s905x-cc
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- nexbox,a95x
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- const: amlogic,s905x
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- const: amlogic,meson-gxl
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@ -147,6 +147,7 @@ properties:
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- enum:
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- hardkernel,odroid-n2
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- khadas,vim3
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- ugoos,am6
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- const: amlogic,s922x
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- const: amlogic,g12b
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@ -156,4 +157,10 @@ properties:
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- seirobotics,sei610
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- khadas,vim3l
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- const: amlogic,sm1
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- description: Boards with the Amlogic Meson A1 A113L SoC
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items:
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- enum:
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- amlogic,ad401
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- const: amlogic,a1
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...
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@ -1,32 +0,0 @@
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Amlogic Meson8 and Meson8b SRAM for smp bringup:
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------------------------------------------------
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Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
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Once the core gets powered up it executes the code that is residing at a
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specific location.
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Therefore a reserved section sub-node has to be added to the mmio-sram
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declaration.
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Required sub-node properties:
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- compatible : depending on the SoC this should be one of:
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"amlogic,meson8-smp-sram"
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"amlogic,meson8b-smp-sram"
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The rest of the properties should follow the generic mmio-sram discription
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found in ../../misc/sram.txt
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Example:
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sram: sram@d9000000 {
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compatible = "mmio-sram";
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reg = <0xd9000000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xd9000000 0x20000>;
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smp-sram@1ff80 {
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compatible = "amlogic,meson8b-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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@ -100,7 +100,7 @@ Required sub-node properties:
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[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power_domain.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/thermal/thermal.txt
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[4] Documentation/devicetree/bindings/sram/sram.txt
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[5] Documentation/devicetree/bindings/reset/reset.txt
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@ -110,7 +110,7 @@ Required properties:
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/thermal/thermal.txt
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[3] Documentation/devicetree/bindings/sram/sram.txt
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[4] Documentation/devicetree/bindings/power/power_domain.txt
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[4] Documentation/devicetree/bindings/power/power-domain.yaml
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Example:
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@ -45,6 +45,13 @@ properties:
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- const: atmel,at91sam9x5
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- const: atmel,at91sam9
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- description: Overkiz kizbox3 board
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items:
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- const: overkiz,kizbox3-hs
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- const: atmel,sama5d27
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- const: atmel,sama5d2
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- const: atmel,sama5
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- items:
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- const: atmel,sama5d27
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- const: atmel,sama5d2
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@ -73,6 +80,13 @@ properties:
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- const: atmel,sama5d3
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- const: atmel,sama5
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- description: Overkiz kizbox2 board with two heads
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items:
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- const: overkiz,kizbox2-2
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- const: atmel,sama5d31
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- const: atmel,sama5d3
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- const: atmel,sama5
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- items:
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- enum:
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- atmel,sama5d31
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@ -1,28 +0,0 @@
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Device tree bindings for Axentia ARM devices
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============================================
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Linea CPU module
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----------------
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Required root node properties:
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compatible = "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from atmel-at91.txt for a sama5d31 SoC.
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Nattis v2 board with Natte v2 power board
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-----------------------------------------
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Required root node properties:
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compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from above for the axentia,linea CPU module.
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TSE-850 v3 board
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----------------
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Required root node properties:
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compatible = "axentia,tse850v3", "axentia,linea",
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"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
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and following the rules from above for the axentia,linea CPU module.
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54
Bindings/arm/bcm/bcm2835.yaml
Normal file
54
Bindings/arm/bcm/bcm2835.yaml
Normal file
@ -0,0 +1,54 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings
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maintainers:
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- Eric Anholt <eric@anholt.net>
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- Stefan Wahren <wahrenst@gmx.net>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: BCM2711 based Boards
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items:
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- enum:
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- raspberrypi,4-model-b
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- const: brcm,bcm2711
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- description: BCM2835 based Boards
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items:
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- enum:
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- raspberrypi,model-a
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- raspberrypi,model-a-plus
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- raspberrypi,model-b
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- raspberrypi,model-b-i2c0 # Raspberry Pi Model B (no P5)
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- raspberrypi,model-b-rev2
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- raspberrypi,model-b-plus
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- raspberrypi,compute-module
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- raspberrypi,model-zero
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- raspberrypi,model-zero-w
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- const: brcm,bcm2835
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- description: BCM2836 based Boards
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items:
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- enum:
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- raspberrypi,2-model-b
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- const: brcm,bcm2836
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- description: BCM2837 based Boards
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items:
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- enum:
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- raspberrypi,3-model-a-plus
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- raspberrypi,3-model-b
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- raspberrypi,3-model-b-plus
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- raspberrypi,3-compute-module
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- raspberrypi,3-compute-module-lite
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- const: brcm,bcm2837
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...
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@ -1,67 +0,0 @@
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Broadcom BCM2835 device tree bindings
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-------------------------------------------
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Raspberry Pi Model A
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Required root node properties:
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compatible = "raspberrypi,model-a", "brcm,bcm2835";
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Raspberry Pi Model A+
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Required root node properties:
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compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
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Raspberry Pi Model B
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Required root node properties:
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compatible = "raspberrypi,model-b", "brcm,bcm2835";
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Raspberry Pi Model B (no P5)
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early model B with I2C0 rather than I2C1 routed to the expansion header
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Required root node properties:
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compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835";
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Raspberry Pi Model B rev2
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Required root node properties:
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compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
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Raspberry Pi Model B+
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Required root node properties:
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compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
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Raspberry Pi 2 Model B
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Required root node properties:
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compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
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Raspberry Pi 3 Model A+
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Required root node properties:
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compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
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Raspberry Pi 3 Model B
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Required root node properties:
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compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
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Raspberry Pi 3 Model B+
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Required root node properties:
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compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
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Raspberry Pi Compute Module
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Required root node properties:
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compatible = "raspberrypi,compute-module", "brcm,bcm2835";
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Raspberry Pi Compute Module 3
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Required root node properties:
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compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
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Raspberry Pi Compute Module 3 Lite
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Required root node properties:
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compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";
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Raspberry Pi Zero
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Required root node properties:
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compatible = "raspberrypi,model-zero", "brcm,bcm2835";
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Raspberry Pi Zero W
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Required root node properties:
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compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
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Generic BCM2835 board
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Required root node properties:
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compatible = "brcm,bcm2835";
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@ -87,6 +87,15 @@ its hardware characteristcs.
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* port or ports: see "Graph bindings for Coresight" below.
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* Optional properties for all components:
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* arm,coresight-loses-context-with-cpu : boolean. Indicates that the
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hardware will lose register context on CPU power down (e.g. CPUIdle).
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An example of where this may be needed are systems which contain a
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coresight component and CPU in the same power domain. When the CPU
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powers down the coresight component also powers down and loses its
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context. This property is currently only used for the ETM 4.x driver.
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* Optional properties for ETM/PTMs:
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* arm,cp14: must be present if the system accesses ETM/PTM management
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@ -189,6 +189,7 @@ properties:
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- marvell,armada-390-smp
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- marvell,armada-xp-smp
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- marvell,98dx3236-smp
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- marvell,mmp3-smp
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- mediatek,mt6589-smp
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- mediatek,mt81xx-tz-smp
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- qcom,gcc-msm8660
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@ -124,7 +124,7 @@ Required properties for Pinctrl sub nodes:
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CONFIG settings.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power_domain.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
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RTC bindings based on SCU Message Protocol
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@ -157,6 +157,15 @@ Required properties:
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Optional properties:
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- timeout-sec: contains the watchdog timeout in seconds.
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SCU key bindings based on SCU Message Protocol
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------------------------------------------------------------
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Required properties:
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- compatible: should be:
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"fsl,imx8qxp-sc-key"
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followed by "fsl,imx-sc-key";
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- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
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Example (imx8qxp):
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-------------
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aliases {
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@ -220,6 +229,11 @@ firmware {
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compatible = "fsl,imx8qxp-sc-rtc";
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};
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scu_key: scu-key {
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compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
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linux,keycodes = <KEY_POWER>;
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};
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watchdog {
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compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
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timeout-sec = <60>;
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@ -38,12 +38,16 @@ properties:
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- description: i.MX27 Product Development Kit
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items:
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- enum:
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- armadeus,imx27-apf27 # APF27 SoM
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- armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board
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- fsl,imx27-pdk
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- const: fsl,imx27
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- description: i.MX28 based Boards
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items:
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- enum:
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- armadeus,imx28-apf28 # APF28 SoM
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- armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board
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- fsl,imx28-evk
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- i2se,duckbill
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- i2se,duckbill-2
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@ -87,7 +91,8 @@ properties:
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- description: i.MX51 Babbage Board
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items:
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- enum:
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- armadeus,imx51-apf51
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- armadeus,imx51-apf51 # APF51 SoM
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- armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board
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- fsl,imx51-babbage
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- technologic,imx51-ts4800
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- const: fsl,imx51
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@ -106,6 +111,8 @@ properties:
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- description: i.MX6Q based Boards
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items:
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- enum:
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- armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM
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- armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board
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- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
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- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
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- fsl,imx6q-arm2
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@ -114,6 +121,11 @@ properties:
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- fsl,imx6q-sabresd
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- technologic,imx6q-ts4900
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- technologic,imx6q-ts7970
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- toradex,apalis_imx6q # Apalis iMX6 Module
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- toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board
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- toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora
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- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1
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- variscite,dt6customboard
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- const: fsl,imx6q
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- description: i.MX6QP based Boards
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@ -126,6 +138,8 @@ properties:
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- description: i.MX6DL based Boards
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items:
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- enum:
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- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
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- armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board
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- eckelmann,imx6dl-ci4x10
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- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
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- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
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@ -133,6 +147,8 @@ properties:
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- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
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- technologic,imx6dl-ts4900
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- technologic,imx6dl-ts7970
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- toradex,colibri_imx6dl # Colibri iMX6 Module
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- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3
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- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
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- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
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- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
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@ -148,6 +164,7 @@ properties:
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items:
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- enum:
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- fsl,imx6sll-evk
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- kobo,clarahd
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- const: fsl,imx6sll
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- description: i.MX6SX based Boards
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@ -160,8 +177,11 @@ properties:
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- description: i.MX6UL based Boards
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items:
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- enum:
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- armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
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- armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
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- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
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- kontron,imx6ul-n6310-som # Kontron N6310 SOM
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- kontron,imx6ul-n6311-som # Kontron N6311 SOM
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- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6310 S Board
|
||||
@ -170,6 +190,12 @@ properties:
|
||||
- const: kontron,imx6ul-n6310-som
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6311 S Board
|
||||
items:
|
||||
- const: kontron,imx6ul-n6311-s
|
||||
- const: kontron,imx6ul-n6311-som
|
||||
- const: fsl,imx6ul
|
||||
|
||||
- description: Kontron N6310 S 43 Board
|
||||
items:
|
||||
- const: kontron,imx6ul-n6310-s-43
|
||||
@ -180,7 +206,18 @@ properties:
|
||||
- description: i.MX6ULL based Boards
|
||||
items:
|
||||
- enum:
|
||||
- armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
|
||||
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
|
||||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: Kontron N6411 S Board
|
||||
items:
|
||||
- const: kontron,imx6ull-n6411-s
|
||||
- const: kontron,imx6ull-n6411-som
|
||||
- const: fsl,imx6ull
|
||||
|
||||
- description: i.MX6ULZ based Boards
|
||||
@ -193,6 +230,8 @@ properties:
|
||||
- description: i.MX7S based Boards
|
||||
items:
|
||||
- enum:
|
||||
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
|
||||
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
|
||||
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
|
||||
- const: fsl,imx7s
|
||||
|
||||
@ -201,6 +240,10 @@ properties:
|
||||
- enum:
|
||||
- fsl,imx7d-sdb # i.MX7 SabreSD Board
|
||||
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
|
||||
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
|
||||
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
|
||||
- toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
|
||||
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
|
||||
- zii,imx7d-rmu2 # ZII RMU2 Board
|
||||
- zii,imx7d-rpu2 # ZII RPU2 Board
|
||||
@ -233,6 +276,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: i.MX8MQ based Boards
|
||||
@ -250,6 +294,8 @@ properties:
|
||||
- enum:
|
||||
- einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board
|
||||
- fsl,imx8qxp-mek # i.MX8QXP MEK Board
|
||||
- toradex,colibri-imx8x # Colibri iMX8X Module
|
||||
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description:
|
||||
@ -267,6 +313,10 @@ properties:
|
||||
- fsl,vf600
|
||||
- fsl,vf610
|
||||
- fsl,vf610m4
|
||||
- toradex,vf500-colibri_vf50 # Colibri VF50 Module
|
||||
- toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board
|
||||
- toradex,vf610-colibri_vf61 # Colibri VF61 Module
|
||||
- toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board
|
||||
|
||||
- description: ZII's VF610 based Boards
|
||||
items:
|
||||
@ -335,4 +385,10 @@ properties:
|
||||
- fsl,ls2088a-rdb
|
||||
- const: fsl,ls2088a
|
||||
|
||||
- description: S32V234 based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
|
||||
- const: fsl,s32v234
|
||||
|
||||
...
|
||||
|
||||
@ -1,15 +1,15 @@
|
||||
Marvell Armada AP806 System Controller
|
||||
Marvell Armada AP80x System Controller
|
||||
======================================
|
||||
|
||||
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
|
||||
SoCs. It contains system controllers, which provide several registers
|
||||
giving access to numerous features: clocks, pin-muxing and many other
|
||||
SoC configuration items. This DT binding allows to describe these
|
||||
system controllers.
|
||||
The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
|
||||
7K/8K/931x SoCs. It contains system controllers, which provide several
|
||||
registers giving access to numerous features: clocks, pin-muxing and
|
||||
many other SoC configuration items. This DT binding allows to describe
|
||||
these system controllers.
|
||||
|
||||
For the top level node:
|
||||
- compatible: must be: "syscon", "simple-mfd";
|
||||
- reg: register area of the AP806 system controller
|
||||
- reg: register area of the AP80x system controller
|
||||
|
||||
SYSTEM CONTROLLER 0
|
||||
===================
|
||||
@ -1,24 +0,0 @@
|
||||
Marvell Armada 7K/8K Platforms Device Tree Bindings
|
||||
---------------------------------------------------
|
||||
|
||||
Boards using a SoC of the Marvell Armada 7K or 8K families must carry
|
||||
the following root node property:
|
||||
|
||||
- compatible, with one of the following values:
|
||||
|
||||
- "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 7020
|
||||
|
||||
- "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 7040
|
||||
|
||||
- "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 8020
|
||||
|
||||
- "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
|
||||
when the SoC being used is the Armada 8040
|
||||
|
||||
Example:
|
||||
|
||||
compatible = "marvell,armada7040-db", "marvell,armada7040",
|
||||
"marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
61
Bindings/arm/marvell/armada-7k-8k.yaml
Normal file
61
Bindings/arm/marvell/armada-7k-8k.yaml
Normal file
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0+ OR X11)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 7K/8K Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: Armada 7020 SoC
|
||||
items:
|
||||
- const: marvell,armada7020
|
||||
- const: marvell,armada-ap806-dual
|
||||
- const: marvell,armada-ap806
|
||||
|
||||
- description: Armada 7040 SoC
|
||||
items:
|
||||
- const: marvell,armada7040
|
||||
- const: marvell,armada-ap806-quad
|
||||
- const: marvell,armada-ap806
|
||||
|
||||
- description: Armada 8020 SoC
|
||||
items:
|
||||
- const: marvell,armada8020
|
||||
- const: marvell,armada-ap806-dual
|
||||
- const: marvell,armada-ap806
|
||||
|
||||
- description: Armada 8040 SoC
|
||||
items:
|
||||
- const: marvell,armada8040
|
||||
- const: marvell,armada-ap806-quad
|
||||
- const: marvell,armada-ap806
|
||||
|
||||
- description: Armada CN9130 SoC with no external CP
|
||||
items:
|
||||
- const: marvell,cn9130
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
- description: Armada CN9131 SoC with one external CP
|
||||
items:
|
||||
- const: marvell,cn9131
|
||||
- const: marvell,cn9130
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
- description: Armada CN9132 SoC with two external CPs
|
||||
items:
|
||||
- const: marvell,cn9132
|
||||
- const: marvell,cn9131
|
||||
- const: marvell,cn9130
|
||||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
@ -1,14 +0,0 @@
|
||||
Marvell Platforms Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
|
||||
PXA168 Aspenite Board
|
||||
Required root node properties:
|
||||
- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
|
||||
|
||||
PXA910 DKB Board
|
||||
Required root node properties:
|
||||
- compatible = "mrvl,pxa910-dkb";
|
||||
|
||||
MMP2 Brownstone Board
|
||||
Required root node properties:
|
||||
- compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
|
||||
35
Bindings/arm/mrvl/mrvl.yaml
Normal file
35
Bindings/arm/mrvl/mrvl.yaml
Normal file
@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Lubomir Rintel <lkundrak@v3.sk>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: PXA168 Aspenite Board
|
||||
items:
|
||||
- enum:
|
||||
- mrvl,pxa168-aspenite
|
||||
- const: mrvl,pxa168
|
||||
- description: PXA910 DKB Board
|
||||
items:
|
||||
- enum:
|
||||
- mrvl,pxa910-dkb
|
||||
- const: mrvl,pxa910
|
||||
- description: MMP2 based boards
|
||||
items:
|
||||
- enum:
|
||||
- mrvl,mmp2-brownstone
|
||||
- const: mrvl,mmp2
|
||||
- description: MMP3 based boards
|
||||
items:
|
||||
- const: mrvl,mmp3
|
||||
...
|
||||
@ -1,41 +0,0 @@
|
||||
== Introduction==
|
||||
|
||||
LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
|
||||
that can be shared by multiple clients. Clients here are different cores in the
|
||||
SOC, the idea is to minimize the local caches at the clients and migrate to
|
||||
common pool of memory. Cache memory is divided into partitions called slices
|
||||
which are assigned to clients. Clients can query the slice details, activate
|
||||
and deactivate them.
|
||||
|
||||
Properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,sdm845-llcc"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value Type: <prop-encoded-array>
|
||||
Definition: The first element specifies the llcc base start address and
|
||||
the size of the register region. The second element specifies
|
||||
the llcc broadcast base address and size of the register region.
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value Type: <stringlist>
|
||||
Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Definition: The interrupt is associated with the llcc edac device.
|
||||
It's used for llcc cache single and double bit error detection
|
||||
and reporting.
|
||||
|
||||
Example:
|
||||
|
||||
cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
55
Bindings/arm/msm/qcom,llcc.yaml
Normal file
55
Bindings/arm/msm/qcom,llcc.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Last Level Cache Controller
|
||||
|
||||
maintainers:
|
||||
- Rishabh Bhatnagar <rishabhb@codeaurora.org>
|
||||
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
|
||||
|
||||
description: |
|
||||
LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
|
||||
that can be shared by multiple clients. Clients here are different cores in the
|
||||
SoC, the idea is to minimize the local caches at the clients and migrate to
|
||||
common pool of memory. Cache memory is divided into partitions called slices
|
||||
which are assigned to clients. Clients can query the slice details, activate
|
||||
and deactivate them.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sdm845-llcc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC base register region
|
||||
- description: LLCC broadcast base register region
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc_base
|
||||
- const: llcc_broadcast_base
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
cache-controller@1100000 {
|
||||
compatible = "qcom,sdm845-llcc";
|
||||
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
|
||||
reg-names = "llcc_base", "llcc_broadcast_base";
|
||||
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
@ -43,7 +43,7 @@ SoC Families:
|
||||
|
||||
- OMAP2 generic - defaults to OMAP2420
|
||||
compatible = "ti,omap2"
|
||||
- OMAP3 generic - defaults to OMAP3430
|
||||
- OMAP3 generic
|
||||
compatible = "ti,omap3"
|
||||
- OMAP4 generic - defaults to OMAP4430
|
||||
compatible = "ti,omap4"
|
||||
@ -51,6 +51,8 @@ SoC Families:
|
||||
compatible = "ti,omap5"
|
||||
- DRA7 generic - defaults to DRA742
|
||||
compatible = "ti,dra7"
|
||||
- AM33x generic
|
||||
compatible = "ti,am33xx"
|
||||
- AM43x generic - defaults to AM4372
|
||||
compatible = "ti,am43"
|
||||
|
||||
@ -63,12 +65,14 @@ SoCs:
|
||||
|
||||
- OMAP3430
|
||||
compatible = "ti,omap3430", "ti,omap3"
|
||||
legacy: "ti,omap34xx" - please do not use any more
|
||||
- AM3517
|
||||
compatible = "ti,am3517", "ti,omap3"
|
||||
- OMAP3630
|
||||
compatible = "ti,omap36xx", "ti,omap3"
|
||||
- AM33xx
|
||||
compatible = "ti,am33xx", "ti,omap3"
|
||||
compatible = "ti,omap3630", "ti,omap3"
|
||||
legacy: "ti,omap36xx" - please do not use any more
|
||||
- AM335x
|
||||
compatible = "ti,am33xx"
|
||||
|
||||
- OMAP4430
|
||||
compatible = "ti,omap4430", "ti,omap4"
|
||||
@ -110,19 +114,19 @@ SoCs:
|
||||
- AM4372
|
||||
compatible = "ti,am4372", "ti,am43"
|
||||
|
||||
Boards:
|
||||
Boards (incomplete list of examples):
|
||||
|
||||
- OMAP3 BeagleBoard : Low cost community board
|
||||
compatible = "ti,omap3-beagle", "ti,omap3"
|
||||
compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
|
||||
|
||||
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
|
||||
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3"
|
||||
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"
|
||||
|
||||
- OMAP4 SDP : Software Development Board
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430"
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"
|
||||
|
||||
- OMAP4 PandaBoard : Low cost community board
|
||||
compatible = "ti,omap4-panda", "ti,omap4430"
|
||||
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"
|
||||
|
||||
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
|
||||
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
|
||||
@ -134,16 +138,16 @@ Boards:
|
||||
compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
|
||||
|
||||
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
|
||||
compatible = "ti,omap3-evm", "ti,omap3"
|
||||
compatible = "ti,omap3-evm", "ti,omap3630", "ti,omap3"
|
||||
|
||||
- AM335X EVM : Software Development Board for AM335x
|
||||
compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
|
||||
compatible = "ti,am335x-evm", "ti,am33xx"
|
||||
|
||||
- AM335X Bone : Low cost community board
|
||||
compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
|
||||
compatible = "ti,am335x-bone", "ti,am33xx"
|
||||
|
||||
- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
|
||||
compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3"
|
||||
compatible = "ti,am3359-icev2", "ti,am33xx"
|
||||
|
||||
- AM335X OrionLXm : Substation Automation Platform
|
||||
compatible = "novatech,am335x-lxm", "ti,am33xx"
|
||||
|
||||
29
Bindings/arm/omap/prm-inst.txt
Normal file
29
Bindings/arm/omap/prm-inst.txt
Normal file
@ -0,0 +1,29 @@
|
||||
OMAP PRM instance bindings
|
||||
|
||||
Power and Reset Manager is an IP block on OMAP family of devices which
|
||||
handle the power domains and their current state, and provide reset
|
||||
handling for the domains and/or separate IP blocks under the power domain
|
||||
hierarchy.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain one of the following:
|
||||
"ti,am3-prm-inst"
|
||||
"ti,am4-prm-inst"
|
||||
"ti,omap4-prm-inst"
|
||||
"ti,omap5-prm-inst"
|
||||
"ti,dra7-prm-inst"
|
||||
and additionally must contain:
|
||||
"ti,omap-prm-inst"
|
||||
- reg: Contains PRM instance register address range
|
||||
(base address and length)
|
||||
|
||||
Optional properties:
|
||||
- #reset-cells: Should be 1 if the PRM instance in question supports resets.
|
||||
|
||||
Example:
|
||||
|
||||
prm_dsp2: prm@1b00 {
|
||||
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1b00 0x40>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -13,11 +13,24 @@ properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
# RTD1295 SoC based boards
|
||||
items:
|
||||
oneOf:
|
||||
# RTD1293 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
- mele,v9
|
||||
- probox2,ava
|
||||
- zidoo,x9s
|
||||
- synology,ds418j # Synology DiskStation DS418j
|
||||
- const: realtek,rtd1293
|
||||
|
||||
# RTD1295 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
- mele,v9 # MeLE V9
|
||||
- probox2,ava # ProBox2 AVA
|
||||
- zidoo,x9s # Zidoo X9S
|
||||
- const: realtek,rtd1295
|
||||
|
||||
# RTD1296 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
- synology,ds418 # Synology DiskStation DS418
|
||||
- const: realtek,rtd1296
|
||||
...
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
Renesas Product Register
|
||||
|
||||
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
|
||||
allows to retrieve SoC product and revision information. If present, a device
|
||||
node for this register should be added.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
"renesas,prr"
|
||||
"renesas,bsid"
|
||||
- reg: Base address and length of the register block.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
35
Bindings/arm/renesas,prr.yaml
Normal file
35
Bindings/arm/renesas,prr.yaml
Normal file
@ -0,0 +1,35 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/renesas,prr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Product Register
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
- Magnus Damm <magnus.damm@gmail.com>
|
||||
|
||||
description: |
|
||||
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
|
||||
Register that allows to retrieve SoC product and revision information.
|
||||
If present, a device node for this register should be added.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,prr
|
||||
- renesas,bsid
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
@ -116,6 +116,18 @@ properties:
|
||||
- const: hoperun,hihope-rzg2m
|
||||
- const: renesas,r8a774a1
|
||||
|
||||
- description: RZ/G2N (R8A774B1)
|
||||
items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2n # HopeRun HiHope RZ/G2N platform
|
||||
- const: renesas,r8a774b1
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
|
||||
- const: hoperun,hihope-rzg2n
|
||||
- const: renesas,r8a774b1
|
||||
|
||||
- description: RZ/G2E (R8A774C0)
|
||||
items:
|
||||
- enum:
|
||||
@ -193,15 +205,23 @@ properties:
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
|
||||
- const: renesas,r8a7796
|
||||
|
||||
- description: R-Car M3-W+ (R8A77961)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012SA5A)
|
||||
- const: renesas,r8a77961
|
||||
|
||||
- description: Kingfisher (SBEV-RCAR-KF-M03)
|
||||
items:
|
||||
- const: shimafuji,kingfisher
|
||||
- enum:
|
||||
- renesas,h3ulcb
|
||||
- renesas,m3ulcb
|
||||
- renesas,m3nulcb
|
||||
- enum:
|
||||
- renesas,r8a7795
|
||||
- renesas,r8a7796
|
||||
- renesas,r8a77965
|
||||
|
||||
- description: R-Car M3-N (R8A77965)
|
||||
items:
|
||||
|
||||
@ -40,6 +40,11 @@ properties:
|
||||
- const: asus,rk3288-tinker-s
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Beelink A1
|
||||
items:
|
||||
- const: azw,beelink-a1
|
||||
- const: rockchip,rk3328
|
||||
|
||||
- description: bq Curie 2 tablet
|
||||
items:
|
||||
- const: mundoreader,bq-curie2
|
||||
@ -82,6 +87,11 @@ properties:
|
||||
- const: firefly,firefly-rk3399
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Firefly ROC-RK3308-CC
|
||||
items:
|
||||
- const: firefly,roc-rk3308-cc
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Firefly roc-rk3328-cc
|
||||
items:
|
||||
- const: firefly,roc-rk3328-cc
|
||||
@ -89,7 +99,9 @@ properties:
|
||||
|
||||
- description: Firefly ROC-RK3399-PC
|
||||
items:
|
||||
- const: firefly,roc-rk3399-pc
|
||||
- enum:
|
||||
- firefly,roc-rk3399-pc
|
||||
- firefly,roc-rk3399-pc-mezzanine
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: FriendlyElec NanoPi4 series boards
|
||||
@ -464,6 +476,11 @@ properties:
|
||||
- rockchip,rk3288-evb-rk808
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Rockchip RK3308 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3308-evb
|
||||
- const: rockchip,rk3308
|
||||
|
||||
- description: Rockchip RK3328 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3328-evb
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
SAMSUNG Exynos SoCs Chipid driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should at least contain "samsung,exynos4210-chipid".
|
||||
|
||||
- reg: offset and length of the register set
|
||||
|
||||
Example:
|
||||
chipid@10000000 {
|
||||
compatible = "samsung,exynos4210-chipid";
|
||||
reg = <0x10000000 0x100>;
|
||||
};
|
||||
39
Bindings/arm/samsung/exynos-chipid.yaml
Normal file
39
Bindings/arm/samsung/exynos-chipid.yaml
Normal file
@ -0,0 +1,39 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC series Chipid driver
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,exynos4210-chipid
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
samsung,asv-bin:
|
||||
description:
|
||||
Adaptive Supply Voltage bin selection. This can be used
|
||||
to determine the ASV bin of an SoC if respective information
|
||||
is missing in the CHIPID registers or in the OTP memory.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
chipid@10000000 {
|
||||
compatible = "samsung,exynos4210-chipid";
|
||||
reg = <0x10000000 0x100>;
|
||||
samsung,asv-bin = <2>;
|
||||
};
|
||||
@ -1,72 +0,0 @@
|
||||
SAMSUNG Exynos SoC series PMU Registers
|
||||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
|
||||
- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
|
||||
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
|
||||
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
|
||||
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
|
||||
- "samsung,exynos5410-pmu" - for Exynos5410 SoC,
|
||||
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
|
||||
- "samsung,exynos5433-pmu" - for Exynos5433 SoC.
|
||||
- "samsung,exynos7-pmu" - for Exynos7 SoC.
|
||||
second value must be always "syscon".
|
||||
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
- #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
|
||||
The single specifier cell is used as index to list of clocks
|
||||
provided by PMU, which is currently:
|
||||
0 : SoC clock output (CLKOUT pin)
|
||||
|
||||
- clock-names : list of clock names for particular CLKOUT mux inputs in
|
||||
following format:
|
||||
"clkoutN", where N is a decimal number corresponding to
|
||||
CLKOUT mux control bits value for given input, e.g.
|
||||
"clkout0", "clkout7", "clkout15".
|
||||
|
||||
- clocks : list of phandles and specifiers to all input clocks listed in
|
||||
clock-names property.
|
||||
|
||||
Optional properties:
|
||||
|
||||
Some PMUs are capable of behaving as an interrupt controller (mostly
|
||||
to wake up a suspended PMU). In which case, they can have the
|
||||
following properties:
|
||||
|
||||
- interrupt-controller: indicate that said PMU is an interrupt controller
|
||||
|
||||
- #interrupt-cells: must be identical to the that of the parent interrupt
|
||||
controller.
|
||||
|
||||
|
||||
Optional nodes:
|
||||
|
||||
- nodes defining the restart and poweroff syscon children
|
||||
|
||||
|
||||
Example :
|
||||
pmu_system_controller: system-controller@10040000 {
|
||||
compatible = "samsung,exynos5250-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
||||
"clkout4", "clkout8", "clkout9";
|
||||
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
||||
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
||||
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
|
||||
<&clock CLK_XUSBXTI>;
|
||||
};
|
||||
|
||||
Example of clock consumer :
|
||||
|
||||
usb3503: usb3503@8 {
|
||||
/* ... */
|
||||
clock-names = "refclk";
|
||||
clocks = <&pmu_system_controller 0>;
|
||||
/* ... */
|
||||
};
|
||||
105
Bindings/arm/samsung/pmu.yaml
Normal file
105
Bindings/arm/samsung/pmu.yaml
Normal file
@ -0,0 +1,105 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC series Power Management Unit (PMU)
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
# Custom select to avoid matching all nodes with 'syscon'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4412-pmu
|
||||
- samsung,exynos5250-pmu
|
||||
- samsung,exynos5260-pmu
|
||||
- samsung,exynos5410-pmu
|
||||
- samsung,exynos5420-pmu
|
||||
- samsung,exynos5433-pmu
|
||||
- samsung,exynos7-pmu
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4412-pmu
|
||||
- samsung,exynos5250-pmu
|
||||
- samsung,exynos5260-pmu
|
||||
- samsung,exynos5410-pmu
|
||||
- samsung,exynos5420-pmu
|
||||
- samsung,exynos5433-pmu
|
||||
- samsung,exynos7-pmu
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clock-names:
|
||||
description:
|
||||
List of clock names for particular CLKOUT mux inputs
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
items:
|
||||
pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$'
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
interrupt-controller:
|
||||
description:
|
||||
Some PMUs are capable of behaving as an interrupt controller (mostly
|
||||
to wake up a suspended PMU).
|
||||
|
||||
'#interrupt-cells':
|
||||
description:
|
||||
Must be identical to the that of the parent interrupt controller.
|
||||
const: 3
|
||||
|
||||
syscon-poweroff:
|
||||
$ref: "../../power/reset/syscon-poweroff.yaml#"
|
||||
type: object
|
||||
description:
|
||||
Node for power off method
|
||||
|
||||
syscon-reboot:
|
||||
$ref: "../../power/reset/syscon-reboot.yaml#"
|
||||
type: object
|
||||
description:
|
||||
Node for reboot method
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos5250.h>
|
||||
|
||||
pmu_system_controller: system-controller@10040000 {
|
||||
compatible = "samsung,exynos5250-pmu", "syscon";
|
||||
reg = <0x10040000 0x5000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "clkout16";
|
||||
clocks = <&clock CLK_FIN_PLL>;
|
||||
};
|
||||
@ -1,83 +0,0 @@
|
||||
* Samsung's Exynos and S5P SoC based boards
|
||||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following.
|
||||
- "samsung,aries" - for S5PV210-based Samsung Aries board.
|
||||
- "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
|
||||
- "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
|
||||
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
|
||||
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
|
||||
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
|
||||
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
|
||||
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
|
||||
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
|
||||
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
|
||||
- "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
|
||||
- "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
|
||||
- "samsung,midas" - for Exynos4412-based Samsung Midas board.
|
||||
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
|
||||
- "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
|
||||
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
|
||||
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
|
||||
- "samsung,xyref5260" - for Exynos5260-based Samsung board.
|
||||
- "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
|
||||
- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
|
||||
- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
|
||||
- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
|
||||
|
||||
* Other companies Exynos SoC based
|
||||
* FriendlyARM
|
||||
- "friendlyarm,tiny4412" - for Exynos4412-based FriendlyARM
|
||||
TINY4412 board.
|
||||
* TOPEET
|
||||
- "topeet,itop4412-elite" - for Exynos4412-based TOPEET
|
||||
Elite base board.
|
||||
|
||||
* Google
|
||||
- "google,pi" - for Exynos5800-based Google Peach Pi
|
||||
Rev 10+ board,
|
||||
also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
|
||||
"google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
|
||||
"google,pi-rev10", "google,peach".
|
||||
|
||||
- "google,pit" - for Exynos5420-based Google Peach Pit
|
||||
Rev 6+ (Exynos5420),
|
||||
also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
|
||||
"google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
|
||||
"google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
|
||||
"google,pit-rev7", "google,pit-rev6", "google,peach".
|
||||
|
||||
- "google,snow-rev4" - for Exynos5250-based Google Snow board,
|
||||
also: "google,snow"
|
||||
- "google,snow-rev5" - for Exynos5250-based Google Snow
|
||||
Rev 5+ board.
|
||||
- "google,spring" - for Exynos5250-based Google Spring board.
|
||||
|
||||
* Hardkernel
|
||||
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
|
||||
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
|
||||
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
|
||||
- "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
|
||||
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
|
||||
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
|
||||
Odroid XU3 Lite board.
|
||||
- "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
|
||||
- "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1.
|
||||
|
||||
* Insignal
|
||||
- "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
|
||||
- "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
|
||||
Octa board.
|
||||
- "insignal,origen" - for Exynos4210-based Insignal Origen board.
|
||||
- "insignal,origen4412" - for Exynos4412-based Insignal Origen board.
|
||||
|
||||
|
||||
Optional nodes:
|
||||
- firmware node, specifying presence and type of secure firmware:
|
||||
- compatible: only "samsung,secure-firmware" is currently supported
|
||||
- reg: address of non-secure SYSRAM used for communication with firmware
|
||||
|
||||
firmware@203f000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0203F000 0x1000>;
|
||||
};
|
||||
181
Bindings/arm/samsung/samsung-boards.yaml
Normal file
181
Bindings/arm/samsung/samsung-boards.yaml
Normal file
@ -0,0 +1,181 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/samsung-boards.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos and S5P SoC based boards
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: S5PV210 based boards
|
||||
items:
|
||||
- enum:
|
||||
- aesop,torbreck # aESOP Torbreck based on S5PV210
|
||||
- samsung,aquila # Samsung Aquila based on S5PC110
|
||||
- samsung,goni # Samsung Goni based on S5PC110
|
||||
- yic,smdkc110 # YIC System SMDKC110 based on S5PC110
|
||||
- yic,smdkv210 # YIC System SMDKV210 based on S5PV210
|
||||
- const: samsung,s5pv210
|
||||
|
||||
- description: S5PV210 based Aries boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,fascinate4g # Samsung Galaxy S Fascinate 4G (SGH-T959P)
|
||||
- samsung,galaxys # Samsung Galaxy S (i9000)
|
||||
- const: samsung,aries
|
||||
- const: samsung,s5pv210
|
||||
|
||||
- description: Exynos3250 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,monk # Samsung Simband
|
||||
- samsung,rinato # Samsung Gear2
|
||||
- const: samsung,exynos3250
|
||||
- const: samsung,exynos3
|
||||
|
||||
- description: Samsung ARTIK5 boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,artik5-eval # Samsung ARTIK5 eval board
|
||||
- const: samsung,artik5 # Samsung ARTIK5 module
|
||||
- const: samsung,exynos3250
|
||||
- const: samsung,exynos3
|
||||
|
||||
- description: Exynos4210 based boards
|
||||
items:
|
||||
- enum:
|
||||
- insignal,origen # Insignal Origen
|
||||
- samsung,smdkv310 # Samsung SMDKV310 eval
|
||||
- samsung,trats # Samsung Tizen Reference
|
||||
- samsung,universal_c210 # Samsung C210
|
||||
- const: samsung,exynos4210
|
||||
- const: samsung,exynos4
|
||||
|
||||
- description: Exynos4412 based boards
|
||||
items:
|
||||
- enum:
|
||||
- friendlyarm,tiny4412 # FriendlyARM TINY4412
|
||||
- hardkernel,odroid-u3 # Hardkernel Odroid U3
|
||||
- hardkernel,odroid-x # Hardkernel Odroid X
|
||||
- hardkernel,odroid-x2 # Hardkernel Odroid X2
|
||||
- insignal,origen4412 # Insignal Origen
|
||||
- samsung,smdk4412 # Samsung SMDK4412 eval
|
||||
- topeet,itop4412-elite # TOPEET Elite base
|
||||
- const: samsung,exynos4412
|
||||
- const: samsung,exynos4
|
||||
|
||||
- description: Samsung Midas family boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,i9300 # Samsung GT-I9300
|
||||
- samsung,i9305 # Samsung GT-I9305
|
||||
- samsung,n710x # Samsung GT-N7100/GT-N7105
|
||||
- samsung,trats2 # Samsung Tizen Reference
|
||||
- const: samsung,midas
|
||||
- const: samsung,exynos4412
|
||||
- const: samsung,exynos4
|
||||
|
||||
- description: Exynos5250 based boards
|
||||
items:
|
||||
- enum:
|
||||
- google,snow-rev5 # Google Snow Rev 5+
|
||||
- google,spring # Google Spring
|
||||
- insignal,arndale # Insignal Arndale
|
||||
- samsung,smdk5250 # Samsung SMDK5250 eval
|
||||
- const: samsung,exynos5250
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Google Snow Boards (Rev 4+)
|
||||
items:
|
||||
- const: google,snow-rev4
|
||||
- const: google,snow
|
||||
- const: samsung,exynos5250
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5260 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,xyref5260 # Samsung Xyref5260 eval
|
||||
- const: samsung,exynos5260
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5410 based boards
|
||||
items:
|
||||
- enum:
|
||||
- hardkernel,odroid-xu # Hardkernel Odroid XU
|
||||
- samsung,smdk5410 # Samsung SMDK5410 eval
|
||||
- const: samsung,exynos5410
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5420 based boards
|
||||
items:
|
||||
- enum:
|
||||
- insignal,arndale-octa # Insignal Arndale Octa
|
||||
- samsung,smdk5420 # Samsung SMDK5420 eval
|
||||
- const: samsung,exynos5420
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Google Peach Pit Boards (Rev 6+)
|
||||
items:
|
||||
- const: google,pit-rev16
|
||||
- const: google,pit-rev15
|
||||
- const: google,pit-rev14
|
||||
- const: google,pit-rev13
|
||||
- const: google,pit-rev12
|
||||
- const: google,pit-rev11
|
||||
- const: google,pit-rev10
|
||||
- const: google,pit-rev9
|
||||
- const: google,pit-rev8
|
||||
- const: google,pit-rev7
|
||||
- const: google,pit-rev6
|
||||
- const: google,pit
|
||||
- const: google,peach
|
||||
- const: samsung,exynos5420
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5800 based boards
|
||||
items:
|
||||
- enum:
|
||||
- hardkernel,odroid-xu3 # Hardkernel Odroid XU3
|
||||
- hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite
|
||||
- hardkernel,odroid-xu4 # Hardkernel Odroid XU4
|
||||
- hardkernel,odroid-hc1 # Hardkernel Odroid HC1
|
||||
- const: samsung,exynos5800
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Google Peach Pi Boards (Rev 10+)
|
||||
items:
|
||||
- const: google,pi-rev16
|
||||
- const: google,pi-rev15
|
||||
- const: google,pi-rev14
|
||||
- const: google,pi-rev13
|
||||
- const: google,pi-rev12
|
||||
- const: google,pi-rev11
|
||||
- const: google,pi-rev10
|
||||
- const: google,pi
|
||||
- const: google,peach
|
||||
- const: samsung,exynos5800
|
||||
- const: samsung,exynos5
|
||||
|
||||
- description: Exynos5433 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,tm2 # Samsung TM2
|
||||
- samsung,tm2e # Samsung TM2E
|
||||
- const: samsung,exynos5433
|
||||
|
||||
- description: Exynos7 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
|
||||
- const: samsung,exynos7
|
||||
|
||||
required:
|
||||
- compatible
|
||||
31
Bindings/arm/samsung/samsung-secure-firmware.yaml
Normal file
31
Bindings/arm/samsung/samsung-secure-firmware.yaml
Normal file
@ -0,0 +1,31 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos Secure Firmware
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,secure-firmware
|
||||
|
||||
reg:
|
||||
description:
|
||||
Address of non-secure SYSRAM used for communication with firmware.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
firmware@203f000 {
|
||||
compatible = "samsung,secure-firmware";
|
||||
reg = <0x0203f000 0x1000>;
|
||||
};
|
||||
@ -1,19 +0,0 @@
|
||||
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
|
||||
- "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
|
||||
second value must be always "syscon".
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
Example:
|
||||
syscon@10010000 {
|
||||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
syscon@10050000 {
|
||||
compatible = "samsung,exynos5-sysreg", "syscon";
|
||||
reg = <0x10050000 0x5000>;
|
||||
};
|
||||
45
Bindings/arm/samsung/sysreg.yaml
Normal file
45
Bindings/arm/samsung/sysreg.yaml
Normal file
@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
# Custom select to avoid matching all nodes with 'syscon'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos4-sysreg
|
||||
- samsung,exynos5-sysreg
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
allOf:
|
||||
- items:
|
||||
- enum:
|
||||
- samsung,exynos4-sysreg
|
||||
- samsung,exynos5-sysreg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
examples:
|
||||
- |
|
||||
syscon@10010000 {
|
||||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
syscon@10050000 {
|
||||
compatible = "samsung,exynos5-sysreg", "syscon";
|
||||
reg = <0x10050000 0x5000>;
|
||||
};
|
||||
@ -1,14 +0,0 @@
|
||||
Spreadtrum SoC Platforms Device Tree Bindings
|
||||
----------------------------------------------------
|
||||
|
||||
SC9836 openphone Board
|
||||
Required root node properties:
|
||||
- compatible = "sprd,sc9836-openphone", "sprd,sc9836";
|
||||
|
||||
SC9860 SoC
|
||||
Required root node properties:
|
||||
- compatible = "sprd,sc9860"
|
||||
|
||||
SP9860G 3GFHD Board
|
||||
Required root node properties:
|
||||
- compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
|
||||
33
Bindings/arm/sprd.yaml
Normal file
33
Bindings/arm/sprd.yaml
Normal file
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2019 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/sprd.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Unisoc platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,sc9836-openphone
|
||||
- const: sprd,sc9836
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,sp9860g-1h10
|
||||
- const: sprd,sc9860
|
||||
- items:
|
||||
- enum:
|
||||
- sprd,sp9863a-1h10
|
||||
- const: sprd,sc9863a
|
||||
|
||||
...
|
||||
@ -13,19 +13,38 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f429i-disco
|
||||
- st,stm32429i-eval
|
||||
- const: st,stm32f429
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f469i-disco
|
||||
- const: st,stm32f469
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f746-disco
|
||||
- st,stm32746g-eval
|
||||
- const: st,stm32f746
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32f769-disco
|
||||
- const: st,stm32f769
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32h743i-disco
|
||||
- st,stm32h743i-eval
|
||||
- const: st,stm32h743
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- st,stm32mp157c-ed1
|
||||
- st,stm32mp157a-dk1
|
||||
- st,stm32mp157c-dk2
|
||||
|
||||
- const: st,stm32mp157
|
||||
- items:
|
||||
- const: st,stm32mp157c-ev1
|
||||
- const: st,stm32mp157c-ed1
|
||||
- const: st,stm32mp157
|
||||
...
|
||||
|
||||
@ -8,7 +8,7 @@ title: Allwinner platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
@ -211,6 +211,11 @@ properties:
|
||||
- const: friendlyarm,nanopi-a64
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: FriendlyARM NanoPi Duo2
|
||||
items:
|
||||
- const: friendlyarm,nanopi-duo2
|
||||
- const: allwinner,sun8i-h3
|
||||
|
||||
- description: FriendlyARM NanoPi M1
|
||||
items:
|
||||
- const: friendlyarm,nanopi-m1
|
||||
|
||||
@ -1,44 +0,0 @@
|
||||
Allwinner SRAM for smp bringup:
|
||||
------------------------------------------------
|
||||
|
||||
Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
|
||||
primary core (cpu0). Once the core gets powered up it checks if a magic
|
||||
value is set at a specific location. If it is then the BROM will jump
|
||||
to the software entry address, instead of executing a standard boot.
|
||||
|
||||
Therefore a reserved section sub-node has to be added to the mmio-sram
|
||||
declaration.
|
||||
|
||||
Note that this is separate from the Allwinner SRAM controller found in
|
||||
../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
|
||||
any device.
|
||||
|
||||
Also there are no "secure-only" properties. The implementation should
|
||||
check if this SRAM is usable first.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : depending on the SoC this should be one of:
|
||||
"allwinner,sun9i-a80-smp-sram"
|
||||
|
||||
The rest of the properties should follow the generic mmio-sram discription
|
||||
found in ../../misc/sram.txt
|
||||
|
||||
Example:
|
||||
|
||||
sram_b: sram@20000 {
|
||||
/* 256 KiB secure SRAM at 0x20000 */
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00020000 0x40000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x00020000 0x40000>;
|
||||
|
||||
smp-sram@1000 {
|
||||
/*
|
||||
* This is checked by BROM to determine if
|
||||
* cpu0 should jump to SMP entry vector
|
||||
*/
|
||||
compatible = "allwinner,sun9i-a80-smp-sram";
|
||||
reg = <0x1000 0x8>;
|
||||
};
|
||||
};
|
||||
@ -8,6 +8,7 @@ bus.
|
||||
Required properties:
|
||||
- compatible: Must be one of:
|
||||
- allwinner,sun5i-a13-mbus
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- reg: Offset and length of the register set for the controller
|
||||
- clocks: phandle to the clock driving the controller
|
||||
- dma-ranges: See section 2.3.9 of the DeviceTree Specification
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain one or more of the following:
|
||||
- "renesas,sata-r8a774b1" for RZ/G2N
|
||||
- "renesas,sata-r8a7779" for R-Car H1
|
||||
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
|
||||
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
|
||||
@ -9,8 +10,10 @@ Required properties:
|
||||
- "renesas,sata-r8a7793" for R-Car M2-N
|
||||
- "renesas,sata-r8a7795" for R-Car H3
|
||||
- "renesas,sata-r8a77965" for R-Car M3-N
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2 compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 compatible device
|
||||
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2
|
||||
compatible device
|
||||
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
|
||||
RZ/G2 compatible device
|
||||
- "renesas,rcar-sata" is deprecated
|
||||
|
||||
When compatible with the generic version nodes
|
||||
|
||||
@ -47,36 +47,6 @@ Example (LS2080A-RDB):
|
||||
reg = <0x3 0 0x10000>;
|
||||
};
|
||||
|
||||
* Freescale BCSR GPIO banks
|
||||
|
||||
Some BCSR registers act as simple GPIO controllers, each such
|
||||
register can be represented by the gpio-controller node.
|
||||
|
||||
Required properities:
|
||||
- compatible : Should be "fsl,<board>-bcsr-gpio".
|
||||
- reg : Should contain the address and the length of the GPIO bank
|
||||
register.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters (currently unused).
|
||||
- gpio-controller : Marks the port as GPIO controller.
|
||||
|
||||
Example:
|
||||
|
||||
bcsr@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8360mds-bcsr";
|
||||
reg = <1 0 0x8000>;
|
||||
ranges = <0 1 0 0x8000>;
|
||||
|
||||
bcsr13: gpio-controller@d {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360mds-bcsr-gpio";
|
||||
reg = <0xd 1>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
* Freescale on-board FPGA connected on I2C bus
|
||||
|
||||
Some Freescale boards like BSC9132QDS have on board FPGA connected on
|
||||
|
||||
@ -8,7 +8,7 @@ title: Allwinner A64 Display Engine Bus Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
|
||||
@ -8,7 +8,7 @@ title: Allwinner A23 RSB Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
|
||||
@ -1,46 +0,0 @@
|
||||
Renesas Bus State Controller (BSC)
|
||||
==================================
|
||||
|
||||
The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
|
||||
Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
|
||||
It provides an external bus for connecting multiple external devices to the
|
||||
SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.
|
||||
|
||||
While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
|
||||
domain, and may have a gateable functional clock.
|
||||
Before a device connected to the BSC can be accessed, the PM domain
|
||||
containing the BSC must be powered on, and the functional clock
|
||||
driving the BSC must be enabled.
|
||||
|
||||
The bindings for the BSC extend the bindings for "simple-pm-bus".
|
||||
|
||||
|
||||
Required properties
|
||||
- compatible: Must contain an SoC-specific value, and "renesas,bsc" and
|
||||
"simple-pm-bus" as fallbacks.
|
||||
SoC-specific values can be:
|
||||
"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
|
||||
"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
|
||||
- #address-cells, #size-cells, ranges: Must describe the mapping between
|
||||
parent address and child address spaces.
|
||||
- reg: Must contain the base address and length to access the bus controller.
|
||||
|
||||
Optional properties:
|
||||
- interrupts: Must contain a reference to the BSC interrupt, if available.
|
||||
- clocks: Must contain a reference to the functional clock, if available.
|
||||
- power-domains: Must contain a reference to the PM domain, if available.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
60
Bindings/bus/renesas,bsc.yaml
Normal file
60
Bindings/bus/renesas,bsc.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Bus State Controller (BSC)
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
|
||||
Bridge", or "External Bus Interface") can be found in several Renesas ARM
|
||||
SoCs. It provides an external bus for connecting multiple external
|
||||
devices to the SoC, driving several chip select lines, for e.g. NOR
|
||||
FLASH, Ethernet and USB.
|
||||
|
||||
While the BSC is a fairly simple memory-mapped bus, it may be part of a
|
||||
PM domain, and may have a gateable functional clock. Before a device
|
||||
connected to the BSC can be accessed, the PM domain containing the BSC
|
||||
must be powered on, and the functional clock driving the BSC must be
|
||||
enabled.
|
||||
|
||||
The bindings for the BSC extend the bindings for "simple-pm-bus".
|
||||
|
||||
allOf:
|
||||
- $ref: simple-pm-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,bsc-r8a73a4 # R-Mobile APE6 (r8a73a4)
|
||||
- renesas,bsc-sh73a0 # SH-Mobile AG5 (sh73a0)
|
||||
- const: renesas,bsc
|
||||
- {} # simple-pm-bus, but not listed here to avoid false select
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc", "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
@ -1,44 +0,0 @@
|
||||
Simple Power-Managed Bus
|
||||
========================
|
||||
|
||||
A Simple Power-Managed Bus is a transparent bus that doesn't need a real
|
||||
driver, as it's typically initialized by the boot loader.
|
||||
|
||||
However, its bus controller is part of a PM domain, or under the control of a
|
||||
functional clock. Hence, the bus controller's PM domain and/or clock must be
|
||||
enabled for child devices connected to the bus (either on-SoC or externally)
|
||||
to function.
|
||||
|
||||
While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
|
||||
in the Devicetree Specification, it is not an extension of "simple-bus".
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain at least "simple-pm-bus".
|
||||
Must not contain "simple-bus".
|
||||
It's recommended to let this be preceded by one or more
|
||||
vendor-specific compatible values.
|
||||
- #address-cells, #size-cells, ranges: Must describe the mapping between
|
||||
parent address and child address spaces.
|
||||
|
||||
Optional platform-specific properties for clock or PM domain control (at least
|
||||
one of them is required):
|
||||
- clocks: Must contain a reference to the functional clock(s),
|
||||
- power-domains: Must contain a reference to the PM domain.
|
||||
Please refer to the binding documentation for the clock and/or PM domain
|
||||
providers for more details.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
bsc: bus@fec10000 {
|
||||
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
||||
"simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20000000>;
|
||||
reg = <0xfec10000 0x400>;
|
||||
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&zb_clk>;
|
||||
power-domains = <&pd_a4s>;
|
||||
};
|
||||
75
Bindings/bus/simple-pm-bus.yaml
Normal file
75
Bindings/bus/simple-pm-bus.yaml
Normal file
@ -0,0 +1,75 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Simple Power-Managed Bus
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
A Simple Power-Managed Bus is a transparent bus that doesn't need a real
|
||||
driver, as it's typically initialized by the boot loader.
|
||||
|
||||
However, its bus controller is part of a PM domain, or under the control
|
||||
of a functional clock. Hence, the bus controller's PM domain and/or
|
||||
clock must be enabled for child devices connected to the bus (either
|
||||
on-SoC or externally) to function.
|
||||
|
||||
While "simple-pm-bus" follows the "simple-bus" set of properties, as
|
||||
specified in the Devicetree Specification, it is not an extension of
|
||||
"simple-bus".
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^bus(@[0-9a-f]+)?$"
|
||||
|
||||
compatible:
|
||||
contains:
|
||||
const: simple-pm-bus
|
||||
description:
|
||||
Shall contain "simple-pm-bus" in addition to a optional bus-specific
|
||||
compatible strings defined in individual pm-bus bindings.
|
||||
|
||||
'#address-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
'#size-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
clocks: true
|
||||
# Functional clocks
|
||||
# Required if power-domains is absent, optional otherwise
|
||||
|
||||
power-domains:
|
||||
# Required if clocks is absent, optional otherwise
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- ranges
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- clocks
|
||||
- required:
|
||||
- power-domains
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
bus {
|
||||
power-domains = <&gcc AGGRE0_NOC_GDSC>;
|
||||
compatible = "simple-pm-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
};
|
||||
@ -8,7 +8,7 @@ title: Allwinner Clock Control Unit Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
|
||||
@ -7,7 +7,8 @@ devices.
|
||||
Required Properties:
|
||||
|
||||
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
|
||||
"amlogic,g12a-audio-clkc" for G12A.
|
||||
"amlogic,g12a-audio-clkc" for G12A,
|
||||
"amlogic,sm1-audio-clkc" for S905X3.
|
||||
- reg : physical base address of the clock controller and length of
|
||||
memory mapped region.
|
||||
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
|
||||
|
||||
@ -9,7 +9,7 @@ bridge.
|
||||
The peripheral clock consumer should specify the desired clock by
|
||||
having the clock ID in its "clocks" phandle cell.
|
||||
|
||||
The following is a list of provided IDs for Armada 370 North bridge clocks:
|
||||
The following is a list of provided IDs for Armada 3700 North bridge clocks:
|
||||
ID Clock name Description
|
||||
-----------------------------------
|
||||
0 mmc MMC controller
|
||||
@ -30,7 +30,7 @@ ID Clock name Description
|
||||
15 eip97 EIP 97
|
||||
16 cpu CPU
|
||||
|
||||
The following is a list of provided IDs for Armada 370 South bridge clocks:
|
||||
The following is a list of provided IDs for Armada 3700 South bridge clocks:
|
||||
ID Clock name Description
|
||||
-----------------------------------
|
||||
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
|
||||
@ -46,6 +46,7 @@ ID Clock name Description
|
||||
10 sdio SDIO
|
||||
11 usb32-sub2-sys USB 2 clock
|
||||
12 usb32-ss-sys USB 3 clock
|
||||
13 pcie PCIe controller
|
||||
|
||||
Required properties:
|
||||
|
||||
|
||||
76
Bindings/clock/bitmain,bm1880-clk.yaml
Normal file
76
Bindings/clock/bitmain,bm1880-clk.yaml
Normal file
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Bitmain BM1880 Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description: |
|
||||
The Bitmain BM1880 clock controller generates and supplies clock to
|
||||
various peripherals within the SoC.
|
||||
|
||||
This binding uses common clock bindings
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: bitmain,bm1880-clk
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: pll registers
|
||||
- description: system registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: pll
|
||||
- const: sys
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: osc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock controller node:
|
||||
- |
|
||||
clk: clock-controller@e8 {
|
||||
compatible = "bitmain,bm1880-clk";
|
||||
reg = <0xe8 0x0c>, <0x800 0xb0>;
|
||||
reg-names = "pll", "sys";
|
||||
clocks = <&osc>;
|
||||
clock-names = "osc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
# Example UART controller node that consumes clock generated by the clock controller:
|
||||
- |
|
||||
uart0: serial@58018000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x58018000 0x0 0x2000>;
|
||||
clocks = <&clk 45>, <&clk 46>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <0 9 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 {
|
||||
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
|
||||
<&scg1 IMX7ULP_CLK_UPLL>,
|
||||
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_MIPI_PLL>,
|
||||
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
|
||||
<&scg1 IMX7ULP_CLK_ROSC>,
|
||||
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
|
||||
|
||||
@ -11,6 +11,7 @@ Required properties:
|
||||
* ingenic,jz4725b-cgu
|
||||
* ingenic,jz4770-cgu
|
||||
* ingenic,jz4780-cgu
|
||||
* ingenic,x1000-cgu
|
||||
- reg : The address & length of the CGU registers.
|
||||
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
|
||||
Two such external clocks should be specified - first the external crystal
|
||||
|
||||
@ -1,94 +0,0 @@
|
||||
Qualcomm Global Clock & Reset Controller Binding
|
||||
------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,gcc-apq8064"
|
||||
"qcom,gcc-apq8084"
|
||||
"qcom,gcc-ipq8064"
|
||||
"qcom,gcc-ipq4019"
|
||||
"qcom,gcc-ipq8074"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8916"
|
||||
"qcom,gcc-msm8960"
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
"qcom,gcc-msm8974pro-ac"
|
||||
"qcom,gcc-msm8994"
|
||||
"qcom,gcc-msm8996"
|
||||
"qcom,gcc-msm8998"
|
||||
"qcom,gcc-mdm9615"
|
||||
"qcom,gcc-qcs404"
|
||||
"qcom,gcc-sdm630"
|
||||
"qcom,gcc-sdm660"
|
||||
"qcom,gcc-sdm845"
|
||||
"qcom,gcc-sm8150"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
- #reset-cells : shall contain 1
|
||||
|
||||
Optional properties :
|
||||
- #power-domain-cells : shall contain 1
|
||||
- Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be
|
||||
part of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
- protected-clocks : Protected clock specifier list as per common clock
|
||||
binding.
|
||||
|
||||
For SM8150 only:
|
||||
- clocks: a list of phandles and clock-specifier pairs,
|
||||
one for each entry in clock-names.
|
||||
- clock-names: "bi_tcxo" (required)
|
||||
"sleep_clk" (optional)
|
||||
"aud_ref_clock" (optional)
|
||||
|
||||
Example:
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
Example of GCC with TSENS properties:
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
Example of GCC with protected-clocks properties:
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm845";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
protected-clocks = <GCC_QSPI_CORE_CLK>,
|
||||
<GCC_QSPI_CORE_CLK_SRC>,
|
||||
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
|
||||
<GCC_LPASS_Q6_AXI_CLK>,
|
||||
<GCC_LPASS_SWAY_CLK>;
|
||||
};
|
||||
|
||||
Example of GCC with clocks
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk";
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&sleep_clk>;
|
||||
};
|
||||
188
Bindings/clock/qcom,gcc.yaml
Normal file
188
Bindings/clock/qcom,gcc.yaml
Normal file
@ -0,0 +1,188 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/qcom,gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
|
||||
properties:
|
||||
compatible :
|
||||
enum:
|
||||
- qcom,gcc-apq8064
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq8074
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,gcc-msm8916
|
||||
- qcom,gcc-msm8960
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-msm8994
|
||||
- qcom,gcc-msm8996
|
||||
- qcom,gcc-msm8998
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-qcs404
|
||||
- qcom,gcc-sc7180
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
- qcom,gcc-sdm845
|
||||
- qcom,gcc-sm8150
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
nvmem-cells:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Qualcomm TSENS (thermal sensor device) on some devices can
|
||||
be part of GCC and hence the TSENS properties can also be part
|
||||
of the GCC/clock-controller node.
|
||||
For more details on the TSENS properties please refer
|
||||
Documentation/devicetree/bindings/thermal/qcom-tsens.txt
|
||||
|
||||
nvmem-cell-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
Names for each nvmem-cells specified.
|
||||
items:
|
||||
- const: calib
|
||||
- const: calib_backup
|
||||
|
||||
'thermal-sensor-cells':
|
||||
const: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,gcc-apq8064
|
||||
|
||||
then:
|
||||
required:
|
||||
- nvmem-cells
|
||||
- nvmem-cell-names
|
||||
- '#thermal-sensor-cells'
|
||||
|
||||
else:
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,gcc-sm8150
|
||||
- qcom,gcc-sc7180
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8960:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8960";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
# Example of GCC with TSENS properties:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-apq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
nvmem-cell-names = "calib", "calib_backup";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with protected-clocks properties:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm845";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
protected-clocks = <187>, <188>, <189>, <190>, <191>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with clock node properties for SM8150:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8150";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
# Example of GCC with clock nodes properties for SC7180:
|
||||
- |
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7180";
|
||||
reg = <0x100000 0x1f0000>;
|
||||
clocks = <&rpmhcc 0>, <&rpmhcc 1>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
43
Bindings/clock/qcom,q6sstopcc.yaml
Normal file
43
Bindings/clock/qcom,q6sstopcc.yaml
Normal file
@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,q6sstopcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Q6SSTOP clock Controller
|
||||
|
||||
maintainers:
|
||||
- Govind Singh <govinds@codeaurora.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: "qcom,qcs404-q6sstopcc"
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Q6SSTOP clocks register region
|
||||
- description: Q6SSTOP_TCSR register region
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: ahb clock for the q6sstopCC
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
q6sstopcc: clock-controller@7500000 {
|
||||
compatible = "qcom,qcs404-q6sstopcc";
|
||||
reg = <0x07500000 0x4e000>, <0x07550000 0x10000>;
|
||||
clocks = <&gcc 141>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,27 +0,0 @@
|
||||
Qualcomm Technologies, Inc. RPMh Clocks
|
||||
-------------------------------------------------------
|
||||
|
||||
Resource Power Manager Hardened (RPMh) manages shared resources on
|
||||
some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
|
||||
other hardware subsystems via RSC to control clocks.
|
||||
|
||||
Required properties :
|
||||
- compatible : must be one of:
|
||||
"qcom,sdm845-rpmh-clk"
|
||||
"qcom,sm8150-rpmh-clk"
|
||||
|
||||
- #clock-cells : must contain 1
|
||||
- clocks: a list of phandles and clock-specifier pairs,
|
||||
one for each entry in clock-names.
|
||||
- clock-names: Parent board clock: "xo".
|
||||
|
||||
Example :
|
||||
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
&apps_rsc {
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sdm845-rpmh-clk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
49
Bindings/clock/qcom,rpmhcc.yaml
Normal file
49
Bindings/clock/qcom,rpmhcc.yaml
Normal file
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bindings/clock/qcom,rpmhcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. RPMh Clocks Bindings
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Resource Power Manager Hardened (RPMh) manages shared resources on
|
||||
some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
|
||||
other hardware subsystems via RSC to control clocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Example for GCC for SDM845: The below node should be defined inside
|
||||
# &apps_rsc node.
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
rpmhcc: clock-controller {
|
||||
compatible = "qcom,sdm845-rpmh-clk";
|
||||
clocks = <&xo_board>;
|
||||
clock-names = "xo";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
||||
@ -19,6 +19,7 @@ Required Properties:
|
||||
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
|
||||
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
|
||||
- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
|
||||
- "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)
|
||||
- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
|
||||
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
|
||||
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
|
||||
@ -26,7 +27,8 @@ Required Properties:
|
||||
- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
|
||||
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
|
||||
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
|
||||
- "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
|
||||
- "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
|
||||
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
|
||||
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
|
||||
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
|
||||
@ -40,10 +42,11 @@ Required Properties:
|
||||
clock-names
|
||||
- clock-names: List of external parent clock names. Valid names are:
|
||||
- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
|
||||
r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
|
||||
r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
|
||||
r8a77995)
|
||||
- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
|
||||
r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
|
||||
r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
|
||||
r8a77980, r8a77990, r8a77995)
|
||||
- "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
|
||||
r8a77970, r8a77980)
|
||||
- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
|
||||
r8a7793, r8a7794)
|
||||
|
||||
@ -59,7 +62,7 @@ Required Properties:
|
||||
power-managed through Module Standby should refer to the CPG device
|
||||
node in their "power-domains" property, as documented by the generic PM
|
||||
Domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
|
||||
- #reset-cells: Must be 1
|
||||
- The single reset specifier cell must be the module number, as defined
|
||||
|
||||
@ -1,60 +0,0 @@
|
||||
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
|
||||
and several fixed ratio dividers.
|
||||
The CPG also provides a Clock Domain for SoC devices, in combination with the
|
||||
CPG Module Stop (MSTP) Clocks.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of
|
||||
- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
|
||||
- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
|
||||
- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
|
||||
- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
|
||||
- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
|
||||
and "renesas,rcar-gen2-cpg-clocks" as a fallback.
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: References to the parent clocks: first to the EXTAL clock, second
|
||||
to the USB_EXTAL clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "main",
|
||||
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
|
||||
"adsp"
|
||||
- #power-domain-cells: Must be 0
|
||||
|
||||
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
|
||||
through an MSTP clock should refer to the CPG device node in their
|
||||
"power-domains" property, as documented by the generic PM domain bindings in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt.
|
||||
|
||||
|
||||
Examples
|
||||
--------
|
||||
|
||||
- CPG device node:
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7790-cpg-clocks",
|
||||
"renesas,rcar-gen2-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk &usb_extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0, "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "sd1", "z",
|
||||
"rcan", "adsp";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
- CPG/MSTP Clock Domain member device node:
|
||||
|
||||
thermal@e61f0000 {
|
||||
compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
|
||||
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
|
||||
power-domains = <&cpg_clocks>;
|
||||
};
|
||||
@ -46,7 +46,7 @@ Required properties:
|
||||
Example (R-Car H3):
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
|
||||
compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
|
||||
|
||||
@ -10,6 +10,11 @@ Required Properties:
|
||||
- compatible: CRU should be "rockchip,px30-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
|
||||
in clock-names
|
||||
- clock-names: Should contain the following:
|
||||
- "xin24m" for both PMUCRU and CRU
|
||||
- "gpll" for CRU (sourced from PMUCRU)
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
|
||||
@ -67,5 +67,5 @@ Examples:
|
||||
|
||||
Also see:
|
||||
- Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
- Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- Documentation/devicetree/bindings/power/power-domain.yaml
|
||||
- Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
@ -1,29 +0,0 @@
|
||||
STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
|
||||
|
||||
STM32 Low-Power Timer provides several counter modes. It can be used as:
|
||||
- quadrature encoder to detect angular position and direction of rotary
|
||||
elements, from IN1 and IN2 input signals.
|
||||
- simple counter from IN1 input signal.
|
||||
|
||||
Must be a sub-node of an STM32 Low-Power Timer device tree node.
|
||||
See ../mfd/stm32-lptimer.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-lptimer-counter".
|
||||
- pinctrl-names: Set to "default". An additional "sleep" state can be
|
||||
defined to set pins in sleep state.
|
||||
- pinctrl-n: List of phandles pointing to pin configuration nodes,
|
||||
to set IN1/IN2 pins in mode of operation for Low-Power
|
||||
Timer input on external pin.
|
||||
|
||||
Example:
|
||||
timer@40002400 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
...
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&lptim1_in_pins>;
|
||||
pinctrl-1 = <&lptim1_sleep_in_pins>;
|
||||
};
|
||||
};
|
||||
@ -1,31 +0,0 @@
|
||||
STMicroelectronics STM32 Timer quadrature encoder
|
||||
|
||||
STM32 Timer provides quadrature encoder to detect
|
||||
angular position and direction of rotary elements,
|
||||
from IN1 and IN2 input signals.
|
||||
|
||||
Must be a sub-node of an STM32 Timer device tree node.
|
||||
See ../mfd/stm32-timers.txt for details about the parent node.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,stm32-timer-counter".
|
||||
- pinctrl-names: Set to "default".
|
||||
- pinctrl-0: List of phandles pointing to pin configuration nodes,
|
||||
to set CH1/CH2 pins in mode of operation for STM32
|
||||
Timer input on external pin.
|
||||
|
||||
Example:
|
||||
timers@40010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc 0 160>;
|
||||
clock-names = "int";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-timer-counter";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tim1_in_pins>;
|
||||
};
|
||||
};
|
||||
50
Bindings/counter/ti-eqep.yaml
Normal file
50
Bindings/counter/ti-eqep.yaml
Normal file
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/counter/ti-eqep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) Module
|
||||
|
||||
maintainers:
|
||||
- David Lechner <david@lechnology.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,am3352-eqep
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: The eQEP event interrupt
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: The clock that determines the SYSCLKOUT rate for the eQEP
|
||||
peripheral.
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: sysclkout
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
eqep0: counter@180 {
|
||||
compatible = "ti,am3352-eqep";
|
||||
reg = <0x180 0x80>;
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "sysclkout";
|
||||
interrupts = <79>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -549,5 +549,5 @@ Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)
|
||||
[2] Devicetree NUMA binding description
|
||||
Documentation/devicetree/bindings/numa.txt
|
||||
[3] RISC-V Linux kernel documentation
|
||||
Documentation/devicetree/bindings/riscv/cpus.txt
|
||||
Documentation/devicetree/bindings/riscv/cpus.yaml
|
||||
[4] https://www.devicetree.org/specifications/
|
||||
|
||||
@ -15,12 +15,16 @@ In 'cpus' nodes:
|
||||
|
||||
In 'operating-points-v2' table:
|
||||
- compatible: Should be
|
||||
- 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs
|
||||
- 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
|
||||
omap34xx, omap36xx and am3517 SoCs
|
||||
- syscon: A phandle pointing to a syscon node representing the control module
|
||||
register space of the SoC.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- "vdd-supply", "vbb-supply": to define two regulators for dra7xx
|
||||
- "cpu0-supply", "vbb-supply": to define two regulators for omap36xx
|
||||
|
||||
For each opp entry in 'operating-points-v2' table:
|
||||
- opp-supported-hw: Two bitfields indicating:
|
||||
1. Which revision of the SoC the OPP is supported by
|
||||
|
||||
@ -8,7 +8,7 @@ title: Allwinner A10 Security System Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
88
Bindings/crypto/allwinner,sun8i-ce.yaml
Normal file
88
Bindings/crypto/allwinner,sun8i-ce.yaml
Normal file
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner Crypto Engine driver
|
||||
|
||||
maintainers:
|
||||
- Corentin Labbe <clabbe.montjoie@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun8i-h3-crypto
|
||||
- allwinner,sun8i-r40-crypto
|
||||
- allwinner,sun50i-a64-crypto
|
||||
- allwinner,sun50i-h5-crypto
|
||||
- allwinner,sun50i-h6-crypto
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus clock
|
||||
- description: Module clock
|
||||
- description: MBus clock
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: mod
|
||||
- const: ram
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
const: allwinner,sun50i-h6-crypto
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
clock-names:
|
||||
minItems: 3
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/sun50i-a64-ccu.h>
|
||||
#include <dt-bindings/reset/sun50i-a64-ccu.h>
|
||||
|
||||
crypto: crypto@1c15000 {
|
||||
compatible = "allwinner,sun8i-h3-crypto";
|
||||
reg = <0x01c15000 0x1000>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_CE>;
|
||||
};
|
||||
|
||||
60
Bindings/crypto/allwinner,sun8i-ss.yaml
Normal file
60
Bindings/crypto/allwinner,sun8i-ss.yaml
Normal file
@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner Security System v2 driver
|
||||
|
||||
maintainers:
|
||||
- Corentin Labbe <corentin.labbe@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun8i-a83t-crypto
|
||||
- allwinner,sun9i-a80-crypto
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus clock
|
||||
- description: Module clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: mod
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
|
||||
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
|
||||
|
||||
crypto: crypto@1c15000 {
|
||||
compatible = "allwinner,sun8i-a83t-crypto";
|
||||
reg = <0x01c15000 0x1000>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&ccu RST_BUS_SS>;
|
||||
clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
|
||||
clock-names = "bus", "mod";
|
||||
};
|
||||
52
Bindings/crypto/amlogic,gxl-crypto.yaml
Normal file
52
Bindings/crypto/amlogic,gxl-crypto.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/amlogic,gxl-crypto.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic GXL Cryptographic Offloader
|
||||
|
||||
maintainers:
|
||||
- Corentin Labbe <clabbe@baylibre.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: amlogic,gxl-crypto
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: "Interrupt for flow 0"
|
||||
- description: "Interrupt for flow 1"
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: blkmv
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
||||
crypto: crypto-engine@c883e000 {
|
||||
compatible = "amlogic,gxl-crypto";
|
||||
reg = <0x0 0xc883e000 0x0 0x36>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&clkc CLKID_BLKMV>;
|
||||
clock-names = "blkmv";
|
||||
};
|
||||
@ -1,19 +0,0 @@
|
||||
Samsung SoC SlimSSS (Slim Security SubSystem) module
|
||||
|
||||
The SlimSSS module in Exynos5433 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
||||
-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entry for slimSSS version:
|
||||
- "samsung,exynos5433-slim-sss" for Exynos5433 SoC.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SlimSSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain "pclk" and
|
||||
"aclk" for slim-sss in Exynos5433.
|
||||
47
Bindings/crypto/samsung-slimsss.yaml
Normal file
47
Bindings/crypto/samsung-slimsss.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/samsung-slimsss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC SlimSSS (Slim Security SubSystem) module
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Kamil Konieczny <k.konieczny@partner.samsung.com>
|
||||
|
||||
description: |+
|
||||
The SlimSSS module in Exynos5433 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
|
||||
-- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: samsung,exynos5433-slim-ss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: aclk
|
||||
|
||||
interrupts:
|
||||
description: One feed control interrupt.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
@ -1,32 +0,0 @@
|
||||
Samsung SoC SSS (Security SubSystem) module
|
||||
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and
|
||||
Exynos5 (Exynos5420 and Exynos5250) SoCs
|
||||
supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SSS versions:
|
||||
- "samsung,s5pv210-secss" for S5PV210 SoC.
|
||||
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
|
||||
Exynos5260 and Exynos5420 SoCs.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain one entry
|
||||
"secss".
|
||||
58
Bindings/crypto/samsung-sss.yaml
Normal file
58
Bindings/crypto/samsung-sss.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/samsung-sss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC SSS (Security SubSystem) module
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
- Kamil Konieczny <k.konieczny@partner.samsung.com>
|
||||
|
||||
description: |+
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and Exynos5 (Exynos5420 and Exynos5250)
|
||||
SoCs supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- samsung,s5pv210-secss # for S5PV210
|
||||
- samsung,exynos4210-secss # for Exynos4210, Exynos4212,
|
||||
# Exynos4412, Exynos5250,
|
||||
# Exynos5260 and Exynos5420
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: secss
|
||||
|
||||
interrupts:
|
||||
description: One feed control interrupt.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
@ -1,16 +0,0 @@
|
||||
* STMicroelectronics STM32 CRC
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f7-crc".
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- clocks: The input clock of the CRC instance
|
||||
|
||||
Optional properties: none
|
||||
|
||||
Example:
|
||||
|
||||
crc: crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 12>;
|
||||
};
|
||||
38
Bindings/crypto/st,stm32-crc.yaml
Normal file
38
Bindings/crypto/st,stm32-crc.yaml
Normal file
@ -0,0 +1,38 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-crc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRC bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32f7-crc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 12>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,19 +0,0 @@
|
||||
* STMicroelectronics STM32 CRYP
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "st,stm32f756-cryp".
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- clocks: The input clock of the CRYP instance
|
||||
- interrupts: The CRYP interrupt
|
||||
|
||||
Optional properties:
|
||||
- resets: The input reset of the CRYP instance
|
||||
|
||||
Example:
|
||||
crypto@50060000 {
|
||||
compatible = "st,stm32f756-cryp";
|
||||
reg = <0x50060000 0x400>;
|
||||
interrupts = <79>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(CRYP)>;
|
||||
resets = <&rcc STM32F7_AHB2_RESET(CRYP)>;
|
||||
};
|
||||
51
Bindings/crypto/st,stm32-cryp.yaml
Normal file
51
Bindings/crypto/st,stm32-cryp.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 CRYP bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f756-cryp
|
||||
- st,stm32mp1-cryp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,30 +0,0 @@
|
||||
* STMicroelectronics STM32 HASH
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain entries for this and backward compatible
|
||||
HASH versions:
|
||||
- "st,stm32f456-hash" for stm32 F456.
|
||||
- "st,stm32f756-hash" for stm32 F756.
|
||||
- reg: The address and length of the peripheral registers space
|
||||
- interrupts: the interrupt specifier for the HASH
|
||||
- clocks: The input clock of the HASH instance
|
||||
|
||||
Optional properties:
|
||||
- resets: The input reset of the HASH instance
|
||||
- dmas: DMA specifiers for the HASH. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt
|
||||
- dma-names: DMA request name. Should be "in" if a dma is present.
|
||||
- dma-maxburst: Set number of maximum dma burst supported
|
||||
|
||||
Example:
|
||||
|
||||
hash1: hash@50060400 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x50060400 0x400>;
|
||||
interrupts = <80>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
|
||||
resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
|
||||
dmas = <&dma2 7 2 0x400 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <0>;
|
||||
};
|
||||
69
Bindings/crypto/st,stm32-hash.yaml
Normal file
69
Bindings/crypto/st,stm32-hash.yaml
Normal file
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics STM32 HASH bindings
|
||||
|
||||
maintainers:
|
||||
- Lionel Debieve <lionel.debieve@st.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- st,stm32f456-hash
|
||||
- st,stm32f756-hash
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: in
|
||||
|
||||
dma-maxburst:
|
||||
description: Set number of maximum dma burst supported
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 0
|
||||
- maximum: 2
|
||||
- default: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
hash@54002000 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc HASH1>;
|
||||
resets = <&rcc HASH1_R>;
|
||||
dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
|
||||
dma-names = "in";
|
||||
dma-maxburst = <2>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -36,7 +36,7 @@ Child nodes:
|
||||
"lpddr2-timings" provides AC timing parameters of the device for
|
||||
a given speed-bin. The user may provide the timings for as many
|
||||
speed-bins as is required. Please see Documentation/devicetree/
|
||||
bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
|
||||
bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
|
||||
|
||||
Example:
|
||||
|
||||
58
Bindings/ddr/lpddr3-timings.txt
Normal file
58
Bindings/ddr/lpddr3-timings.txt
Normal file
@ -0,0 +1,58 @@
|
||||
* AC timing parameters of LPDDR3 memories for a given speed-bin.
|
||||
|
||||
The structures are based on LPDDR2 and extended where needed.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "jedec,lpddr3-timings"
|
||||
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following properties represent AC timing parameters from the memory
|
||||
data-sheet of the device for a given speed-bin. All these properties are
|
||||
of type <u32> and the default unit is ps (pico seconds).
|
||||
- tRFC
|
||||
- tRRD
|
||||
- tRPab
|
||||
- tRPpb
|
||||
- tRCD
|
||||
- tRC
|
||||
- tRAS
|
||||
- tWTR
|
||||
- tWR
|
||||
- tRTP
|
||||
- tW2W-C2C
|
||||
- tR2R-C2C
|
||||
- tFAW
|
||||
- tXSR
|
||||
- tXP
|
||||
- tCKE
|
||||
- tCKESR
|
||||
- tMRD
|
||||
|
||||
Example:
|
||||
|
||||
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
reg = <800000000>; /* workaround: it shows max-freq */
|
||||
min-freq = <100000000>;
|
||||
tRFC = <65000>;
|
||||
tRRD = <6000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRCD = <10000>;
|
||||
tRC = <33750>;
|
||||
tRAS = <23000>;
|
||||
tWTR = <3750>;
|
||||
tWR = <7500>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tR2R-C2C = <0>;
|
||||
tFAW = <25000>;
|
||||
tXSR = <70000>;
|
||||
tXP = <3750>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tMRD = <7000>;
|
||||
};
|
||||
101
Bindings/ddr/lpddr3.txt
Normal file
101
Bindings/ddr/lpddr3.txt
Normal file
@ -0,0 +1,101 @@
|
||||
* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
|
||||
Example "<vendor>,<type>" values:
|
||||
"samsung,K3QF2F20DB"
|
||||
|
||||
- density : <u32> representing density in Mb (Mega bits)
|
||||
- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
|
||||
- #address-cells: Must be set to 1
|
||||
- #size-cells: Must be set to 0
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following optional properties represent the minimum value of some AC
|
||||
timing parameters of the DDR device in terms of number of clock cycles.
|
||||
These values shall be obtained from the device data-sheet.
|
||||
- tRFC-min-tck
|
||||
- tRRD-min-tck
|
||||
- tRPab-min-tck
|
||||
- tRPpb-min-tck
|
||||
- tRCD-min-tck
|
||||
- tRC-min-tck
|
||||
- tRAS-min-tck
|
||||
- tWTR-min-tck
|
||||
- tWR-min-tck
|
||||
- tRTP-min-tck
|
||||
- tW2W-C2C-min-tck
|
||||
- tR2R-C2C-min-tck
|
||||
- tWL-min-tck
|
||||
- tDQSCK-min-tck
|
||||
- tRL-min-tck
|
||||
- tFAW-min-tck
|
||||
- tXSR-min-tck
|
||||
- tXP-min-tck
|
||||
- tCKE-min-tck
|
||||
- tCKESR-min-tck
|
||||
- tMRD-min-tck
|
||||
|
||||
Child nodes:
|
||||
- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
|
||||
"lpddr3-timings" provides AC timing parameters of the device for
|
||||
a given speed-bin. Please see Documentation/devicetree/
|
||||
bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"
|
||||
|
||||
Example:
|
||||
|
||||
samsung_K3QF2F20DB: lpddr3 {
|
||||
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
|
||||
density = <16384>;
|
||||
io-width = <32>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tRFC-min-tck = <17>;
|
||||
tRRD-min-tck = <2>;
|
||||
tRPab-min-tck = <2>;
|
||||
tRPpb-min-tck = <2>;
|
||||
tRCD-min-tck = <3>;
|
||||
tRC-min-tck = <6>;
|
||||
tRAS-min-tck = <5>;
|
||||
tWTR-min-tck = <2>;
|
||||
tWR-min-tck = <7>;
|
||||
tRTP-min-tck = <2>;
|
||||
tW2W-C2C-min-tck = <0>;
|
||||
tR2R-C2C-min-tck = <0>;
|
||||
tWL-min-tck = <8>;
|
||||
tDQSCK-min-tck = <5>;
|
||||
tRL-min-tck = <14>;
|
||||
tFAW-min-tck = <5>;
|
||||
tXSR-min-tck = <12>;
|
||||
tXP-min-tck = <2>;
|
||||
tCKE-min-tck = <2>;
|
||||
tCKESR-min-tck = <2>;
|
||||
tMRD-min-tck = <5>;
|
||||
|
||||
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
|
||||
compatible = "jedec,lpddr3-timings";
|
||||
/* workaround: 'reg' shows max-freq */
|
||||
reg = <800000000>;
|
||||
min-freq = <100000000>;
|
||||
tRFC = <65000>;
|
||||
tRRD = <6000>;
|
||||
tRPab = <12000>;
|
||||
tRPpb = <12000>;
|
||||
tRCD = <10000>;
|
||||
tRC = <33750>;
|
||||
tRAS = <23000>;
|
||||
tWTR = <3750>;
|
||||
tWR = <7500>;
|
||||
tRTP = <3750>;
|
||||
tW2W-C2C = <0>;
|
||||
tR2R-C2C = <0>;
|
||||
tFAW = <25000>;
|
||||
tXSR = <70000>;
|
||||
tXP = <3750>;
|
||||
tCKE = <3750>;
|
||||
tCKESR = <3750>;
|
||||
tMRD = <7000>;
|
||||
};
|
||||
}
|
||||
@ -10,14 +10,23 @@ The Exynos PPMU driver uses the devfreq-event class to provide event data
|
||||
to various devfreq devices. The devfreq devices would use the event data when
|
||||
derterming the current state of each IP.
|
||||
|
||||
Required properties:
|
||||
Required properties for PPMU device:
|
||||
- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
|
||||
- reg: physical base address of each PPMU and length of memory mapped region.
|
||||
|
||||
Optional properties:
|
||||
Optional properties for PPMU device:
|
||||
- clock-names : the name of clock used by the PPMU, "ppmu"
|
||||
- clocks : phandles for clock specified in "clock-names" property
|
||||
|
||||
Required properties for 'events' child node of PPMU device:
|
||||
- event-name : the unique event name among PPMU device
|
||||
Optional properties for 'events' child node of PPMU device:
|
||||
- event-data-type : Define the type of data which shell be counted
|
||||
by the counter. You can check include/dt-bindings/pmu/exynos_ppmu.h for
|
||||
all possible type, i.e. count read requests, count write data in bytes,
|
||||
etc. This field is optional and when it is missing, the driver code
|
||||
will use default data type.
|
||||
|
||||
Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
|
||||
|
||||
ppmu_dmc0: ppmu_dmc0@106a0000 {
|
||||
@ -145,3 +154,16 @@ Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
|
||||
reg = <0x104d0000 0x2000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Example4 : 'event-data-type' in exynos4412-ppmu-common.dtsi are listed below.
|
||||
|
||||
&ppmu_dmc0 {
|
||||
status = "okay";
|
||||
events {
|
||||
ppmu_dmc0_3: ppmu-event3-dmc0 {
|
||||
event-name = "ppmu-event3-dmc0";
|
||||
event-data-type = <(PPMU_RO_DATA_CNT |
|
||||
PPMU_WO_DATA_CNT)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -50,8 +50,6 @@ Required properties only for passive bus device:
|
||||
Optional properties only for parent bus device:
|
||||
- exynos,saturation-ratio: the percentage value which is used to calibrate
|
||||
the performance count against total cycle count.
|
||||
- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
|
||||
which is used to calculate the max voltage.
|
||||
|
||||
Detailed correlation between sub-blocks and power line according to Exynos SoC:
|
||||
- In case of Exynos3250, there are two power line as following:
|
||||
|
||||
@ -8,7 +8,7 @@ title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
- Maxime Ripard <mripard@kernel.org>
|
||||
|
||||
properties:
|
||||
"#address-cells": true
|
||||
@ -36,6 +36,9 @@ properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
vcc-dsi-supply:
|
||||
description: VCC-DSI power supply of the DSI encoder
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
@ -64,6 +67,7 @@ required:
|
||||
- phys
|
||||
- phy-names
|
||||
- resets
|
||||
- vcc-dsi-supply
|
||||
- port
|
||||
|
||||
additionalProperties: false
|
||||
@ -79,6 +83,7 @@ examples:
|
||||
resets = <&ccu 4>;
|
||||
phys = <&dphy0>;
|
||||
phy-names = "dphy";
|
||||
vcc-dsi-supply = <®_dcdc1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@ -79,8 +79,6 @@ properties:
|
||||
|
||||
hdmi-supply:
|
||||
description: phandle to an external 5V regulator to power the HDMI logic
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
port@0:
|
||||
type: object
|
||||
|
||||
@ -37,6 +37,8 @@ Optional properties:
|
||||
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
|
||||
to be used for the framebuffer; if not present, the framebuffer may
|
||||
be located anywhere in memory.
|
||||
- arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
|
||||
levels of DP500's QoS signaling.
|
||||
|
||||
|
||||
Example:
|
||||
@ -54,6 +56,7 @@ Example:
|
||||
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
|
||||
clock-names = "pxlclk", "mclk", "aclk", "pclk";
|
||||
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
|
||||
arm,malidp-arqos-high-level = <0xd000d000>;
|
||||
port {
|
||||
dp0_output: endpoint {
|
||||
remote-endpoint = <&tda998x_2_input>;
|
||||
|
||||
102
Bindings/display/bridge/anx6345.yaml
Normal file
102
Bindings/display/bridge/anx6345.yaml
Normal file
@ -0,0 +1,102 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analogix ANX6345 eDP Transmitter Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Torsten Duwe <duwe@lst.de>
|
||||
|
||||
description: |
|
||||
The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
|
||||
portable devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: analogix,anx6345
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: base I2C address of the device
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO connected to active low reset
|
||||
|
||||
dvdd12-supply:
|
||||
maxItems: 1
|
||||
description: Regulator for 1.2V digital core power.
|
||||
|
||||
dvdd25-supply:
|
||||
maxItems: 1
|
||||
description: Regulator for 2.5V digital core power.
|
||||
|
||||
ports:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
type: object
|
||||
description: |
|
||||
Video port for LVTTL input
|
||||
|
||||
port@1:
|
||||
type: object
|
||||
description: |
|
||||
Video port for eDP output (panel or connector).
|
||||
May be omitted if EDID works reliably.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reset-gpios
|
||||
- dvdd12-supply
|
||||
- dvdd25-supply
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
anx6345: anx6345@38 {
|
||||
compatible = "analogix,anx6345";
|
||||
reg = <0x38>;
|
||||
reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>;
|
||||
dvdd25-supply = <®_dldo2>;
|
||||
dvdd12-supply = <®_fldo1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
anx6345_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
anx6345_in_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon0_out_anx6345>;
|
||||
};
|
||||
};
|
||||
|
||||
anx6345_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
anx6345_out_panel: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_in_edp>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -6,7 +6,11 @@ designed for portable devices.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : "analogix,anx7814"
|
||||
- compatible : Must be one of:
|
||||
"analogix,anx7808"
|
||||
"analogix,anx7812"
|
||||
"analogix,anx7814"
|
||||
"analogix,anx7818"
|
||||
- reg : I2C address of the device
|
||||
- interrupts : Should contain the INTP interrupt
|
||||
- hpd-gpios : Which GPIO to use for hpd
|
||||
|
||||
@ -13,6 +13,7 @@ Required properties:
|
||||
|
||||
- compatible : Shall contain one or more of
|
||||
- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
|
||||
- "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
|
||||
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
|
||||
- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
|
||||
- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
|
||||
|
||||
@ -10,6 +10,7 @@ Required properties:
|
||||
- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
|
||||
- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
|
||||
- "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
|
||||
- "renesas,r8a774b1-lvds" for R8A774B1 (RZ/G2N) compatible LVDS encoders
|
||||
- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
|
||||
- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
|
||||
- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
|
||||
|
||||
@ -21,7 +21,7 @@ Optional properties:
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
the second cell is used to specify flags.
|
||||
See ../../gpio/gpio.txt for more information.
|
||||
- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of
|
||||
- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of
|
||||
the cell formats.
|
||||
|
||||
- clock-names: should be "refclk"
|
||||
|
||||
@ -27,11 +27,11 @@ Example:
|
||||
|
||||
display: display {
|
||||
model = "320x240x4";
|
||||
native-mode = <&timing0>;
|
||||
bits-per-pixel = <4>;
|
||||
ac-prescale = <17>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: 320x240 {
|
||||
hactive = <320>;
|
||||
hback-porch = <0>;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user