Clean up some macros. Add in ISP 1080/1240 NVRAM layout definitions.
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mjacob
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1f0c5e57fe
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352b4ebe9e
@ -1,5 +1,5 @@
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/* $Id: ispreg.h,v 1.7 1999/03/17 05:04:39 mjacob Exp $ */
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/* release_03_25_99 */
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/* $Id: ispreg.h,v 1.8 1999/03/25 22:52:45 mjacob Exp $ */
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/* release_5_11_99 */
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/*
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* Machine Independent (well, as best as possible) register
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* definitions for Qlogic ISP SCSI adapters.
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@ -54,6 +54,14 @@
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* Offsets for various register blocks.
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*
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* Sad but true, different architectures have different offsets.
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*
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* Don't be alarmed if none of this makes sense. The original register
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* layout set some defines in a certain pattern. Everything else has been
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* grafted on since. For example, the ISP1080 manual will state that DMA
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* registers start at 0x80 from the base of the register address space.
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* That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
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* to start at offset 0x60 because the DMA registers are all defined to
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* be DMA_BLOCK+0x20 and so on. Clear?
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*/
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#define BIU_REGS_OFF 0x00
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@ -188,11 +196,11 @@
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#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
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#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
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#define ENABLE_INTS(isp) (isp->isp_type & ISP_HA_SCSI)? \
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#define ENABLE_INTS(isp) (IS_SCSI(isp))? \
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ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \
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ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS)
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#define INTS_ENABLED(isp) ((isp->isp_type & ISP_HA_SCSI)? \
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#define INTS_ENABLED(isp) ((IS_SCSI(isp))? \
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(ISP_READ(isp, BIU_ICR) & (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)) :\
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(ISP_READ(isp, BIU_ICR) & \
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(BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)))
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@ -606,7 +614,13 @@
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#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
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/*
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* Qlogic 1XXX NVRAM is an array of 128 bytes.
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* NVRAM Definitions (PCI cards only)
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*/
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#define ISPBSMX(c, byte, shift, mask) \
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(((c)[(byte)] >> (shift)) & (mask))
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/*
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* Qlogic 1020/1040 NVRAM is an array of 128 bytes.
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*
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* Some portion of the front of this is for general host adapter properties
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* This is followed by an array of per-target parameters, and is tailed off
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@ -616,9 +630,6 @@
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#define ISP_NVRAM_SIZE 128
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#define ISPBSMX(c, byte, shift, mask) \
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(((c)[(byte)] >> (shift)) & (mask))
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#define ISP_NVRAM_VERSION(c) (c)[4]
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#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
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#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
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@ -668,6 +679,115 @@
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#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
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#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
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/*
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* Qlogic 1080/1240 NVRAM is an array of 256 bytes.
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*
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* Some portion of the front of this is for general host adapter properties
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* This is followed by an array of per-target parameters, and is tailed off
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* with a checksum xor byte at offset 256. For non-byte entities data is
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* stored in Little Endian order.
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*/
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#define ISP1080_NVRAM_SIZE 256
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#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c)
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/* Offset 5 */
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/*
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uint8_t bios_configuration_mode :2;
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uint8_t bios_disable :1;
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uint8_t selectable_scsi_boot_enable :1;
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uint8_t cd_rom_boot_enable :1;
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uint8_t disable_loading_risc_code :1;
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uint8_t enable_64bit_addressing :1;
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uint8_t unused_7 :1;
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*/
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/* Offsets 6, 7 */
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/*
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uint8_t boot_lun_number :5;
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uint8_t scsi_bus_number :1;
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uint8_t unused_6 :1;
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uint8_t unused_7 :1;
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uint8_t boot_target_number :4;
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uint8_t unused_12 :1;
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uint8_t unused_13 :1;
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uint8_t unused_14 :1;
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uint8_t unused_15 :1;
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*/
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#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01)
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#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01)
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#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f)
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#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01)
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#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03)
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#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03)
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#define ISP1080_ISP_PARAMETER(c) \
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(((c)[18]) | ((c)[19] << 8))
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#define ISP1080_FAST_POST ISPBSMX(c, 20, 0, 0x01)
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#define ISP1080_REPORT_LVD_TRANSITION ISPBSMX(c, 20, 1, 0x01)
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#define ISP1080_BUS1_OFF 112
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#define ISP1080_NVRAM_INITIATOR_ID(c, b) \
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ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
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#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \
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(c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
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#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \
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(c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
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#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \
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(c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]
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#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \
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ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
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#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \
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ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
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#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \
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ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
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#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \
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(((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
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((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
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#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \
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(((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
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((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))
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#define ISP1080_NVRAM_TARGOFF(b) \
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((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
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#define ISP1080_NVRAM_TARGSIZE 6
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#define _IxT8(tgt, tidx, b) \
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(ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
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#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
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#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
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#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
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#define ISP1080_NVRAM_TGT_TQING(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
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#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
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#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
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#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
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#define ISP1080_NVRAM_TGT_DISC(c, t, b) \
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ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
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#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
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ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
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#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
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ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
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#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
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ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
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#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
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ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
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#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
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ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
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/*
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* Qlogic 2XXX NVRAM is an array of 256 bytes.
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*
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