Allow more VMCB fields to be cached:
- CR2 - CR0, CR3, CR4 and EFER - GDT/IDT base/limit fields - CS/DS/ES/SS selector/base/limit/attrib fields The caching can be further restricted via the tunable 'hw.vmm.svm.vmcb_clean'. Restructure the code such that the fields above are only modified in a single place. This makes it easy to invalidate the VMCB cache when any of these fields is modified.
This commit is contained in:
neel
parent
5834276187
commit
35aaa3ac11
@ -89,16 +89,22 @@ SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW, NULL, NULL);
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VMCB_CACHE_IOPM | \
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VMCB_CACHE_I | \
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VMCB_CACHE_TPR | \
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VMCB_CACHE_CR2 | \
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VMCB_CACHE_CR | \
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VMCB_CACHE_DT | \
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VMCB_CACHE_SEG | \
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VMCB_CACHE_NP)
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static uint32_t vmcb_clean = VMCB_CACHE_DEFAULT;
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SYSCTL_INT(_hw_vmm_svm, OID_AUTO, vmcb_clean, CTLFLAG_RDTUN, &vmcb_clean,
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0, NULL);
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MALLOC_DEFINE(M_SVM, "svm", "svm");
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MALLOC_DEFINE(M_SVM_VLAPIC, "svm-vlapic", "svm-vlapic");
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/* Per-CPU context area. */
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extern struct pcpu __pcpu[];
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static int svm_getdesc(void *arg, int vcpu, int type, struct seg_desc *desc);
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static uint32_t svm_feature; /* AMD SVM features. */
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SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, features, CTLFLAG_RD, &svm_feature, 0,
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"SVM features advertised by CPUID.8000000AH:EDX");
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@ -129,6 +135,8 @@ static VMM_STAT_AMD(VCPU_EXITINTINFO, "VM exits during event delivery");
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static VMM_STAT_AMD(VCPU_INTINFO_INJECTED, "Events pending at VM entry");
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static VMM_STAT_AMD(VMEXIT_VINTR, "VM exits due to interrupt window");
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static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val);
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/*
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* Common function to enable or disabled SVM for a CPU.
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*/
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@ -292,6 +300,8 @@ svm_init(int ipinum)
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if (err)
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return (err);
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vmcb_clean &= VMCB_CACHE_DEFAULT;
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for (cpu = 0; cpu < MAXCPU; cpu++) {
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/*
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* Initialize the host ASIDs to their "highest" valid values.
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@ -410,16 +420,6 @@ svm_msr_rd_ok(uint8_t *perm_bitmap, uint64_t msr)
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return svm_msr_perm(perm_bitmap, msr, true, false);
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}
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static __inline void
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vcpu_set_dirty(struct svm_softc *sc, int vcpu, uint32_t dirtybits)
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{
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struct svm_vcpu *vcpustate;
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vcpustate = svm_get_vcpu(sc, vcpu);
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vcpustate->dirty |= dirtybits;
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}
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static __inline int
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svm_get_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask)
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{
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@ -449,7 +449,7 @@ svm_set_intercept(struct svm_softc *sc, int vcpu, int idx, uint32_t bitmask,
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ctrl->intercept[idx] &= ~bitmask;
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if (ctrl->intercept[idx] != oldval) {
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vcpu_set_dirty(sc, vcpu, VMCB_CACHE_I);
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svm_set_dirty(sc, vcpu, VMCB_CACHE_I);
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VCPU_CTR3(sc->vm, vcpu, "intercept[%d] modified "
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"from %#x to %#x", idx, oldval, ctrl->intercept[idx]);
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}
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@ -592,6 +592,10 @@ svm_vminit(struct vm *vm, pmap_t pmap)
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svm_msr_rw_ok(svm_sc->msr_bitmap, MSR_PAT);
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svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_TSC);
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/*
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* Intercept writes to make sure that the EFER_SVM bit is not cleared.
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*/
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svm_msr_rd_ok(svm_sc->msr_bitmap, MSR_EFER);
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/* Intercept access to all I/O ports. */
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@ -627,18 +631,22 @@ svm_cpl(struct vmcb_state *state)
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static enum vm_cpu_mode
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svm_vcpu_mode(struct vmcb *vmcb)
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{
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struct vmcb_segment *seg;
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struct vmcb_segment seg;
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struct vmcb_state *state;
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int error;
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state = &vmcb->state;
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if (state->efer & EFER_LMA) {
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seg = vmcb_seg(vmcb, VM_REG_GUEST_CS);
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error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg);
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KASSERT(error == 0, ("%s: vmcb_seg(cs) error %d", __func__,
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error));
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/*
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* Section 4.8.1 for APM2, check if Code Segment has
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* Long attribute set in descriptor.
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*/
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if (seg->attrib & VMCB_CS_ATTRIB_L)
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if (seg.attrib & VMCB_CS_ATTRIB_L)
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return (CPU_MODE_64BIT);
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else
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return (CPU_MODE_COMPATIBILITY);
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@ -700,7 +708,7 @@ svm_inout_str_seginfo(struct svm_softc *svm_sc, int vcpu, int64_t info1,
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vis->seg_name = vm_segment_name(s);
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}
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error = svm_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc);
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error = vmcb_getdesc(svm_sc, vcpu, vis->seg_name, &vis->seg_desc);
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KASSERT(error == 0, ("%s: svm_getdesc error %d", __func__, error));
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}
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@ -824,10 +832,10 @@ static void
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svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit)
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{
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struct vm_guest_paging *paging;
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struct vmcb_segment *seg;
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struct vmcb_segment seg;
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struct vmcb_ctrl *ctrl;
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char *inst_bytes;
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int inst_len;
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int error, inst_len;
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ctrl = &vmcb->ctrl;
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paging = &vmexit->u.inst_emul.paging;
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@ -837,14 +845,16 @@ svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit)
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vmexit->u.inst_emul.gla = VIE_INVALID_GLA;
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svm_paging_info(vmcb, paging);
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seg = vmcb_seg(vmcb, VM_REG_GUEST_CS);
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error = vmcb_seg(vmcb, VM_REG_GUEST_CS, &seg);
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KASSERT(error == 0, ("%s: vmcb_seg(CS) error %d", __func__, error));
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switch(paging->cpu_mode) {
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case CPU_MODE_PROTECTED:
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case CPU_MODE_COMPATIBILITY:
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/*
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* Section 4.8.1 of APM2, Default Operand Size or D bit.
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*/
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vmexit->u.inst_emul.cs_d = (seg->attrib & VMCB_CS_ATTRIB_D) ?
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vmexit->u.inst_emul.cs_d = (seg.attrib & VMCB_CS_ATTRIB_D) ?
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1 : 0;
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break;
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default:
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@ -865,28 +875,6 @@ svm_handle_inst_emul(struct vmcb *vmcb, uint64_t gpa, struct vm_exit *vmexit)
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vie_init(&vmexit->u.inst_emul.vie, inst_bytes, inst_len);
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}
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/*
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* Intercept access to MSR_EFER to prevent the guest from clearing the
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* SVM enable bit.
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*/
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static int
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svm_write_efer(struct svm_softc *sc, int vcpu, uint64_t val)
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{
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struct vmcb_state *state;
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uint64_t oldval;
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state = svm_get_vmcb_state(sc, vcpu);
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oldval = state->efer;
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state->efer = val | EFER_SVM;
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if (state->efer != oldval) {
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VCPU_CTR2(sc->vm, vcpu, "Guest EFER changed from %#lx to %#lx",
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oldval, state->efer);
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vcpu_set_dirty(sc, vcpu, VMCB_CACHE_CR);
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}
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return (0);
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}
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#ifdef KTR
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static const char *
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intrtype_to_str(int intr_type)
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@ -1028,7 +1016,7 @@ enable_intr_window_exiting(struct svm_softc *sc, int vcpu)
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ctrl->v_irq = 1;
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ctrl->v_ign_tpr = 1;
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ctrl->v_intr_vector = 0;
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vcpu_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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svm_enable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR);
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}
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@ -1053,7 +1041,7 @@ disable_intr_window_exiting(struct svm_softc *sc, int vcpu)
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#endif
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ctrl->v_irq = 0;
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ctrl->v_intr_vector = 0;
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vcpu_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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svm_disable_intercept(sc, vcpu, VMCB_CTRL1_INTCPT, VMCB_INTCPT_VINTR);
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}
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@ -1144,7 +1132,7 @@ emulate_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val,
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if (lapic_msr(num))
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error = lapic_wrmsr(sc->vm, vcpu, num, val, retu);
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else if (num == MSR_EFER)
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error = svm_write_efer(sc, vcpu, val);
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error = svm_setreg(sc, vcpu, VM_REG_GUEST_EFER, val);
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else
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error = svm_wrmsr(sc, vcpu, num, val, retu);
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@ -1622,7 +1610,7 @@ svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic)
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VCPU_CTR2(sc->vm, vcpu, "VMCB V_TPR changed from %#x to %#x",
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ctrl->v_tpr, v_tpr);
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ctrl->v_tpr = v_tpr;
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vcpu_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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}
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if (pending_apic_vector) {
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@ -1638,7 +1626,7 @@ svm_inj_interrupts(struct svm_softc *sc, int vcpu, struct vlapic *vlapic)
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ctrl->v_ign_tpr = 0;
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ctrl->v_intr_vector = pending_apic_vector;
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ctrl->v_intr_prio = pending_apic_vector >> 4;
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vcpu_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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svm_set_dirty(sc, vcpu, VMCB_CACHE_TPR);
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} else if (need_intr_window) {
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/*
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* We use V_IRQ in conjunction with the VINTR intercept to
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@ -1764,7 +1752,7 @@ check_asid(struct svm_softc *sc, int vcpuid, pmap_t pmap, u_int thiscpu)
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vcpustate->asid.num = asid[thiscpu].num;
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ctrl->asid = vcpustate->asid.num;
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vcpu_set_dirty(sc, vcpuid, VMCB_CACHE_ASID);
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svm_set_dirty(sc, vcpuid, VMCB_CACHE_ASID);
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/*
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* If this cpu supports "flush-by-asid" then the TLB
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* was not flushed after the generation bump. The TLB
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@ -1830,7 +1818,7 @@ svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap,
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/*
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* Invalidate the VMCB state cache by marking all fields dirty.
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*/
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vcpu_set_dirty(svm_sc, vcpu, 0xffffffff);
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svm_set_dirty(svm_sc, vcpu, 0xffffffff);
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/*
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* XXX
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@ -1891,7 +1879,7 @@ svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap,
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*/
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check_asid(svm_sc, vcpu, pmap, thiscpu);
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ctrl->vmcb_clean = VMCB_CACHE_DEFAULT & ~vcpustate->dirty;
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ctrl->vmcb_clean = vmcb_clean & ~vcpustate->dirty;
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vcpustate->dirty = 0;
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VCPU_CTR1(vm, vcpu, "vmcb clean %#x", ctrl->vmcb_clean);
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@ -2001,17 +1989,15 @@ static int
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svm_getreg(void *arg, int vcpu, int ident, uint64_t *val)
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{
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struct svm_softc *svm_sc;
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struct vmcb *vmcb;
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register_t *reg;
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svm_sc = arg;
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vmcb = svm_get_vmcb(svm_sc, vcpu);
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if (ident == VM_REG_GUEST_INTR_SHADOW) {
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return (svm_get_intr_shadow(svm_sc, vcpu, val));
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}
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if (vmcb_read(vmcb, ident, val) == 0) {
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if (vmcb_read(svm_sc, vcpu, ident, val) == 0) {
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return (0);
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}
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@ -2034,17 +2020,15 @@ static int
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svm_setreg(void *arg, int vcpu, int ident, uint64_t val)
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{
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struct svm_softc *svm_sc;
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struct vmcb *vmcb;
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register_t *reg;
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svm_sc = arg;
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vmcb = svm_get_vmcb(svm_sc, vcpu);
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if (ident == VM_REG_GUEST_INTR_SHADOW) {
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return (svm_modify_intr_shadow(svm_sc, vcpu, val));
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}
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if (vmcb_write(vmcb, ident, val) == 0) {
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if (vmcb_write(svm_sc, vcpu, ident, val) == 0) {
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return (0);
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}
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@ -2065,81 +2049,6 @@ svm_setreg(void *arg, int vcpu, int ident, uint64_t val)
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return (EINVAL);
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}
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/*
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* Inteface to set various descriptors.
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*/
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static int
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svm_setdesc(void *arg, int vcpu, int type, struct seg_desc *desc)
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{
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struct svm_softc *svm_sc;
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struct vmcb *vmcb;
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struct vmcb_segment *seg;
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uint16_t attrib;
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svm_sc = arg;
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vmcb = svm_get_vmcb(svm_sc, vcpu);
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VCPU_CTR1(svm_sc->vm, vcpu, "SVM:set_desc: Type%d\n", type);
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seg = vmcb_seg(vmcb, type);
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if (seg == NULL) {
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ERR("SVM_ERR:Unsupported segment type%d\n", type);
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return (EINVAL);
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}
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/* Map seg_desc access to VMCB attribute format.*/
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attrib = ((desc->access & 0xF000) >> 4) | (desc->access & 0xFF);
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VCPU_CTR3(svm_sc->vm, vcpu, "SVM:[sel %d attribute 0x%x limit:0x%x]\n",
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type, desc->access, desc->limit);
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seg->attrib = attrib;
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seg->base = desc->base;
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seg->limit = desc->limit;
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return (0);
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}
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/*
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* Interface to get guest descriptor.
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*/
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static int
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svm_getdesc(void *arg, int vcpu, int type, struct seg_desc *desc)
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{
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struct svm_softc *svm_sc;
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struct vmcb_segment *seg;
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svm_sc = arg;
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VCPU_CTR1(svm_sc->vm, vcpu, "SVM:get_desc: Type%d\n", type);
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seg = vmcb_seg(svm_get_vmcb(svm_sc, vcpu), type);
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if (!seg) {
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ERR("SVM_ERR:Unsupported segment type%d\n", type);
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return (EINVAL);
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}
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/* Map seg_desc access to VMCB attribute format.*/
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desc->access = ((seg->attrib & 0xF00) << 4) | (seg->attrib & 0xFF);
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desc->base = seg->base;
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desc->limit = seg->limit;
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/*
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* VT-x uses bit 16 (Unusable) to indicate a segment that has been
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* loaded with a NULL segment selector. The 'desc->access' field is
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* interpreted in the VT-x format by the processor-independent code.
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*
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* SVM uses the 'P' bit to convey the same information so convert it
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* into the VT-x format. For more details refer to section
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* "Segment State in the VMCB" in APMv2.
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*/
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if (type == VM_REG_GUEST_CS && type == VM_REG_GUEST_TR)
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desc->access |= 0x80; /* CS and TS always present */
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if (!(desc->access & 0x80))
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desc->access |= 0x10000; /* Unusable segment */
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return (0);
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}
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static int
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svm_setcap(void *arg, int vcpu, int type, int val)
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{
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@ -2231,8 +2140,8 @@ struct vmm_ops vmm_ops_amd = {
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svm_vmcleanup,
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svm_getreg,
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svm_setreg,
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svm_getdesc,
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svm_setdesc,
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vmcb_getdesc,
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vmcb_setdesc,
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svm_getcap,
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svm_setcap,
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svm_npt_alloc,
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@ -92,25 +92,4 @@ enable_gintr(void)
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__asm __volatile("stgi" : : :);
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}
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static __inline void
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save_cr2(uint64_t *cr2)
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{
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__asm __volatile(
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"mov %%cr2, %%rax; movq %%rax, %0"
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:"=m"(*cr2)
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:
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:"rax", "memory");
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}
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static __inline void
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load_cr2(uint64_t *cr2)
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{
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__asm __volatile(
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"movq %0, %%rax; movq %%rax, %%cr2"
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:
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:"m"(*cr2)
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:"rax");
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}
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#endif /* _SVM_H_ */
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@ -116,5 +116,14 @@ svm_get_guest_regctx(struct svm_softc *sc, int vcpu)
|
||||
return (&(sc->vcpu[vcpu].swctx));
|
||||
}
|
||||
|
||||
void svm_dump_vmcb(struct svm_softc *svm_sc, int vcpu);
|
||||
static __inline void
|
||||
svm_set_dirty(struct svm_softc *sc, int vcpu, uint32_t dirtybits)
|
||||
{
|
||||
struct svm_vcpu *vcpustate;
|
||||
|
||||
vcpustate = svm_get_vcpu(sc, vcpu);
|
||||
|
||||
vcpustate->dirty |= dirtybits;
|
||||
}
|
||||
|
||||
#endif /* _SVM_SOFTC_H_ */
|
||||
|
||||
@ -35,8 +35,11 @@ __FBSDID("$FreeBSD$");
|
||||
#include <machine/specialreg.h>
|
||||
#include <machine/vmm.h>
|
||||
|
||||
#include "vmm_ktr.h"
|
||||
|
||||
#include "vmcb.h"
|
||||
#include "svm.h"
|
||||
#include "svm_softc.h"
|
||||
|
||||
/*
|
||||
* The VMCB aka Virtual Machine Control Block is a 4KB aligned page
|
||||
@ -48,175 +51,11 @@ __FBSDID("$FreeBSD$");
|
||||
* - guest processor state (e.g. general purpose registers)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Read from segment selector, control and general purpose register of VMCB.
|
||||
*/
|
||||
int
|
||||
vmcb_read(struct vmcb *vmcb, int ident, uint64_t *retval)
|
||||
{
|
||||
struct vmcb_state *state;
|
||||
struct vmcb_segment *seg;
|
||||
int err;
|
||||
|
||||
state = &vmcb->state;
|
||||
err = 0;
|
||||
|
||||
switch (ident) {
|
||||
case VM_REG_GUEST_CR0:
|
||||
*retval = state->cr0;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR2:
|
||||
*retval = state->cr2;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR3:
|
||||
*retval = state->cr3;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR4:
|
||||
*retval = state->cr4;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_DR7:
|
||||
*retval = state->dr7;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_EFER:
|
||||
*retval = state->efer;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RAX:
|
||||
*retval = state->rax;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RFLAGS:
|
||||
*retval = state->rflags;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RIP:
|
||||
*retval = state->rip;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RSP:
|
||||
*retval = state->rsp;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CS:
|
||||
case VM_REG_GUEST_DS:
|
||||
case VM_REG_GUEST_ES:
|
||||
case VM_REG_GUEST_FS:
|
||||
case VM_REG_GUEST_GS:
|
||||
case VM_REG_GUEST_SS:
|
||||
case VM_REG_GUEST_GDTR:
|
||||
case VM_REG_GUEST_IDTR:
|
||||
case VM_REG_GUEST_LDTR:
|
||||
case VM_REG_GUEST_TR:
|
||||
seg = vmcb_seg(vmcb, ident);
|
||||
if (seg == NULL) {
|
||||
ERR("Invalid seg type %d\n", ident);
|
||||
err = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
*retval = seg->selector;
|
||||
break;
|
||||
|
||||
default:
|
||||
err = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return (err);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write to segment selector, control and general purpose register of VMCB.
|
||||
*/
|
||||
int
|
||||
vmcb_write(struct vmcb *vmcb, int ident, uint64_t val)
|
||||
{
|
||||
struct vmcb_state *state;
|
||||
struct vmcb_segment *seg;
|
||||
int err;
|
||||
|
||||
state = &vmcb->state;
|
||||
err = 0;
|
||||
|
||||
switch (ident) {
|
||||
case VM_REG_GUEST_CR0:
|
||||
state->cr0 = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR2:
|
||||
state->cr2 = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR3:
|
||||
state->cr3 = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR4:
|
||||
state->cr4 = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_DR7:
|
||||
state->dr7 = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_EFER:
|
||||
/* EFER_SVM must always be set when the guest is executing */
|
||||
state->efer = val | EFER_SVM;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RAX:
|
||||
state->rax = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RFLAGS:
|
||||
state->rflags = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RIP:
|
||||
state->rip = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RSP:
|
||||
state->rsp = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CS:
|
||||
case VM_REG_GUEST_DS:
|
||||
case VM_REG_GUEST_ES:
|
||||
case VM_REG_GUEST_FS:
|
||||
case VM_REG_GUEST_GS:
|
||||
case VM_REG_GUEST_SS:
|
||||
case VM_REG_GUEST_GDTR:
|
||||
case VM_REG_GUEST_IDTR:
|
||||
case VM_REG_GUEST_LDTR:
|
||||
case VM_REG_GUEST_TR:
|
||||
seg = vmcb_seg(vmcb, ident);
|
||||
if (seg == NULL) {
|
||||
ERR("Invalid segment type %d\n", ident);
|
||||
err = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
seg->selector = val;
|
||||
break;
|
||||
|
||||
default:
|
||||
err = EINVAL;
|
||||
}
|
||||
|
||||
return (err);
|
||||
}
|
||||
|
||||
/*
|
||||
* Return VMCB segment area.
|
||||
*/
|
||||
struct vmcb_segment *
|
||||
vmcb_seg(struct vmcb *vmcb, int type)
|
||||
static struct vmcb_segment *
|
||||
vmcb_segptr(struct vmcb *vmcb, int type)
|
||||
{
|
||||
struct vmcb_state *state;
|
||||
struct vmcb_segment *seg;
|
||||
@ -271,3 +110,285 @@ vmcb_seg(struct vmcb *vmcb, int type)
|
||||
|
||||
return (seg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read from segment selector, control and general purpose register of VMCB.
|
||||
*/
|
||||
int
|
||||
vmcb_read(struct svm_softc *sc, int vcpu, int ident, uint64_t *retval)
|
||||
{
|
||||
struct vmcb *vmcb;
|
||||
struct vmcb_state *state;
|
||||
struct vmcb_segment *seg;
|
||||
int err;
|
||||
|
||||
vmcb = svm_get_vmcb(sc, vcpu);
|
||||
state = &vmcb->state;
|
||||
err = 0;
|
||||
|
||||
switch (ident) {
|
||||
case VM_REG_GUEST_CR0:
|
||||
*retval = state->cr0;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR2:
|
||||
*retval = state->cr2;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR3:
|
||||
*retval = state->cr3;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR4:
|
||||
*retval = state->cr4;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_DR7:
|
||||
*retval = state->dr7;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_EFER:
|
||||
*retval = state->efer;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RAX:
|
||||
*retval = state->rax;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RFLAGS:
|
||||
*retval = state->rflags;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RIP:
|
||||
*retval = state->rip;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RSP:
|
||||
*retval = state->rsp;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CS:
|
||||
case VM_REG_GUEST_DS:
|
||||
case VM_REG_GUEST_ES:
|
||||
case VM_REG_GUEST_FS:
|
||||
case VM_REG_GUEST_GS:
|
||||
case VM_REG_GUEST_SS:
|
||||
case VM_REG_GUEST_LDTR:
|
||||
case VM_REG_GUEST_TR:
|
||||
seg = vmcb_segptr(vmcb, ident);
|
||||
KASSERT(seg != NULL, ("%s: unable to get segment %d from VMCB",
|
||||
__func__, ident));
|
||||
*retval = seg->selector;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_GDTR:
|
||||
case VM_REG_GUEST_IDTR:
|
||||
/* GDTR and IDTR don't have segment selectors */
|
||||
err = EINVAL;
|
||||
break;
|
||||
default:
|
||||
err = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return (err);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write to segment selector, control and general purpose register of VMCB.
|
||||
*/
|
||||
int
|
||||
vmcb_write(struct svm_softc *sc, int vcpu, int ident, uint64_t val)
|
||||
{
|
||||
struct vmcb *vmcb;
|
||||
struct vmcb_state *state;
|
||||
struct vmcb_segment *seg;
|
||||
int err, dirtyseg;
|
||||
|
||||
vmcb = svm_get_vmcb(sc, vcpu);
|
||||
state = &vmcb->state;
|
||||
dirtyseg = 0;
|
||||
err = 0;
|
||||
|
||||
switch (ident) {
|
||||
case VM_REG_GUEST_CR0:
|
||||
state->cr0 = val;
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_CR);
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR2:
|
||||
state->cr2 = val;
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_CR2);
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR3:
|
||||
state->cr3 = val;
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_CR);
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CR4:
|
||||
state->cr4 = val;
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_CR);
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_DR7:
|
||||
state->dr7 = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_EFER:
|
||||
/* EFER_SVM must always be set when the guest is executing */
|
||||
state->efer = val | EFER_SVM;
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_CR);
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RAX:
|
||||
state->rax = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RFLAGS:
|
||||
state->rflags = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RIP:
|
||||
state->rip = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_RSP:
|
||||
state->rsp = val;
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_CS:
|
||||
case VM_REG_GUEST_DS:
|
||||
case VM_REG_GUEST_ES:
|
||||
case VM_REG_GUEST_SS:
|
||||
dirtyseg = 1; /* FALLTHROUGH */
|
||||
case VM_REG_GUEST_FS:
|
||||
case VM_REG_GUEST_GS:
|
||||
case VM_REG_GUEST_LDTR:
|
||||
case VM_REG_GUEST_TR:
|
||||
seg = vmcb_segptr(vmcb, ident);
|
||||
KASSERT(seg != NULL, ("%s: unable to get segment %d from VMCB",
|
||||
__func__, ident));
|
||||
seg->selector = val;
|
||||
if (dirtyseg)
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_SEG);
|
||||
break;
|
||||
|
||||
case VM_REG_GUEST_GDTR:
|
||||
case VM_REG_GUEST_IDTR:
|
||||
/* GDTR and IDTR don't have segment selectors */
|
||||
err = EINVAL;
|
||||
break;
|
||||
default:
|
||||
err = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return (err);
|
||||
}
|
||||
|
||||
int
|
||||
vmcb_seg(struct vmcb *vmcb, int ident, struct vmcb_segment *seg2)
|
||||
{
|
||||
struct vmcb_segment *seg;
|
||||
|
||||
seg = vmcb_segptr(vmcb, ident);
|
||||
if (seg != NULL) {
|
||||
bcopy(seg, seg2, sizeof(struct vmcb_segment));
|
||||
return (0);
|
||||
} else {
|
||||
return (EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
vmcb_setdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
|
||||
{
|
||||
struct vmcb *vmcb;
|
||||
struct svm_softc *sc;
|
||||
struct vmcb_segment *seg;
|
||||
uint16_t attrib;
|
||||
|
||||
sc = arg;
|
||||
vmcb = svm_get_vmcb(sc, vcpu);
|
||||
|
||||
seg = vmcb_segptr(vmcb, reg);
|
||||
KASSERT(seg != NULL, ("%s: invalid segment descriptor %d",
|
||||
__func__, reg));
|
||||
|
||||
seg->base = desc->base;
|
||||
seg->limit = desc->limit;
|
||||
if (reg != VM_REG_GUEST_GDTR && reg != VM_REG_GUEST_IDTR) {
|
||||
/*
|
||||
* Map seg_desc access to VMCB attribute format.
|
||||
*
|
||||
* SVM uses the 'P' bit in the segment attributes to indicate a
|
||||
* NULL segment so clear it if the segment is marked unusable.
|
||||
*/
|
||||
attrib = ((desc->access & 0xF000) >> 4) | (desc->access & 0xFF);
|
||||
if (SEG_DESC_UNUSABLE(desc->access)) {
|
||||
attrib &= ~0x80;
|
||||
}
|
||||
seg->attrib = attrib;
|
||||
}
|
||||
|
||||
VCPU_CTR4(sc->vm, vcpu, "Setting desc %d: base (%#lx), limit (%#x), "
|
||||
"attrib (%#x)", reg, seg->base, seg->limit, seg->attrib);
|
||||
|
||||
switch (reg) {
|
||||
case VM_REG_GUEST_CS:
|
||||
case VM_REG_GUEST_DS:
|
||||
case VM_REG_GUEST_ES:
|
||||
case VM_REG_GUEST_SS:
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_SEG);
|
||||
case VM_REG_GUEST_GDTR:
|
||||
case VM_REG_GUEST_IDTR:
|
||||
svm_set_dirty(sc, vcpu, VMCB_CACHE_DT);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
vmcb_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
|
||||
{
|
||||
struct vmcb *vmcb;
|
||||
struct svm_softc *sc;
|
||||
struct vmcb_segment *seg;
|
||||
|
||||
sc = arg;
|
||||
vmcb = svm_get_vmcb(sc, vcpu);
|
||||
seg = vmcb_segptr(vmcb, reg);
|
||||
KASSERT(seg != NULL, ("%s: invalid segment descriptor %d",
|
||||
__func__, reg));
|
||||
|
||||
desc->base = seg->base;
|
||||
desc->limit = seg->limit;
|
||||
desc->access = 0;
|
||||
|
||||
if (reg != VM_REG_GUEST_GDTR && reg != VM_REG_GUEST_IDTR) {
|
||||
/* Map seg_desc access to VMCB attribute format */
|
||||
desc->access = ((seg->attrib & 0xF00) << 4) |
|
||||
(seg->attrib & 0xFF);
|
||||
|
||||
/*
|
||||
* VT-x uses bit 16 to indicate a segment that has been loaded
|
||||
* with a NULL selector (aka unusable). The 'desc->access'
|
||||
* field is interpreted in the VT-x format by the
|
||||
* processor-independent code.
|
||||
*
|
||||
* SVM uses the 'P' bit to convey the same information so
|
||||
* convert it into the VT-x format. For more details refer to
|
||||
* section "Segment State in the VMCB" in APMv2.
|
||||
*/
|
||||
if (reg != VM_REG_GUEST_CS && reg != VM_REG_GUEST_TR) {
|
||||
if ((desc->access & 0x80) == 0)
|
||||
desc->access |= 0x10000; /* Unusable segment */
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -29,6 +29,8 @@
|
||||
#ifndef _VMCB_H_
|
||||
#define _VMCB_H_
|
||||
|
||||
struct svm_softc;
|
||||
|
||||
/*
|
||||
* Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15
|
||||
* Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B
|
||||
@ -279,8 +281,10 @@ struct vmcb {
|
||||
CTASSERT(sizeof(struct vmcb) == PAGE_SIZE);
|
||||
CTASSERT(offsetof(struct vmcb, state) == 0x400);
|
||||
|
||||
int vmcb_read(struct vmcb *vmcb, int ident, uint64_t *retval);
|
||||
int vmcb_write(struct vmcb *vmcb, int ident, uint64_t val);
|
||||
struct vmcb_segment *vmcb_seg(struct vmcb *vmcb, int type);
|
||||
int vmcb_read(struct svm_softc *sc, int vcpu, int ident, uint64_t *retval);
|
||||
int vmcb_write(struct svm_softc *sc, int vcpu, int ident, uint64_t val);
|
||||
int vmcb_setdesc(void *arg, int vcpu, int ident, struct seg_desc *desc);
|
||||
int vmcb_getdesc(void *arg, int vcpu, int ident, struct seg_desc *desc);
|
||||
int vmcb_seg(struct vmcb *vmcb, int ident, struct vmcb_segment *seg);
|
||||
|
||||
#endif /* _VMCB_H_ */
|
||||
|
||||
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Reference in New Issue
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