Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on actual hardware driver for register access. sdhci_pci implements driver for PCI SDHC controllers using new SDHCI interface No kernel config modifications are required, but if you load sdhc as a module you must switch to sdhci_pci instead.
This commit is contained in:
parent
867cb9c7c5
commit
36548e3e1a
6
UPDATING
6
UPDATING
@ -24,6 +24,12 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 10.x IS SLOW:
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disable the most expensive debugging functionality run
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"ln -s 'abort:false,junk:false' /etc/malloc.conf".)
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20121015:
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The sdhci driver was split in two parts: sdhci (generic SD Host
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Controller logic) and sdhci_pci (actual hardware driver).
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No kernel config modifications are required, but if you
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load sdhc as a module you must switch to sdhci_pci instead.
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20121014:
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Import the FUSE kernel and userland support into base system.
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@ -1905,7 +1905,9 @@ dev/scc/scc_dev_sab82532.c optional scc
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dev/scc/scc_dev_z8530.c optional scc
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dev/scd/scd.c optional scd isa
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dev/scd/scd_isa.c optional scd isa
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dev/sdhci/sdhci.c optional sdhci pci
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dev/sdhci/sdhci.c optional sdhci
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dev/sdhci/sdhci_if.m optional sdhci
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dev/sdhci/sdhci_pci.c optional sdhci pci
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dev/sf/if_sf.c optional sf pci
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dev/sge/if_sge.c optional sge pci
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dev/si/si.c optional si
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@ -345,7 +345,8 @@ MFILES?= dev/acpica/acpi_if.m dev/acpi_support/acpi_wmi_if.m \
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dev/mmc/mmcbr_if.m dev/mmc/mmcbus_if.m \
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dev/mii/miibus_if.m dev/mvs/mvs_if.m dev/ofw/ofw_bus_if.m \
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dev/pccard/card_if.m dev/pccard/power_if.m dev/pci/pci_if.m \
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dev/pci/pcib_if.m dev/ppbus/ppbus_if.m dev/smbus/smbus_if.m \
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dev/pci/pcib_if.m dev/ppbus/ppbus_if.m \
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dev/sdhci/sdhci_if.m dev/smbus/smbus_if.m \
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dev/sound/pci/hda/hdac_if.m \
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dev/sound/pcm/ac97_if.m dev/sound/pcm/channel_if.m \
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dev/sound/pcm/feeder_if.m dev/sound/pcm/mixer_if.m \
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@ -1730,4 +1730,4 @@ static devclass_t mmc_devclass;
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DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci, mmc_driver, mmc_devclass, NULL, NULL);
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DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL);
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@ -39,9 +39,6 @@ __FBSDID("$FreeBSD$");
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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@ -52,104 +49,12 @@ __FBSDID("$FreeBSD$");
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#include "mmcbr_if.h"
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#include "sdhci.h"
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#define DMA_BLOCK_SIZE 4096
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#define DMA_BOUNDARY 0 /* DMA reload every 4K */
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/* Controller doesn't honor resets unless we touch the clock register */
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#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
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/* Controller really supports DMA */
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#define SDHCI_QUIRK_FORCE_DMA (1<<1)
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/* Controller has unusable DMA engine */
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#define SDHCI_QUIRK_BROKEN_DMA (1<<2)
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/* Controller doesn't like to be reset when there is no card inserted. */
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#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
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/* Controller has flaky internal state so reset it on each ios change */
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#define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
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/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
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#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
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/* Controller needs to be reset after each request to stay stable */
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#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
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/* Controller has an off-by-one issue with timeout value */
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#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
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/* Controller has broken read timings */
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#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
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/* Controller needs lowered frequency */
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#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
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static const struct sdhci_device {
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uint32_t model;
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uint16_t subvendor;
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char *desc;
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u_int quirks;
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} sdhci_devices[] = {
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{ 0x08221180, 0xffff, "RICOH R5C822 SD",
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SDHCI_QUIRK_FORCE_DMA },
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{ 0xe8221180, 0xffff, "RICOH SD",
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SDHCI_QUIRK_FORCE_DMA },
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{ 0xe8231180, 0xffff, "RICOH R5CE823 SD",
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SDHCI_QUIRK_LOWER_FREQUENCY },
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{ 0x8034104c, 0xffff, "TI XX21/XX11 SD",
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SDHCI_QUIRK_FORCE_DMA },
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{ 0x05501524, 0xffff, "ENE CB712 SD",
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x05511524, 0xffff, "ENE CB712 SD 2",
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x07501524, 0xffff, "ENE CB714 SD",
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SDHCI_QUIRK_RESET_ON_IOS |
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x07511524, 0xffff, "ENE CB714 SD 2",
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SDHCI_QUIRK_RESET_ON_IOS |
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SDHCI_QUIRK_BROKEN_TIMINGS },
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{ 0x410111ab, 0xffff, "Marvell CaFe SD",
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SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
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{ 0x2381197B, 0xffff, "JMicron JMB38X SD",
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_RESET_AFTER_REQUEST },
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{ 0, 0xffff, NULL,
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0 }
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};
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#include "sdhci_if.h"
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struct sdhci_softc;
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struct sdhci_slot {
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struct sdhci_softc *sc;
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device_t dev; /* Slot device */
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u_char num; /* Slot number */
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u_char opt; /* Slot options */
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#define SDHCI_HAVE_DMA 1
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uint32_t max_clk; /* Max possible freq */
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uint32_t timeout_clk; /* Timeout freq */
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struct resource *mem_res; /* Memory resource */
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int mem_rid;
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bus_dma_tag_t dmatag;
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bus_dmamap_t dmamap;
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u_char *dmamem;
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bus_addr_t paddr; /* DMA buffer address */
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struct task card_task; /* Card presence check task */
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struct callout card_callout; /* Card insert delay callout */
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struct mmc_host host; /* Host parameters */
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struct mmc_request *req; /* Current request */
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struct mmc_command *curcmd; /* Current command of current request */
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uint32_t intmask; /* Current interrupt mask */
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uint32_t clock; /* Current clock freq. */
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size_t offset; /* Data buffer offset */
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uint8_t hostctrl; /* Current host control register */
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u_char power; /* Current power */
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u_char bus_busy; /* Bus busy status */
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u_char cmd_done; /* CMD command part done flag */
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u_char data_done; /* DAT command part done flag */
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u_char flags; /* Request execution flags */
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#define CMD_STARTED 1
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#define STOP_STARTED 2
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#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
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struct mtx mtx; /* Slot mutex */
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};
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struct sdhci_softc {
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device_t dev; /* Controller device */
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u_int quirks; /* Chip specific quirks */
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struct resource *irq_res; /* IRQ resource */
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int irq_rid;
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void *intrhand; /* Interrupt handle */
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@ -160,63 +65,21 @@ struct sdhci_softc {
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static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
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int sdhci_debug;
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int sdhci_debug = 0;
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TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
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SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
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static inline uint8_t
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RD1(struct sdhci_slot *slot, bus_size_t off)
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{
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bus_barrier(slot->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_1(slot->mem_res, off);
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}
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#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
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#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
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#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
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#define RD_MULTI_4(slot, off, ptr, count) \
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SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
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static inline void
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WR1(struct sdhci_slot *slot, bus_size_t off, uint8_t val)
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{
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bus_barrier(slot->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_1(slot->mem_res, off, val);
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}
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static inline uint16_t
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RD2(struct sdhci_slot *slot, bus_size_t off)
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{
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bus_barrier(slot->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_2(slot->mem_res, off);
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}
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static inline void
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WR2(struct sdhci_slot *slot, bus_size_t off, uint16_t val)
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{
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bus_barrier(slot->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_2(slot->mem_res, off, val);
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}
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static inline uint32_t
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RD4(struct sdhci_slot *slot, bus_size_t off)
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{
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bus_barrier(slot->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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return bus_read_4(slot->mem_res, off);
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}
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static inline void
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WR4(struct sdhci_slot *slot, bus_size_t off, uint32_t val)
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{
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bus_barrier(slot->mem_res, 0, 0xFF,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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bus_write_4(slot->mem_res, off, val);
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}
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/* bus entry points */
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static int sdhci_probe(device_t dev);
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static int sdhci_attach(device_t dev);
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static int sdhci_detach(device_t dev);
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static void sdhci_intr(void *);
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#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
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#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
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#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
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#define WR_MULTI_4(slot, off, ptr, count) \
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SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
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static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
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static void sdhci_start(struct sdhci_slot *slot);
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@ -233,21 +96,6 @@ static void sdhci_card_task(void *, int);
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#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
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#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
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static int
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slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
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{
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va_list ap;
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int retval;
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retval = printf("%s-slot%d: ",
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device_get_nameunit(slot->sc->dev), slot->num);
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va_start(ap, fmt);
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retval += vprintf(fmt, ap);
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va_end(ap);
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return (retval);
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}
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static void
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sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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@ -258,6 +106,21 @@ sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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static int
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slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
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{
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va_list ap;
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int retval;
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retval = printf("%s-slot%d: ",
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device_get_nameunit(slot->bus), slot->num);
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va_start(ap, fmt);
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retval += vprintf(fmt, ap);
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va_end(ap);
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return (retval);
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}
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static void
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sdhci_dumpregs(struct sdhci_slot *slot)
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{
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@ -295,7 +158,7 @@ sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
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int timeout;
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uint8_t res;
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if (slot->sc->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
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if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
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if (!(RD4(slot, SDHCI_PRESENT_STATE) &
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SDHCI_CARD_PRESENT))
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return;
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@ -303,7 +166,7 @@ sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
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/* Some controllers need this kick or reset won't work. */
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if ((mask & SDHCI_RESET_ALL) == 0 &&
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(slot->sc->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
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(slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
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uint32_t clock;
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/* This is to force an update */
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@ -353,24 +216,6 @@ sdhci_init(struct sdhci_slot *slot)
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WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
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}
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static void
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sdhci_lower_frequency(device_t dev)
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{
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/* Enable SD2.0 mode. */
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pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
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pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
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pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
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/*
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* Some SD/MMC cards don't work with the default base
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* clock frequency of 200MHz. Lower it to 50MHz.
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*/
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pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
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pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
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pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
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}
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static void
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sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
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{
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@ -427,6 +272,7 @@ sdhci_set_power(struct sdhci_slot *slot, u_char power)
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if (slot->power == power)
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return;
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slot->power = power;
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/* Turn off the power. */
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@ -469,7 +315,7 @@ sdhci_read_block_pio(struct sdhci_slot *slot)
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slot->offset += left;
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/* If we are too fast, broken controllers return zeroes. */
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if (slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
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if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
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DELAY(10);
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/* Handle unalligned and alligned buffer cases. */
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if ((intptr_t)buffer & 3) {
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@ -483,7 +329,7 @@ sdhci_read_block_pio(struct sdhci_slot *slot)
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left -= 4;
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}
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} else {
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bus_read_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
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RD_MULTI_4(slot, SDHCI_BUFFER,
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(uint32_t *)buffer, left >> 2);
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left &= 3;
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}
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@ -523,7 +369,7 @@ sdhci_write_block_pio(struct sdhci_slot *slot)
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WR4(slot, SDHCI_BUFFER, data);
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}
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} else {
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bus_write_multi_stream_4(slot->mem_res, SDHCI_BUFFER,
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WR_MULTI_4(slot, SDHCI_BUFFER,
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(uint32_t *)buffer, left >> 2);
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left &= 3;
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}
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@ -577,7 +423,7 @@ sdhci_card_task(void *arg, int pending)
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if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
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if (slot->dev == NULL) {
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/* If card is present - attach mmc bus. */
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slot->dev = device_add_child(slot->sc->dev, "mmc", -1);
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slot->dev = device_add_child(slot->bus, "mmc", -1);
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device_set_ivars(slot->dev, slot);
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SDHCI_UNLOCK(slot);
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device_probe_and_attach(slot->dev);
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@ -589,107 +435,22 @@ sdhci_card_task(void *arg, int pending)
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device_t d = slot->dev;
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slot->dev = NULL;
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SDHCI_UNLOCK(slot);
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device_delete_child(slot->sc->dev, d);
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device_delete_child(slot->bus, d);
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} else
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SDHCI_UNLOCK(slot);
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}
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}
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static int
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sdhci_probe(device_t dev)
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int
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sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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{
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uint32_t model;
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uint16_t subvendor;
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uint8_t class, subclass;
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int i, result;
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model = (uint32_t)pci_get_device(dev) << 16;
|
||||
model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
|
||||
subvendor = pci_get_subvendor(dev);
|
||||
class = pci_get_class(dev);
|
||||
subclass = pci_get_subclass(dev);
|
||||
|
||||
result = ENXIO;
|
||||
for (i = 0; sdhci_devices[i].model != 0; i++) {
|
||||
if (sdhci_devices[i].model == model &&
|
||||
(sdhci_devices[i].subvendor == 0xffff ||
|
||||
sdhci_devices[i].subvendor == subvendor)) {
|
||||
device_set_desc(dev, sdhci_devices[i].desc);
|
||||
result = BUS_PROBE_DEFAULT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (result == ENXIO && class == PCIC_BASEPERIPH &&
|
||||
subclass == PCIS_BASEPERIPH_SDHC) {
|
||||
device_set_desc(dev, "Generic SD HCI");
|
||||
result = BUS_PROBE_GENERIC;
|
||||
}
|
||||
|
||||
return (result);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_attach(device_t dev)
|
||||
{
|
||||
struct sdhci_softc *sc = device_get_softc(dev);
|
||||
uint32_t model;
|
||||
uint16_t subvendor;
|
||||
uint8_t class, subclass, progif;
|
||||
int err, slots, bar, i;
|
||||
|
||||
sc->dev = dev;
|
||||
model = (uint32_t)pci_get_device(dev) << 16;
|
||||
model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
|
||||
subvendor = pci_get_subvendor(dev);
|
||||
class = pci_get_class(dev);
|
||||
subclass = pci_get_subclass(dev);
|
||||
progif = pci_get_progif(dev);
|
||||
/* Apply chip specific quirks. */
|
||||
for (i = 0; sdhci_devices[i].model != 0; i++) {
|
||||
if (sdhci_devices[i].model == model &&
|
||||
(sdhci_devices[i].subvendor == 0xffff ||
|
||||
sdhci_devices[i].subvendor == subvendor)) {
|
||||
sc->quirks = sdhci_devices[i].quirks;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Some controllers need to be bumped into the right mode. */
|
||||
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
|
||||
sdhci_lower_frequency(dev);
|
||||
/* Read slots info from PCI registers. */
|
||||
slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
|
||||
bar = PCI_SLOT_INFO_FIRST_BAR(slots);
|
||||
slots = PCI_SLOT_INFO_SLOTS(slots);
|
||||
if (slots > 6 || bar > 5) {
|
||||
device_printf(dev, "Incorrect slots information (%d, %d).\n",
|
||||
slots, bar);
|
||||
return (EINVAL);
|
||||
}
|
||||
/* Allocate IRQ. */
|
||||
sc->irq_rid = 0;
|
||||
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
|
||||
RF_SHAREABLE | RF_ACTIVE);
|
||||
if (sc->irq_res == NULL) {
|
||||
device_printf(dev, "Can't allocate IRQ\n");
|
||||
return (ENOMEM);
|
||||
}
|
||||
/* Scan all slots. */
|
||||
for (i = 0; i < slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[sc->num_slots];
|
||||
uint32_t caps;
|
||||
int err;
|
||||
|
||||
SDHCI_LOCK_INIT(slot);
|
||||
slot->sc = sc;
|
||||
slot->num = sc->num_slots;
|
||||
/* Allocate memory. */
|
||||
slot->mem_rid = PCIR_BAR(bar + i);
|
||||
slot->mem_res = bus_alloc_resource(dev,
|
||||
SYS_RES_MEMORY, &slot->mem_rid, 0ul, ~0ul, 0x100, RF_ACTIVE);
|
||||
if (slot->mem_res == NULL) {
|
||||
device_printf(dev, "Can't allocate memory\n");
|
||||
SDHCI_LOCK_DESTROY(slot);
|
||||
continue;
|
||||
}
|
||||
slot->num = num;
|
||||
slot->bus = dev;
|
||||
|
||||
/* Allocate DMA tag. */
|
||||
err = bus_dma_tag_create(bus_get_dma_tag(dev),
|
||||
DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
|
||||
@ -700,7 +461,7 @@ sdhci_attach(device_t dev)
|
||||
if (err != 0) {
|
||||
device_printf(dev, "Can't create DMA tag\n");
|
||||
SDHCI_LOCK_DESTROY(slot);
|
||||
continue;
|
||||
return (err);
|
||||
}
|
||||
/* Allocate DMA memory. */
|
||||
err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
|
||||
@ -708,7 +469,7 @@ sdhci_attach(device_t dev)
|
||||
if (err != 0) {
|
||||
device_printf(dev, "Can't alloc DMA memory\n");
|
||||
SDHCI_LOCK_DESTROY(slot);
|
||||
continue;
|
||||
return (err);
|
||||
}
|
||||
/* Map the memory. */
|
||||
err = bus_dmamap_load(slot->dmatag, slot->dmamap,
|
||||
@ -717,15 +478,22 @@ sdhci_attach(device_t dev)
|
||||
if (err != 0 || slot->paddr == 0) {
|
||||
device_printf(dev, "Can't load DMA memory\n");
|
||||
SDHCI_LOCK_DESTROY(slot);
|
||||
continue;
|
||||
if(err)
|
||||
return (err);
|
||||
else
|
||||
return (EFAULT);
|
||||
}
|
||||
|
||||
/* Initialize slot. */
|
||||
sdhci_init(slot);
|
||||
slot->version = (RD2(slot, SDHCI_HOST_VERSION)
|
||||
>> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
|
||||
caps = RD4(slot, SDHCI_CAPABILITIES);
|
||||
/* Calculate base clock frequency. */
|
||||
slot->max_clk =
|
||||
(caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
|
||||
if (slot->max_clk == 0) {
|
||||
slot->max_clk = 50;
|
||||
device_printf(dev, "Hardware doesn't specify base clock "
|
||||
"frequency.\n");
|
||||
}
|
||||
@ -759,13 +527,10 @@ sdhci_attach(device_t dev)
|
||||
/* Decide if we have usable DMA. */
|
||||
if (caps & SDHCI_CAN_DO_DMA)
|
||||
slot->opt |= SDHCI_HAVE_DMA;
|
||||
if (class == PCIC_BASEPERIPH &&
|
||||
subclass == PCIS_BASEPERIPH_SDHC &&
|
||||
progif != PCI_SDHCI_IFDMA)
|
||||
|
||||
if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
|
||||
slot->opt &= ~SDHCI_HAVE_DMA;
|
||||
if (sc->quirks & SDHCI_QUIRK_BROKEN_DMA)
|
||||
slot->opt &= ~SDHCI_HAVE_DMA;
|
||||
if (sc->quirks & SDHCI_QUIRK_FORCE_DMA)
|
||||
if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
|
||||
slot->opt |= SDHCI_HAVE_DMA;
|
||||
|
||||
if (bootverbose || sdhci_debug) {
|
||||
@ -781,37 +546,18 @@ sdhci_attach(device_t dev)
|
||||
|
||||
TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
|
||||
callout_init(&slot->card_callout, 1);
|
||||
sc->num_slots++;
|
||||
}
|
||||
device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
|
||||
/* Activate the interrupt */
|
||||
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
||||
NULL, sdhci_intr, sc, &sc->intrhand);
|
||||
if (err)
|
||||
device_printf(dev, "Can't setup IRQ\n");
|
||||
pci_enable_busmaster(dev);
|
||||
/* Process cards detection. */
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
|
||||
sdhci_card_task(slot, 0);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_detach(device_t dev)
|
||||
void
|
||||
sdhci_start_slot(struct sdhci_slot *slot)
|
||||
{
|
||||
struct sdhci_softc *sc = device_get_softc(dev);
|
||||
int i;
|
||||
sdhci_card_task(slot, 0);
|
||||
}
|
||||
|
||||
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
||||
bus_release_resource(dev, SYS_RES_IRQ,
|
||||
sc->irq_rid, sc->irq_res);
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
int
|
||||
sdhci_cleanup_slot(struct sdhci_slot *slot)
|
||||
{
|
||||
device_t d;
|
||||
|
||||
callout_drain(&slot->card_callout);
|
||||
@ -822,7 +568,7 @@ sdhci_detach(device_t dev)
|
||||
slot->dev = NULL;
|
||||
SDHCI_UNLOCK(slot);
|
||||
if (d != NULL)
|
||||
device_delete_child(dev, d);
|
||||
device_delete_child(slot->bus, d);
|
||||
|
||||
SDHCI_LOCK(slot);
|
||||
sdhci_reset(slot, SDHCI_RESET_ALL);
|
||||
@ -830,40 +576,30 @@ sdhci_detach(device_t dev)
|
||||
bus_dmamap_unload(slot->dmatag, slot->dmamap);
|
||||
bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
|
||||
bus_dma_tag_destroy(slot->dmatag);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
slot->mem_rid, slot->mem_res);
|
||||
|
||||
SDHCI_LOCK_DESTROY(slot);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_suspend(device_t dev)
|
||||
int
|
||||
sdhci_generic_suspend(struct sdhci_slot *slot)
|
||||
{
|
||||
struct sdhci_softc *sc = device_get_softc(dev);
|
||||
int i, err;
|
||||
sdhci_reset(slot, SDHCI_RESET_ALL);
|
||||
|
||||
err = bus_generic_suspend(dev);
|
||||
if (err)
|
||||
return (err);
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_reset(&sc->slots[i], SDHCI_RESET_ALL);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_resume(device_t dev)
|
||||
int
|
||||
sdhci_generic_resume(struct sdhci_slot *slot)
|
||||
{
|
||||
struct sdhci_softc *sc = device_get_softc(dev);
|
||||
int i;
|
||||
sdhci_init(slot);
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_init(&sc->slots[i]);
|
||||
return (bus_generic_resume(dev));
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_update_ios(device_t brdev, device_t reqdev)
|
||||
int
|
||||
sdhci_generic_update_ios(device_t brdev, device_t reqdev)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(reqdev);
|
||||
struct mmc_ios *ios = &slot->host.ios;
|
||||
@ -887,7 +623,7 @@ sdhci_update_ios(device_t brdev, device_t reqdev)
|
||||
slot->hostctrl &= ~SDHCI_CTRL_HISPD;
|
||||
WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
|
||||
/* Some controllers like reset after bus changes. */
|
||||
if(slot->sc->quirks & SDHCI_QUIRK_RESET_ON_IOS)
|
||||
if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
|
||||
sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
|
||||
|
||||
SDHCI_UNLOCK(slot);
|
||||
@ -1009,10 +745,8 @@ sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
|
||||
WR4(slot, SDHCI_ARGUMENT, cmd->arg);
|
||||
/* Set data transfer mode. */
|
||||
sdhci_set_transfer_mode(slot, cmd->data);
|
||||
/* Set command flags. */
|
||||
WR1(slot, SDHCI_COMMAND_FLAGS, flags);
|
||||
/* Start command. */
|
||||
WR1(slot, SDHCI_COMMAND, cmd->opcode);
|
||||
WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
|
||||
}
|
||||
|
||||
static void
|
||||
@ -1075,7 +809,7 @@ sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
|
||||
break;
|
||||
}
|
||||
/* Compensate for an off-by-one error in the CaFe chip.*/
|
||||
if (slot->sc->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
|
||||
if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
|
||||
div++;
|
||||
if (div >= 0xF) {
|
||||
slot_printf(slot, "Timeout too large!\n");
|
||||
@ -1090,11 +824,11 @@ sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
|
||||
if ((slot->opt & SDHCI_HAVE_DMA))
|
||||
slot->flags |= SDHCI_USE_DMA;
|
||||
/* If data is small, broken DMA may return zeroes instead of data, */
|
||||
if ((slot->sc->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
|
||||
if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
|
||||
(data->len <= 512))
|
||||
slot->flags &= ~SDHCI_USE_DMA;
|
||||
/* Some controllers require even block sizes. */
|
||||
if ((slot->sc->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
|
||||
if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
|
||||
((data->len) & 0x3))
|
||||
slot->flags &= ~SDHCI_USE_DMA;
|
||||
/* Load DMA buffer. */
|
||||
@ -1183,7 +917,7 @@ sdhci_start(struct sdhci_slot *slot)
|
||||
if (sdhci_debug > 1)
|
||||
slot_printf(slot, "result: %d\n", req->cmd->error);
|
||||
if (!req->cmd->error &&
|
||||
(slot->sc->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
|
||||
(slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
|
||||
sdhci_reset(slot, SDHCI_RESET_CMD);
|
||||
sdhci_reset(slot, SDHCI_RESET_DATA);
|
||||
}
|
||||
@ -1194,8 +928,8 @@ sdhci_start(struct sdhci_slot *slot)
|
||||
req->done(req);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
|
||||
int
|
||||
sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(reqdev);
|
||||
|
||||
@ -1216,15 +950,15 @@ sdhci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
|
||||
SDHCI_UNLOCK(slot);
|
||||
if (dumping) {
|
||||
while (slot->req != NULL) {
|
||||
sdhci_intr(slot->sc);
|
||||
sdhci_generic_intr(slot);
|
||||
DELAY(10);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_get_ro(device_t brdev, device_t reqdev)
|
||||
int
|
||||
sdhci_generic_get_ro(device_t brdev, device_t reqdev)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(reqdev);
|
||||
uint32_t val;
|
||||
@ -1235,8 +969,8 @@ sdhci_get_ro(device_t brdev, device_t reqdev)
|
||||
return (!(val & SDHCI_WRITE_PROTECT));
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_acquire_host(device_t brdev, device_t reqdev)
|
||||
int
|
||||
sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(reqdev);
|
||||
int err = 0;
|
||||
@ -1251,8 +985,8 @@ sdhci_acquire_host(device_t brdev, device_t reqdev)
|
||||
return (err);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_release_host(device_t brdev, device_t reqdev)
|
||||
int
|
||||
sdhci_generic_release_host(device_t brdev, device_t reqdev)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(reqdev);
|
||||
|
||||
@ -1382,14 +1116,9 @@ sdhci_acmd_irq(struct sdhci_slot *slot)
|
||||
sdhci_reset(slot, SDHCI_RESET_CMD);
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_intr(void *arg)
|
||||
void
|
||||
sdhci_generic_intr(struct sdhci_slot *slot)
|
||||
{
|
||||
struct sdhci_softc *sc = (struct sdhci_softc *)arg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
uint32_t intmask;
|
||||
|
||||
SDHCI_LOCK(slot);
|
||||
@ -1397,7 +1126,7 @@ sdhci_intr(void *arg)
|
||||
intmask = RD4(slot, SDHCI_INT_STATUS);
|
||||
if (intmask == 0 || intmask == 0xffffffff) {
|
||||
SDHCI_UNLOCK(slot);
|
||||
continue;
|
||||
return;
|
||||
}
|
||||
if (sdhci_debug > 2)
|
||||
slot_printf(slot, "Interrupt %#x\n", intmask);
|
||||
@ -1457,10 +1186,9 @@ sdhci_intr(void *arg)
|
||||
|
||||
SDHCI_UNLOCK(slot);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
|
||||
int
|
||||
sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(child);
|
||||
|
||||
@ -1513,8 +1241,8 @@ sdhci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
|
||||
int
|
||||
sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
|
||||
{
|
||||
struct sdhci_slot *slot = device_get_ivars(child);
|
||||
|
||||
@ -1569,34 +1297,4 @@ sdhci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t sdhci_methods[] = {
|
||||
/* device_if */
|
||||
DEVMETHOD(device_probe, sdhci_probe),
|
||||
DEVMETHOD(device_attach, sdhci_attach),
|
||||
DEVMETHOD(device_detach, sdhci_detach),
|
||||
DEVMETHOD(device_suspend, sdhci_suspend),
|
||||
DEVMETHOD(device_resume, sdhci_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, sdhci_read_ivar),
|
||||
DEVMETHOD(bus_write_ivar, sdhci_write_ivar),
|
||||
|
||||
/* mmcbr_if */
|
||||
DEVMETHOD(mmcbr_update_ios, sdhci_update_ios),
|
||||
DEVMETHOD(mmcbr_request, sdhci_request),
|
||||
DEVMETHOD(mmcbr_get_ro, sdhci_get_ro),
|
||||
DEVMETHOD(mmcbr_acquire_host, sdhci_acquire_host),
|
||||
DEVMETHOD(mmcbr_release_host, sdhci_release_host),
|
||||
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static driver_t sdhci_driver = {
|
||||
"sdhci",
|
||||
sdhci_methods,
|
||||
sizeof(struct sdhci_softc),
|
||||
};
|
||||
static devclass_t sdhci_devclass;
|
||||
|
||||
|
||||
DRIVER_MODULE(sdhci, pci, sdhci_driver, sdhci_devclass, 0, 0);
|
||||
MODULE_VERSION(sdhci, 1);
|
||||
|
@ -25,26 +25,33 @@
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* PCI registers
|
||||
*/
|
||||
#ifndef __SDHCI_H__
|
||||
#define __SDHCI_H__
|
||||
|
||||
#define PCI_SDHCI_IFPIO 0x00
|
||||
#define PCI_SDHCI_IFDMA 0x01
|
||||
#define PCI_SDHCI_IFVENDOR 0x02
|
||||
#define DMA_BLOCK_SIZE 4096
|
||||
#define DMA_BOUNDARY 0 /* DMA reload every 4K */
|
||||
|
||||
#define PCI_SLOT_INFO 0x40 /* 8 bits */
|
||||
#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
|
||||
#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
|
||||
/* Controller doesn't honor resets unless we touch the clock register */
|
||||
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
|
||||
/* Controller really supports DMA */
|
||||
#define SDHCI_QUIRK_FORCE_DMA (1<<1)
|
||||
/* Controller has unusable DMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_DMA (1<<2)
|
||||
/* Controller doesn't like to be reset when there is no card inserted. */
|
||||
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
|
||||
/* Controller has flaky internal state so reset it on each ios change */
|
||||
#define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
|
||||
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
|
||||
/* Controller needs to be reset after each request to stay stable */
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
|
||||
/* Controller has an off-by-one issue with timeout value */
|
||||
#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
|
||||
/* Controller has broken read timings */
|
||||
#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
|
||||
/* Controller needs lowered frequency */
|
||||
#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
|
||||
|
||||
/*
|
||||
* RICOH specific PCI registers
|
||||
*/
|
||||
#define SDHC_PCI_MODE_KEY 0xf9
|
||||
#define SDHC_PCI_MODE 0x150
|
||||
#define SDHC_PCI_MODE_SD20 0x10
|
||||
#define SDHC_PCI_BASE_FREQ_KEY 0xfc
|
||||
#define SDHC_PCI_BASE_FREQ 0xe1
|
||||
|
||||
/*
|
||||
* Controller registers
|
||||
@ -197,3 +204,54 @@
|
||||
#define SDHCI_VENDOR_VER_SHIFT 8
|
||||
#define SDHCI_SPEC_VER_MASK 0x00FF
|
||||
#define SDHCI_SPEC_VER_SHIFT 0
|
||||
|
||||
struct sdhci_slot {
|
||||
u_int quirks; /* Chip specific quirks */
|
||||
device_t bus; /* Bus device */
|
||||
device_t dev; /* Slot device */
|
||||
u_char num; /* Slot number */
|
||||
u_char opt; /* Slot options */
|
||||
u_char version;
|
||||
#define SDHCI_HAVE_DMA 1
|
||||
uint32_t max_clk; /* Max possible freq */
|
||||
uint32_t timeout_clk; /* Timeout freq */
|
||||
bus_dma_tag_t dmatag;
|
||||
bus_dmamap_t dmamap;
|
||||
u_char *dmamem;
|
||||
bus_addr_t paddr; /* DMA buffer address */
|
||||
struct task card_task; /* Card presence check task */
|
||||
struct callout card_callout; /* Card insert delay callout */
|
||||
struct mmc_host host; /* Host parameters */
|
||||
struct mmc_request *req; /* Current request */
|
||||
struct mmc_command *curcmd; /* Current command of current request */
|
||||
|
||||
uint32_t intmask; /* Current interrupt mask */
|
||||
uint32_t clock; /* Current clock freq. */
|
||||
size_t offset; /* Data buffer offset */
|
||||
uint8_t hostctrl; /* Current host control register */
|
||||
u_char power; /* Current power */
|
||||
u_char bus_busy; /* Bus busy status */
|
||||
u_char cmd_done; /* CMD command part done flag */
|
||||
u_char data_done; /* DAT command part done flag */
|
||||
u_char flags; /* Request execution flags */
|
||||
#define CMD_STARTED 1
|
||||
#define STOP_STARTED 2
|
||||
#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
|
||||
struct mtx mtx; /* Slot mutex */
|
||||
};
|
||||
|
||||
int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result);
|
||||
int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value);
|
||||
int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num);
|
||||
void sdhci_start_slot(struct sdhci_slot *slot);
|
||||
int sdhci_cleanup_slot(struct sdhci_slot *slot);
|
||||
int sdhci_generic_suspend(struct sdhci_slot *slot);
|
||||
int sdhci_generic_resume(struct sdhci_slot *slot);
|
||||
int sdhci_generic_update_ios(device_t brdev, device_t reqdev);
|
||||
int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req);
|
||||
int sdhci_generic_get_ro(device_t brdev, device_t reqdev);
|
||||
int sdhci_generic_acquire_host(device_t brdev, device_t reqdev);
|
||||
int sdhci_generic_release_host(device_t brdev, device_t reqdev);
|
||||
void sdhci_generic_intr(struct sdhci_slot *slot);
|
||||
|
||||
#endif /* __SDHCI_H__ */
|
||||
|
121
sys/dev/sdhci/sdhci_if.m
Normal file
121
sys/dev/sdhci/sdhci_if.m
Normal file
@ -0,0 +1,121 @@
|
||||
#-
|
||||
# Copyright (c) 2006 M. Warner Losh
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
# SUCH DAMAGE.
|
||||
#
|
||||
# Portions of this software may have been developed with reference to
|
||||
# the SD Simplified Specification. The following disclaimer may apply:
|
||||
#
|
||||
# The following conditions apply to the release of the simplified
|
||||
# specification ("Simplified Specification") by the SD Card Association and
|
||||
# the SD Group. The Simplified Specification is a subset of the complete SD
|
||||
# Specification which is owned by the SD Card Association and the SD
|
||||
# Group. This Simplified Specification is provided on a non-confidential
|
||||
# basis subject to the disclaimers below. Any implementation of the
|
||||
# Simplified Specification may require a license from the SD Card
|
||||
# Association, SD Group, SD-3C LLC or other third parties.
|
||||
#
|
||||
# Disclaimers:
|
||||
#
|
||||
# The information contained in the Simplified Specification is presented only
|
||||
# as a standard specification for SD Cards and SD Host/Ancillary products and
|
||||
# is provided "AS-IS" without any representations or warranties of any
|
||||
# kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
|
||||
# Card Association for any damages, any infringements of patents or other
|
||||
# right of the SD Group, SD-3C LLC, the SD Card Association or any third
|
||||
# parties, which may result from its use. No license is granted by
|
||||
# implication, estoppel or otherwise under any patent or other rights of the
|
||||
# SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
|
||||
# herein shall be construed as an obligation by the SD Group, the SD-3C LLC
|
||||
# or the SD Card Association to disclose or distribute any technical
|
||||
# information, know-how or other confidential information to any third party.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
#
|
||||
# This is the set of callbacks that mmc bridges call into the bus, or
|
||||
# that mmc/sd card drivers call to make requests.
|
||||
#
|
||||
|
||||
#include <machine/bus.h>
|
||||
CODE {
|
||||
struct sdhci_slot;
|
||||
}
|
||||
|
||||
INTERFACE sdhci;
|
||||
|
||||
METHOD uint8_t read_1 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
}
|
||||
|
||||
METHOD uint16_t read_2 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
}
|
||||
|
||||
METHOD uint32_t read_4 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
}
|
||||
|
||||
METHOD void read_multi_4 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
uint32_t *data;
|
||||
bus_size_t count;
|
||||
}
|
||||
|
||||
METHOD void write_1 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
uint8_t val;
|
||||
}
|
||||
|
||||
METHOD void write_2 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
uint16_t val;
|
||||
}
|
||||
|
||||
METHOD void write_4 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
uint32_t val;
|
||||
}
|
||||
|
||||
METHOD void write_multi_4 {
|
||||
device_t brdev;
|
||||
struct sdhci_slot *slot;
|
||||
bus_size_t off;
|
||||
uint32_t *data;
|
||||
bus_size_t count;
|
||||
}
|
440
sys/dev/sdhci/sdhci_pci.c
Normal file
440
sys/dev/sdhci/sdhci_pci.c
Normal file
@ -0,0 +1,440 @@
|
||||
/*-
|
||||
* Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/conf.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/resource.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/sysctl.h>
|
||||
#include <sys/taskqueue.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <machine/stdarg.h>
|
||||
|
||||
#include <dev/mmc/bridge.h>
|
||||
#include <dev/mmc/mmcreg.h>
|
||||
#include <dev/mmc/mmcbrvar.h>
|
||||
|
||||
#include "sdhci.h"
|
||||
#include "mmcbr_if.h"
|
||||
#include "sdhci_if.h"
|
||||
|
||||
/*
|
||||
* PCI registers
|
||||
*/
|
||||
|
||||
#define PCI_SDHCI_IFPIO 0x00
|
||||
#define PCI_SDHCI_IFDMA 0x01
|
||||
#define PCI_SDHCI_IFVENDOR 0x02
|
||||
|
||||
#define PCI_SLOT_INFO 0x40 /* 8 bits */
|
||||
#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
|
||||
#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
|
||||
|
||||
/*
|
||||
* RICOH specific PCI registers
|
||||
*/
|
||||
#define SDHC_PCI_MODE_KEY 0xf9
|
||||
#define SDHC_PCI_MODE 0x150
|
||||
#define SDHC_PCI_MODE_SD20 0x10
|
||||
#define SDHC_PCI_BASE_FREQ_KEY 0xfc
|
||||
#define SDHC_PCI_BASE_FREQ 0xe1
|
||||
|
||||
static const struct sdhci_device {
|
||||
uint32_t model;
|
||||
uint16_t subvendor;
|
||||
char *desc;
|
||||
u_int quirks;
|
||||
} sdhci_devices[] = {
|
||||
{ 0x08221180, 0xffff, "RICOH R5C822 SD",
|
||||
SDHCI_QUIRK_FORCE_DMA },
|
||||
{ 0xe8221180, 0xffff, "RICOH SD",
|
||||
SDHCI_QUIRK_FORCE_DMA },
|
||||
{ 0xe8231180, 0xffff, "RICOH R5CE823 SD",
|
||||
SDHCI_QUIRK_LOWER_FREQUENCY },
|
||||
{ 0x8034104c, 0xffff, "TI XX21/XX11 SD",
|
||||
SDHCI_QUIRK_FORCE_DMA },
|
||||
{ 0x05501524, 0xffff, "ENE CB712 SD",
|
||||
SDHCI_QUIRK_BROKEN_TIMINGS },
|
||||
{ 0x05511524, 0xffff, "ENE CB712 SD 2",
|
||||
SDHCI_QUIRK_BROKEN_TIMINGS },
|
||||
{ 0x07501524, 0xffff, "ENE CB714 SD",
|
||||
SDHCI_QUIRK_RESET_ON_IOS |
|
||||
SDHCI_QUIRK_BROKEN_TIMINGS },
|
||||
{ 0x07511524, 0xffff, "ENE CB714 SD 2",
|
||||
SDHCI_QUIRK_RESET_ON_IOS |
|
||||
SDHCI_QUIRK_BROKEN_TIMINGS },
|
||||
{ 0x410111ab, 0xffff, "Marvell CaFe SD",
|
||||
SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
|
||||
{ 0x2381197B, 0xffff, "JMicron JMB38X SD",
|
||||
SDHCI_QUIRK_32BIT_DMA_SIZE |
|
||||
SDHCI_QUIRK_RESET_AFTER_REQUEST },
|
||||
{ 0, 0xffff, NULL,
|
||||
0 }
|
||||
};
|
||||
|
||||
struct sdhci_pci_softc {
|
||||
device_t dev; /* Controller device */
|
||||
u_int quirks; /* Chip specific quirks */
|
||||
struct resource *irq_res; /* IRQ resource */
|
||||
int irq_rid;
|
||||
void *intrhand; /* Interrupt handle */
|
||||
|
||||
int num_slots; /* Number of slots on this controller */
|
||||
struct sdhci_slot slots[6];
|
||||
struct resource *mem_res[6]; /* Memory resource */
|
||||
int mem_rid[6];
|
||||
};
|
||||
|
||||
static SYSCTL_NODE(_hw, OID_AUTO, sdhci_pci, CTLFLAG_RD, 0, "sdhci PCI driver");
|
||||
|
||||
int sdhci_pci_debug;
|
||||
TUNABLE_INT("hw.sdhci_pci.debug", &sdhci_pci_debug);
|
||||
SYSCTL_INT(_hw_sdhci_pci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_pci_debug, 0, "Debug level");
|
||||
|
||||
static uint8_t
|
||||
sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
|
||||
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
||||
return bus_read_1(sc->mem_res[slot->num], off);
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
|
||||
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
||||
bus_write_1(sc->mem_res[slot->num], off, val);
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
|
||||
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
||||
return bus_read_2(sc->mem_res[slot->num], off);
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
|
||||
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
||||
bus_write_2(sc->mem_res[slot->num], off, val);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
|
||||
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
||||
return bus_read_4(sc->mem_res[slot->num], off);
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
|
||||
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
||||
bus_write_4(sc->mem_res[slot->num], off, val);
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot,
|
||||
bus_size_t off, uint32_t *data, bus_size_t count)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot,
|
||||
bus_size_t off, uint32_t *data, bus_size_t count)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
|
||||
}
|
||||
|
||||
static void sdhci_pci_intr(void *arg);
|
||||
|
||||
static void
|
||||
sdhci_lower_frequency(device_t dev)
|
||||
{
|
||||
|
||||
/* Enable SD2.0 mode. */
|
||||
pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
|
||||
pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
|
||||
pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
|
||||
|
||||
/*
|
||||
* Some SD/MMC cards don't work with the default base
|
||||
* clock frequency of 200MHz. Lower it to 50Hz.
|
||||
*/
|
||||
pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
|
||||
pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
|
||||
pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_pci_probe(device_t dev)
|
||||
{
|
||||
uint32_t model;
|
||||
uint16_t subvendor;
|
||||
uint8_t class, subclass;
|
||||
int i, result;
|
||||
|
||||
model = (uint32_t)pci_get_device(dev) << 16;
|
||||
model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
|
||||
subvendor = pci_get_subvendor(dev);
|
||||
class = pci_get_class(dev);
|
||||
subclass = pci_get_subclass(dev);
|
||||
|
||||
result = ENXIO;
|
||||
for (i = 0; sdhci_devices[i].model != 0; i++) {
|
||||
if (sdhci_devices[i].model == model &&
|
||||
(sdhci_devices[i].subvendor == 0xffff ||
|
||||
sdhci_devices[i].subvendor == subvendor)) {
|
||||
device_set_desc(dev, sdhci_devices[i].desc);
|
||||
result = BUS_PROBE_DEFAULT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (result == ENXIO && class == PCIC_BASEPERIPH &&
|
||||
subclass == PCIS_BASEPERIPH_SDHC) {
|
||||
device_set_desc(dev, "Generic SD HCI");
|
||||
result = BUS_PROBE_GENERIC;
|
||||
}
|
||||
|
||||
return (result);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_pci_attach(device_t dev)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
uint32_t model;
|
||||
uint16_t subvendor;
|
||||
uint8_t class, subclass, progif;
|
||||
int err, slots, bar, i;
|
||||
|
||||
sc->dev = dev;
|
||||
model = (uint32_t)pci_get_device(dev) << 16;
|
||||
model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
|
||||
subvendor = pci_get_subvendor(dev);
|
||||
class = pci_get_class(dev);
|
||||
subclass = pci_get_subclass(dev);
|
||||
progif = pci_get_progif(dev);
|
||||
/* Apply chip specific quirks. */
|
||||
for (i = 0; sdhci_devices[i].model != 0; i++) {
|
||||
if (sdhci_devices[i].model == model &&
|
||||
(sdhci_devices[i].subvendor == 0xffff ||
|
||||
sdhci_devices[i].subvendor == subvendor)) {
|
||||
sc->quirks = sdhci_devices[i].quirks;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Some controllers need to be bumped into the right mode. */
|
||||
if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
|
||||
sdhci_lower_frequency(dev);
|
||||
/* Read slots info from PCI registers. */
|
||||
slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
|
||||
bar = PCI_SLOT_INFO_FIRST_BAR(slots);
|
||||
slots = PCI_SLOT_INFO_SLOTS(slots);
|
||||
if (slots > 6 || bar > 5) {
|
||||
device_printf(dev, "Incorrect slots information (%d, %d).\n",
|
||||
slots, bar);
|
||||
return (EINVAL);
|
||||
}
|
||||
/* Allocate IRQ. */
|
||||
sc->irq_rid = 0;
|
||||
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
|
||||
RF_SHAREABLE | RF_ACTIVE);
|
||||
if (sc->irq_res == NULL) {
|
||||
device_printf(dev, "Can't allocate IRQ\n");
|
||||
return (ENOMEM);
|
||||
}
|
||||
/* Scan all slots. */
|
||||
for (i = 0; i < slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[sc->num_slots];
|
||||
|
||||
/* Allocate memory. */
|
||||
sc->mem_rid[i] = PCIR_BAR(bar + i);
|
||||
sc->mem_res[i] = bus_alloc_resource(dev,
|
||||
SYS_RES_MEMORY, &(sc->mem_rid[i]), 0ul, ~0ul, 0x100, RF_ACTIVE);
|
||||
if (sc->mem_res[i] == NULL) {
|
||||
device_printf(dev, "Can't allocate memory for slot %d\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (sdhci_init_slot(dev, slot, i) != 0)
|
||||
continue;
|
||||
|
||||
|
||||
sc->num_slots++;
|
||||
}
|
||||
device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
|
||||
/* Activate the interrupt */
|
||||
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
||||
NULL, sdhci_pci_intr, sc, &sc->intrhand);
|
||||
if (err)
|
||||
device_printf(dev, "Can't setup IRQ\n");
|
||||
pci_enable_busmaster(dev);
|
||||
/* Process cards detection. */
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
|
||||
sdhci_start_slot(slot);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_pci_detach(device_t dev)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
int i;
|
||||
|
||||
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
||||
bus_release_resource(dev, SYS_RES_IRQ,
|
||||
sc->irq_rid, sc->irq_res);
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
|
||||
sdhci_cleanup_slot(slot);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
sc->mem_rid[i], sc->mem_res[i]);
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_pci_suspend(device_t dev)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
int i, err;
|
||||
|
||||
err = bus_generic_suspend(dev);
|
||||
if (err)
|
||||
return (err);
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_generic_suspend(&sc->slots[i]);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sdhci_pci_resume(device_t dev)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_generic_resume(&sc->slots[i]);
|
||||
return (bus_generic_resume(dev));
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
sdhci_pci_intr(void *arg)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
sdhci_generic_intr(slot);
|
||||
}
|
||||
}
|
||||
|
||||
static device_method_t sdhci_methods[] = {
|
||||
/* device_if */
|
||||
DEVMETHOD(device_probe, sdhci_pci_probe),
|
||||
DEVMETHOD(device_attach, sdhci_pci_attach),
|
||||
DEVMETHOD(device_detach, sdhci_pci_detach),
|
||||
DEVMETHOD(device_suspend, sdhci_pci_suspend),
|
||||
DEVMETHOD(device_resume, sdhci_pci_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
||||
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
||||
|
||||
/* mmcbr_if */
|
||||
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
||||
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
||||
DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
|
||||
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
||||
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
||||
|
||||
/* SDHCI registers accessors */
|
||||
DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
|
||||
DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
|
||||
DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
|
||||
DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
|
||||
DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
|
||||
DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
|
||||
DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
|
||||
DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
|
||||
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static driver_t sdhci_pci_driver = {
|
||||
"sdhci_pci",
|
||||
sdhci_methods,
|
||||
sizeof(struct sdhci_pci_softc),
|
||||
};
|
||||
static devclass_t sdhci_pci_devclass;
|
||||
|
||||
DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, 0, 0);
|
||||
MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
|
@ -290,6 +290,7 @@ SUBDIR= \
|
||||
scd \
|
||||
${_scsi_low} \
|
||||
sdhci \
|
||||
sdhci_pci \
|
||||
sem \
|
||||
send \
|
||||
${_sf} \
|
||||
|
@ -3,6 +3,6 @@
|
||||
.PATH: ${.CURDIR}/../../dev/sdhci
|
||||
|
||||
KMOD= sdhci
|
||||
SRCS= sdhci.c sdhci.h device_if.h bus_if.h pci_if.h mmcbr_if.h
|
||||
SRCS= sdhci.c sdhci.h sdhci_if.c sdhci_if.h device_if.h bus_if.h mmcbr_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
8
sys/modules/sdhci_pci/Makefile
Normal file
8
sys/modules/sdhci_pci/Makefile
Normal file
@ -0,0 +1,8 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/sdhci
|
||||
|
||||
KMOD= sdhci_pci
|
||||
SRCS= sdhci_pci.c sdhci.h sdhci_if.h device_if.h bus_if.h pci_if.h mmcbr_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
Loading…
x
Reference in New Issue
Block a user