Bring overhauled nfe(4) into tree.
o s/printf/device_printf/g o Nuke OpenBSDism. o Nuke NetBSD/OpenBSD specific DMA sync operations.(we don't have a way to sync a single descriptor within a DMA map.) o Remove recursive mutex. o bus_dma(9) clean up. o 40bit DMA address support. o Add protection for Rx map load failure. o Fix a long standing bug for watchdog timeout. [1] o Add additional protections, missing Tx completion interrupt, losing start Tx command, for watchdog timeout. o Switch to taskqueue(9) API to handle interrupts. o Use our own timer for watchdog instead of if_watchdog/if_timer interface. o Advertise VLAN header length/capability correctly to upper layer. o Remove excessive kernel stack consumption in nfe_encap(). o Handle highly fragmented mbuf chains correctly. o Enable etherenet address reprogramming with ifconfig(8). o Add ALTQ/TSO, MSI/MSIX support. o Increased Rx ring to 256 descriptors from 128. o Align Tx/Rx descriptor ring on sizeof(struct nfe_desc64) boundary. o Remove alignment restrictions on Tx/Rx buffers. o Rewritten jumbo frame support code. o Add support for hardware assistend VLAN tag insertion/stripping. o Add support for Tx/Rx flow control based on patches from Peer Chen. [2] o Add a routine that detects whether ethernet address swap routines is required. [3] o Add a workaround that take MAC/PHY out of power down mode. o Add suspend/resume support. o style(9) and code clean up. Special thanks to Shigeaki Tagashira, the original porter of nfe(4), who submitted lots of patches, performed uncountable number of regression tests and maintained nfe(4) for a long time. Without his enthusiastic help and support I could never have completed this overhauling task. The only weak point of nfe(4) compared to nve(4) is instability of manual half-duplex media selection on certain hardwares(auto sensing media type should work for all cases, though). This was a long standing bug of nfe(4) and I still have no idea why it doesn't work on some hardwares. Obtained from: OpenBSD [1] Submitted by: Peer Chen < pchen at nvidia dot com > [2], [3] Reviewed by: Shigeaki Tagashira < shigeaki AT se DOT hiroshima-u DOT ac DOT jp > Tested by: Shigeaki Tagashira, current Discussed with: current Silence from: obrien
This commit is contained in:
yongari
parent
ec6a039b62
commit
36a63ea429
2872
sys/dev/nfe/if_nfe.c
2872
sys/dev/nfe/if_nfe.c
File diff suppressed because it is too large
Load Diff
@ -18,26 +18,47 @@
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* $FreeBSD$
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*/
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#define NFE_PCI_BA 0x10
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#define NFE_RX_RING_COUNT 128
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#define NFE_RX_RING_COUNT 256
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#define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT
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#define NFE_TX_RING_COUNT 256
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#define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4)
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#define NFE_PROC_MIN 50
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#define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1)
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#define NFE_INC(x, y) (x) = ((x) + 1) % y
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/* RX/TX MAC addr + type + VLAN + align + slack */
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#define NFE_RX_HEADERS 64
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/* Maximum MTU size. */
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#define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */
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#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */
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#define NFE_JBYTES (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN)
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#define NFE_JPOOL_COUNT (NFE_RX_RING_COUNT + NFE_RX_HEADERS)
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#define NFE_MAX_SCATTER (NFE_TX_RING_COUNT - 2)
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#define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2
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#define NFE_JUMBO_MTU \
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(NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS)
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#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
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#define NFE_JSLOTS ((NFE_JUMBO_RX_RING_COUNT * 3) / 2)
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#define NFE_JRAWLEN (NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
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#define NFE_JLEN \
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(NFE_JRAWLEN + (sizeof(uint64_t) - (NFE_JRAWLEN % sizeof(uint64_t))))
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#define NFE_JPAGESZ PAGE_SIZE
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#define NFE_RESID \
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(NFE_JPAGESZ - (NFE_JLEN * NFE_JSLOTS) % NFE_JPAGESZ)
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#define NFE_JMEM ((NFE_JLEN * NFE_JSLOTS) + NFE_RESID)
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#define NFE_MAX_SCATTER 32
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#define NFE_IRQ_STATUS 0x000
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#define NFE_IRQ_MASK 0x004
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#define NFE_SETUP_R6 0x008
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#define NFE_IMTIMER 0x00c
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#define NFE_MSI_MAP0 0x020
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#define NFE_MSI_MAP1 0x024
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#define NFE_MSI_IRQ_MASK 0x030
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#define NFE_MAC_RESET 0x03c
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#define NFE_MISC1 0x080
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#define NFE_TX_CTL 0x084
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#define NFE_TX_STATUS 0x088
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@ -66,6 +87,7 @@
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#define NFE_RXTX_CTL 0x144
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#define NFE_TX_RING_ADDR_HI 0x148
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#define NFE_RX_RING_ADDR_HI 0x14c
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#define NFE_TX_PAUSE_FRAME 0x170
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#define NFE_PHY_STATUS 0x180
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#define NFE_SETUP_R4 0x184
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#define NFE_STATUS 0x188
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@ -78,6 +100,14 @@
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#define NFE_PWR_CAP 0x268
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#define NFE_PWR_STATE 0x26c
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#define NFE_VTAG_CTL 0x300
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#define NFE_MSIX_MAP0 0x3e0
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#define NFE_MSIX_MAP1 0x3e4
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#define NFE_MSIX_IRQ_STATUS 0x3f0
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#define NFE_PWR2_CTL 0x600
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#define NFE_MAC_RESET_MAGIC 0x00f3
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#define NFE_MAC_ADDR_INORDER 0x8000
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#define NFE_PHY_ERROR 0x00001
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#define NFE_PHY_WRITE 0x00400
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@ -86,7 +116,9 @@
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#define NFE_STATUS_MAGIC 0x140000
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#define NFE_R1_MAGIC 0x16070f
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#define NFE_R1_MAGIC_1000 0x14050f
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#define NFE_R1_MAGIC_10_100 0x16070f
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#define NFE_R1_MAGIC_DEFAULT 0x15050f
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#define NFE_R2_MAGIC 0x16
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#define NFE_R4_MAGIC 0x08
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#define NFE_R6_MAGIC 0x03
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@ -118,9 +150,11 @@
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#define NFE_RXTX_RXCSUM 0x0400
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#define NFE_RXTX_V2MAGIC 0x2100
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#define NFE_RXTX_V3MAGIC 0x2200
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#define NFE_RXFILTER_MAGIC 0x007f0008
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#define NFE_U2M (1 << 5)
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#define NFE_PROMISC (1 << 7)
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#define NFE_RXFILTER_MAGIC 0x007f0000
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#define NFE_PFF_RX_PAUSE (1 << 3)
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#define NFE_PFF_LOOPBACK (1 << 4)
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#define NFE_PFF_U2M (1 << 5)
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#define NFE_PFF_PROMISC (1 << 7)
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#define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
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/* default interrupt moderation timer of 128us */
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@ -131,6 +165,9 @@
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#define NFE_PWR_VALID (1 << 8)
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#define NFE_PWR_WAKEUP (1 << 15)
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#define NFE_PWR2_WAKEUP_MASK 0x0f11
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#define NFE_PWR2_REVA3 (1 << 0)
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#define NFE_MEDIA_SET 0x10000
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#define NFE_MEDIA_1000T 0x00032
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#define NFE_MEDIA_100TX 0x00064
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@ -141,13 +178,32 @@
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#define NFE_PHY_HDX (1 << 8)
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#define NFE_MISC1_MAGIC 0x003b0f3c
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#define NFE_MISC1_TX_PAUSE (1 << 0)
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#define NFE_MISC1_HDX (1 << 1)
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#define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080
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#define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030
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#define NFE_SEED_MASK 0x0003ff00
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#define NFE_SEED_10T 0x00007f00
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#define NFE_SEED_100TX 0x00002d00
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#define NFE_SEED_1000T 0x00007400
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#define NFE_MSI_MESSAGES 8
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#define NFE_MSI_VECTOR_0_ENABLED 0x01
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/*
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* It seems that nForce supports only the lower 40 bits of a DMA address.
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*/
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#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
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#define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR
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#else
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#define NFE_DMA_MAXADDR 0xFFFFFFFFFF
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#endif
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#define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
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#define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32)
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/* Rx/Tx descriptor */
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struct nfe_desc32 {
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uint32_t physaddr;
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@ -179,9 +235,6 @@ struct nfe_desc64 {
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#define NFE_RX_VALID_V2 (1 << 13)
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#define NFE_TX_ERROR_V2 0x5c04
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#define NFE_TX_LASTFRAG_V2 (1 << 13)
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#define NFE_RX_IP_CSUMOK_V2 0x1000
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#define NFE_RX_UDP_CSUMOK_V2 0x1400
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#define NFE_RX_TCP_CSUMOK_V2 0x1800
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#define NFE_RX_ERROR1_V2 (1<<2)
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#define NFE_RX_ERROR2_V2 (1<<3)
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#define NFE_RX_ERROR3_V2 (1<<4)
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@ -191,19 +244,28 @@ struct nfe_desc64 {
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#define NFE_V2_TXERR "\020" \
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"\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
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#define NFE_RING_ALIGN (sizeof(struct nfe_desc64))
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/* flags common to V1/V2 descriptors */
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#define NFE_RX_CSUMOK 0x1c00
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#define NFE_RX_UDP_CSUMOK (1 << 10)
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#define NFE_RX_TCP_CSUMOK (1 << 11)
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#define NFE_RX_IP_CSUMOK (1 << 12)
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#define NFE_RX_ERROR (1 << 14)
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#define NFE_RX_READY (1 << 15)
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#define NFE_TX_TCP_CSUM (1 << 10)
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#define NFE_RX_LEN_MASK 0x3fff
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#define NFE_TX_TCP_UDP_CSUM (1 << 10)
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#define NFE_TX_IP_CSUM (1 << 11)
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#define NFE_TX_TSO (1 << 12)
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#define NFE_TX_TSO_SHIFT 14
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#define NFE_TX_VALID (1 << 15)
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#define NFE_READ(sc, reg) \
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bus_space_read_4((sc)->nfe_memt, (sc)->nfe_memh, (reg))
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bus_read_4((sc)->nfe_res[0], (reg))
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#define NFE_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->nfe_memt, (sc)->nfe_memh, (reg), (val))
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bus_write_4((sc)->nfe_res[0], (reg), (val))
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#define NFE_TIMEOUT 1000
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#ifndef PCI_VENDOR_NVIDIA
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#define PCI_VENDOR_NVIDIA 0x10DE
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@ -232,6 +294,10 @@ struct nfe_desc64 {
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452
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#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e
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#define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1
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#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2
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@ -18,110 +18,120 @@
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* $FreeBSD$
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*/
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#define NFE_IFQ_MAXLEN 64
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struct nfe_tx_data {
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bus_dmamap_t tx_data_map;
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bus_dmamap_t active;
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int nsegs;
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struct mbuf *m;
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};
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struct nfe_tx_ring {
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bus_dma_tag_t tx_desc_tag;
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bus_dmamap_t tx_desc_map;
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bus_dma_segment_t tx_desc_segs;
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bus_addr_t physaddr;
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struct nfe_desc32 *desc32;
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struct nfe_desc64 *desc64;
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bus_dma_tag_t tx_data_tag;
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struct nfe_tx_data data[NFE_TX_RING_COUNT];
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int queued;
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int cur;
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int next;
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bus_addr_t tx_desc_addr;
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bus_addr_t tx_data_addr;
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bus_dma_tag_t tx_desc_tag;
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bus_dma_tag_t tx_data_tag;
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};
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struct nfe_jbuf {
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caddr_t buf;
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bus_addr_t physaddr;
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SLIST_ENTRY(nfe_jbuf) jnext;
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struct nfe_jpool_entry {
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int slot;
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SLIST_ENTRY(nfe_jpool_entry) jpool_entries;
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};
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struct nfe_rx_data {
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bus_dmamap_t rx_data_map;
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bus_dma_tag_t rx_data_tag;
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bus_addr_t rx_data_addr;
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bus_dma_segment_t rx_data_segs;
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bus_addr_t paddr;
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struct mbuf *m;
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};
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struct nfe_rx_ring {
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bus_dma_tag_t rx_desc_tag;
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bus_dmamap_t rx_desc_map;
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bus_dma_segment_t rx_desc_segs;
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bus_dma_tag_t rx_desc_tag;
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bus_addr_t rx_desc_addr;
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#ifndef JMBUF
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bus_dmamap_t rx_jumbo_map;
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bus_dma_segment_t rx_jumbo_segs;
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bus_dma_tag_t rx_jumbo_tag;
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bus_addr_t rx_jumbo_addr;
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caddr_t jpool;
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struct nfe_jbuf jbuf[NFE_JPOOL_COUNT];
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SLIST_HEAD(, nfe_jbuf) jfreelist;
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#endif
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bus_addr_t physaddr;
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struct nfe_desc32 *desc32;
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struct nfe_desc64 *desc64;
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bus_dma_tag_t rx_data_tag;
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bus_dmamap_t rx_spare_map;
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struct nfe_rx_data data[NFE_RX_RING_COUNT];
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int bufsz;
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int cur;
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int next;
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};
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struct nfe_jrx_ring {
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bus_dma_tag_t jrx_desc_tag;
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bus_dmamap_t jrx_desc_map;
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bus_dma_tag_t jrx_jumbo_tag;
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bus_dmamap_t jrx_jumbo_map;
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void *jpool;
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caddr_t jslots[NFE_JSLOTS];
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bus_addr_t jphysaddr;
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struct nfe_desc32 *jdesc32;
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struct nfe_desc64 *jdesc64;
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bus_dma_tag_t jrx_data_tag;
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bus_dmamap_t jrx_spare_map;
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struct nfe_rx_data jdata[NFE_JUMBO_RX_RING_COUNT];
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int jcur;
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int jnext;
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};
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struct nfe_softc {
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struct ifnet *nfe_ifp;
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device_t nfe_dev;
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uint16_t nfe_devid;
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uint16_t nfe_revid;
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device_t nfe_miibus;
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struct mtx nfe_mtx;
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bus_space_handle_t nfe_memh;
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bus_space_tag_t nfe_memt;
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struct resource *nfe_res;
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struct resource *nfe_irq;
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void *nfe_intrhand;
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struct mii_data nfe_mii;
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u_int8_t nfe_unit;
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struct resource *nfe_res[1];
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struct resource *nfe_msix_res;
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struct resource *nfe_msix_pba_res;
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struct resource *nfe_irq[NFE_MSI_MESSAGES];
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void *nfe_intrhand[NFE_MSI_MESSAGES];
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struct callout nfe_stat_ch;
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int nfe_watchdog_timer;
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struct arpcom nfe_arpcom;
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bus_dma_tag_t nfe_parent_tag;
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/* struct timeout nfe_tick_ch; */
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void *nfe_powerhook;
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int nfe_if_flags;
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u_int nfe_flags;
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#define NFE_JUMBO_SUP 0x01
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#define NFE_40BIT_ADDR 0x02
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#define NFE_HW_CSUM 0x04
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#define NFE_HW_VLAN 0x08
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u_int32_t rxtxctl;
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u_int32_t nfe_mtu;
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u_int8_t mii_phyaddr;
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u_char eaddr[ETHER_ADDR_LEN];
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struct task nfe_txtask;
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uint32_t nfe_flags;
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#define NFE_JUMBO_SUP 0x0001
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#define NFE_40BIT_ADDR 0x0002
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#define NFE_HW_CSUM 0x0004
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#define NFE_HW_VLAN 0x0008
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#define NFE_PWR_MGMT 0x0010
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#define NFE_CORRECT_MACADDR 0x0020
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#define NFE_TX_FLOW_CTRL 0x0040
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uint32_t rxtxctl;
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uint8_t mii_phyaddr;
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uint8_t eaddr[ETHER_ADDR_LEN];
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struct taskqueue *nfe_tq;
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struct task nfe_int_task;
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struct task nfe_tx_task;
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struct task nfe_link_task;
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int nfe_link;
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int nfe_suspended;
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int nfe_framesize;
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int nfe_process_limit;
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int nfe_force_tx;
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uint32_t nfe_irq_status;
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uint32_t nfe_irq_mask;
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uint32_t nfe_intrs;
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uint32_t nfe_nointrs;
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uint32_t nfe_msi;
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uint32_t nfe_msix;
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struct nfe_tx_ring txq;
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struct nfe_rx_ring rxq;
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#ifdef DEVICE_POLLING
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int rxcycles;
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#endif
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struct nfe_jrx_ring jrxq;
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SLIST_HEAD(__nfe_jfreehead, nfe_jpool_entry) nfe_jfree_listhead;
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SLIST_HEAD(__nfe_jinusehead, nfe_jpool_entry) nfe_jinuse_listhead;
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struct mtx nfe_jlist_mtx;
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};
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struct nfe_type {
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u_int16_t vid_id;
|
||||
u_int16_t dev_id;
|
||||
uint16_t vid_id;
|
||||
uint16_t dev_id;
|
||||
char *name;
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user