Enable arm,io-coherent property of PL310 L2 cache on Armada 38x platforms

This patch disables outer cache sync in PL310 driver
by adding "arm,io-coherent" property. In addition to
the previous patches it was the last bit needed
for enabling proper operation of Armada 38x SoCs
with the IO cache coherency.

Submitted by: Michal Mazur <mkm@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: mmel
Differential revision: https://reviews.freebsd.org/D11204

sys/boot/fdt/dts/arm/armada-38x.dtsi

@@ -177,6 +177,7 @@
 				reg = <0x8000 0x1000>;
 				cache-unified;
 				cache-level = <2>;
+				arm,io-coherent;
 			};
 
 			scu@c000 {