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Enable arm,io-coherent property of PL310 L2 cache on Armada 38x platforms

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This patch disables outer cache sync in PL310 driver
by adding "arm,io-coherent" property. In addition to
the previous patches it was the last bit needed
for enabling proper operation of Armada 38x SoCs
with the IO cache coherency.

Submitted by: Michal Mazur <mkm@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: mmel
Differential revision: https://reviews.freebsd.org/D11204
This commit is contained in:
Zbigniew Bodek 2017-06-21 18:28:37 +00:00
parent 3361fdc431
commit 3706b98788
1 changed files with 1 additions and 0 deletions
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sys/boot/fdt/dts/arm/armada-38x.dtsi
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@ -177,6 +177,7 @@
reg = <0x8000 0x1000>; reg = <0x8000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
arm,io-coherent;
}; };
scu@c000 { scu@c000 {