drm: Import drm_dp_helper.c from Linux 3.8-rc3
While here, update drm_dp_helper.h to better match Linux one.
This commit is contained in:
dumbbell
parent
dc23a4a559
commit
37cc370860
@ -317,6 +317,9 @@ typedef int8_t s8;
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#define DRM_HZ hz
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#define DRM_UDELAY(udelay) DELAY(udelay)
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#define DRM_MDELAY(msecs) do { int loops = (msecs); \
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while (loops--) DELAY(1000); \
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} while (0)
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#define DRM_TIME_SLICE (hz/20) /* Time slice for GLXContexts */
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#define DRM_GET_PRIV_SAREA(_dev, _ctx, _map) do { \
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147
sys/dev/drm2/drm_dp_helper.c
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147
sys/dev/drm2/drm_dp_helper.c
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@ -0,0 +1,147 @@
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/*
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* Copyright © 2009 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <dev/drm2/drmP.h>
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#include <dev/drm2/drm_dp_helper.h>
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/**
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* DOC: dp helpers
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*
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* These functions contain some common logic and helpers at various abstraction
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* levels to deal with Display Port sink devices and related things like DP aux
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* channel transfers, EDID reading over DP aux channels, decoding certain DPCD
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* blocks, ...
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*/
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static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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DRM_UDELAY(100);
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else
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DRM_MDELAY(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
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}
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
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if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
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DRM_UDELAY(400);
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else
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DRM_MDELAY(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
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}
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u8 drm_dp_link_rate_to_bw_code(int link_rate)
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{
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switch (link_rate) {
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case 162000:
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default:
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return DP_LINK_BW_1_62;
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case 270000:
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return DP_LINK_BW_2_7;
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case 540000:
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return DP_LINK_BW_5_4;
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}
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}
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int drm_dp_bw_code_to_link_rate(u8 link_bw)
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{
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switch (link_bw) {
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case DP_LINK_BW_1_62:
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default:
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return 162000;
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case DP_LINK_BW_2_7:
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return 270000;
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case DP_LINK_BW_5_4:
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return 540000;
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}
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}
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@ -25,7 +25,19 @@
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#ifndef _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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/* From the VESA DisplayPort spec */
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/*
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* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
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* DP and DPCD versions are independent. Differences from 1.0 are not noted,
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* 1.0 devices basically don't exist in the wild.
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*
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* Abbreviations, in chronological order:
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*
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* eDP: Embedded DisplayPort version 1
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* DPI: DisplayPort Interoperability Guideline v1.1a
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* 1.2: DisplayPort 1.2
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*
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* 1.2 formally includes both eDP and DPI definitions.
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*/
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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@ -52,7 +64,7 @@
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6)
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# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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@ -68,14 +80,33 @@
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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#define DP_DOWN_STREAM_PORT_COUNT 0x007
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# define DP_PORT_COUNT_MASK 0x0f
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# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
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# define DP_OUI_SUPPORT (1 << 7)
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#define DP_PSR_SUPPORT 0x070
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#define DP_I2C_SPEED_CAP 0x00c /* DPI */
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# define DP_I2C_SPEED_1K 0x01
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# define DP_I2C_SPEED_5K 0x02
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# define DP_I2C_SPEED_10K 0x04
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# define DP_I2C_SPEED_100K 0x08
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# define DP_I2C_SPEED_400K 0x10
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# define DP_I2C_SPEED_1M 0x20
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#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
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/* Multiple stream transport */
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#define DP_MSTM_CAP 0x021 /* 1.2 */
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# define DP_MST_CAP (1 << 0)
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#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071
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#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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@ -87,11 +118,36 @@
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# define DP_PSR_SETUP_TIME_MASK (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT 1
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/*
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* 0x80-0x8f describe downstream port capabilities, but there are two layouts
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* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
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* each port's descriptor is one byte wide. If it was set, each port's is
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* four bytes wide, starting with the one byte from the base info. As of
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* DP interop v1.1a only VGA defines additional detail.
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*/
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/* offset 0 */
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#define DP_DOWNSTREAM_PORT_0 0x80
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# define DP_DS_PORT_TYPE_MASK (7 << 0)
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# define DP_DS_PORT_TYPE_DP 0
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# define DP_DS_PORT_TYPE_VGA 1
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# define DP_DS_PORT_TYPE_DVI 2
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# define DP_DS_PORT_TYPE_HDMI 3
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# define DP_DS_PORT_TYPE_NON_EDID 4
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# define DP_DS_PORT_HPD (1 << 3)
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/* offset 1 for VGA is maximum megapixels per second / 8 */
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/* offset 2 */
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# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
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# define DP_DS_VGA_8BPC 0
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# define DP_DS_VGA_10BPC 1
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# define DP_DS_VGA_12BPC 2
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# define DP_DS_VGA_16BPC 3
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/* link configuration */
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14
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# define DP_LINK_BW_5_4 0x14 /* 1.2 */
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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@ -101,7 +157,7 @@
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3
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# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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@ -142,16 +198,32 @@
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#define DP_DOWNSPREAD_CTRL 0x107
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# define DP_SPREAD_AMP_0_5 (1 << 4)
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# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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# define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_PSR_EN_CFG 0x170
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#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
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/* bitmask as for DP_I2C_SPEED_CAP */
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#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
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#define DP_MSTM_CTRL 0x111 /* 1.2 */
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# define DP_MST_EN (1 << 0)
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# define DP_UP_REQ_EN (1 << 1)
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# define DP_UPSTREAM_IS_SRC (1 << 2)
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#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
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# define DP_PSR_ENABLE (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
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# define DP_PSR_CRC_VERIFICATION (1 << 2)
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# define DP_PSR_FRAME_CAPTURE (1 << 3)
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#define DP_SINK_COUNT 0x200
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/* prior to 1.2 bit 7 was reserved mbz */
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# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
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# define DP_SINK_CP_READY (1 << 6)
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#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
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# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
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# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
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@ -209,18 +281,22 @@
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# define DP_TEST_NAK (1 << 1)
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# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
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#define DP_SOURCE_OUI 0x300
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#define DP_SINK_OUI 0x400
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#define DP_BRANCH_OUI 0x500
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#define DP_SET_POWER 0x600
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# define DP_SET_POWER_D0 0x1
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# define DP_SET_POWER_D3 0x2
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#define DP_PSR_ERROR_STATUS 0x2006
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#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
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#define DP_PSR_ESI 0x2007
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#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
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# define DP_PSR_CAPS_CHANGE (1 << 0)
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#define DP_PSR_STATUS 0x2008
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#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
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# define DP_PSR_SINK_INACTIVE 0
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# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
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# define DP_PSR_SINK_ACTIVE_RFB 2
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@ -247,4 +323,34 @@ int iic_dp_aux_add_bus(device_t dev, const char *name,
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int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte),
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void *priv, device_t *bus, device_t *adapter);
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#define DP_LINK_STATUS_SIZE 6
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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#define DP_RECEIVER_CAP_SIZE 0xf
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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u8 drm_dp_link_rate_to_bw_code(int link_rate);
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int drm_dp_bw_code_to_link_rate(u8 link_bw);
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static inline int
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drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
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}
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static inline u8
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drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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}
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#endif /* _DRM_DP_HELPER_H_ */
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@ -11,6 +11,7 @@ SRCS = \
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drm_crtc.c \
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drm_crtc_helper.c \
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drm_dma.c \
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drm_dp_helper.c \
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drm_dp_iic_helper.c \
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drm_drawable.c \
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drm_drv.c \
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