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MFC r276249:

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Fix the musb initialization sequence on AM335x.

According to http://e2e.ti.com/support/arm/sitara_arm/f/791/t/210729 the
USB reset pulse has an undocumented duration of 200ns and during this
period the module must not be acessed.

We wait for 100us to take into account for some imprecision of the early
DELAY() loop.

This fixes the eventual 'External Non-Linefetch Abort (S)' that happens at
boot while resetting the musb subsystem.

While here, enable the USB subsystem clock before the first access.
This commit is contained in:
loos 2015-01-09 03:32:51 +00:00
parent baf17b5b91
commit 3897d680e7
1 changed files with 18 additions and 9 deletions
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27
sys/arm/ti/am335x/am335x_usbss.c
View File

@ -288,21 +288,30 @@ musbotg_attach(device_t dev)
return (ENXIO);
}
/* Enable device clocks. */
ti_prcm_clk_enable(MUSB0_CLK);
/*
* Reset USBSS, USB0 and USB1
* Reset USBSS, USB0 and USB1.
* The registers of USB subsystem must not be accessed while the
* reset pulse is active (200ns).
*/
USBSS_WRITE4(sc, USBSS_SYSCONFIG, USBSS_SYSCONFIG_SRESET);
DELAY(100);
i = 10;
while (USBSS_READ4(sc, USBSS_SYSCONFIG) & USBSS_SYSCONFIG_SRESET) {
DELAY(100);
if (i-- == 0) {
device_printf(dev, "reset timeout.\n");
return (ENXIO);
}
}
/* Read the module revision. */
rev = USBSS_READ4(sc, USBSS_REVREG);
device_printf(dev, "TI AM335X USBSS v%d.%d.%d\n",
(rev >> 8) & 7, (rev >> 6) & 3, rev & 63);
ti_prcm_clk_enable(MUSB0_CLK);
USBSS_WRITE4(sc, USBSS_SYSCONFIG,
USBSS_SYSCONFIG_SRESET);
while (USBSS_READ4(sc, USBSS_SYSCONFIG) &
USBSS_SYSCONFIG_SRESET)
;
err = bus_setup_intr(dev, sc->sc_irq_res[0],
INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)musbotg_usbss_interrupt, sc,