iwn(4) debugging improvements.
* Add in some new register debugging under IWN_DEBUG_REGISTER * Make IWN_DEBUG an option now for building. I'll chase this up with a commit to 'options' soon. Submitted by: Cedric GROSS <cg@cgross.info>
This commit is contained in:
Adrian Chadd
parent
cbe75ae8f5
commit
38b1a25dfd
@ -160,7 +160,9 @@ static void iwn5000_ict_reset(struct iwn_softc *);
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static int iwn_read_eeprom(struct iwn_softc *,
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uint8_t macaddr[IEEE80211_ADDR_LEN]);
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static void iwn4965_read_eeprom(struct iwn_softc *);
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#ifdef IWN_DEBUG
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static void iwn4965_print_power_group(struct iwn_softc *, int);
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#endif
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static void iwn5000_read_eeprom(struct iwn_softc *);
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static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
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static void iwn_read_eeprom_band(struct iwn_softc *, int);
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@ -320,9 +322,12 @@ static void iwn_set_channel(struct ieee80211com *);
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static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
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static void iwn_scan_mindwell(struct ieee80211_scan_state *);
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static void iwn_hw_reset(void *, int);
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#ifdef IWN_DEBUG
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static char *iwn_get_csr_string(int);
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static void iwn_debug_register(struct iwn_softc *);
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#endif
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#define IWN_DEBUG
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#ifdef IWN_DEBUG
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#ifdef IWN_DEBUG
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enum {
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IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
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IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
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@ -339,6 +344,7 @@ enum {
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IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
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IWN_DEBUG_TXRATE = 0x00002000, /* TX rate debugging */
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IWN_DEBUG_PWRSAVE = 0x00004000, /* Power save operations */
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IWN_DEBUG_REGISTER = 0x20000000, /* print chipset register */
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IWN_DEBUG_TRACE = 0x40000000, /* Print begin and start driver function */
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IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
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IWN_DEBUG_ANY = 0xffffffff
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@ -924,6 +930,8 @@ iwn_detach(device_t dev)
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struct ieee80211com *ic;
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int qid;
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DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__);
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if (ifp != NULL) {
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ic = ifp->if_l2com;
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@ -961,7 +969,7 @@ iwn_detach(device_t dev)
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if (ifp != NULL)
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if_free(ifp);
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DPRINTF(sc, IWN_DEBUG_TRACE, "->%s done\n", __func__);
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DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__);
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IWN_LOCK_DESTROY(sc);
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return 0;
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}
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@ -3202,8 +3210,6 @@ iwn_notif_intr(struct iwn_softc *sc)
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}
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case IWN_STATE_CHANGED:
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{
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uint32_t *status = (uint32_t *)(desc + 1);
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/*
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* State change allows hardware switch change to be
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* noted. However, we handle this in iwn_intr as we
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@ -3211,32 +3217,37 @@ iwn_notif_intr(struct iwn_softc *sc)
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*/
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bus_dmamap_sync(sc->rxq.data_dmat, data->map,
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BUS_DMASYNC_POSTREAD);
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#ifdef IWN_DEBUG
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uint32_t *status = (uint32_t *)(desc + 1);
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DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
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le32toh(*status));
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#endif
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break;
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}
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case IWN_START_SCAN:
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{
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struct iwn_start_scan *scan =
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(struct iwn_start_scan *)(desc + 1);
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bus_dmamap_sync(sc->rxq.data_dmat, data->map,
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BUS_DMASYNC_POSTREAD);
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#ifdef IWN_DEBUG
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struct iwn_start_scan *scan =
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(struct iwn_start_scan *)(desc + 1);
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DPRINTF(sc, IWN_DEBUG_ANY,
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"%s: scanning channel %d status %x\n",
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__func__, scan->chan, le32toh(scan->status));
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#endif
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break;
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}
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case IWN_STOP_SCAN:
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{
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struct iwn_stop_scan *scan =
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(struct iwn_stop_scan *)(desc + 1);
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bus_dmamap_sync(sc->rxq.data_dmat, data->map,
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BUS_DMASYNC_POSTREAD);
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#ifdef IWN_DEBUG
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struct iwn_stop_scan *scan =
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(struct iwn_stop_scan *)(desc + 1);
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DPRINTF(sc, IWN_DEBUG_STATE,
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"scan finished nchan=%d status=%d chan=%d\n",
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scan->nchan, scan->status, scan->chan);
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#endif
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IWN_UNLOCK(sc);
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ieee80211_scan_next(vap);
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@ -3416,6 +3427,9 @@ iwn_intr(void *arg)
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if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
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device_printf(sc->sc_dev, "%s: fatal firmware error\n",
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__func__);
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#ifdef IWN_DEBUG
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iwn_debug_register(sc);
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#endif
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/* Dump firmware error log and stop. */
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iwn_fatal_intr(sc);
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ifp->if_flags &= ~IFF_UP;
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@ -7467,3 +7481,85 @@ iwn_hw_reset(void *arg0, int pending)
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iwn_init(sc);
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ieee80211_notify_radio(ic, 1);
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}
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#ifdef IWN_DEBUG
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#define IWN_DESC(x) case x: return #x
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#define COUNTOF(array) (sizeof(array) / sizeof(array[0]))
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/*
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* Transate CSR code to string
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*/
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static char *iwn_get_csr_string(int csr)
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{
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switch (csr) {
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IWN_DESC(IWN_HW_IF_CONFIG);
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IWN_DESC(IWN_INT_COALESCING);
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IWN_DESC(IWN_INT);
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IWN_DESC(IWN_INT_MASK);
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IWN_DESC(IWN_FH_INT);
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IWN_DESC(IWN_GPIO_IN);
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IWN_DESC(IWN_RESET);
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IWN_DESC(IWN_GP_CNTRL);
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IWN_DESC(IWN_HW_REV);
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IWN_DESC(IWN_EEPROM);
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IWN_DESC(IWN_EEPROM_GP);
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IWN_DESC(IWN_OTP_GP);
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IWN_DESC(IWN_GIO);
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IWN_DESC(IWN_GP_UCODE);
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IWN_DESC(IWN_GP_DRIVER);
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IWN_DESC(IWN_UCODE_GP1);
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IWN_DESC(IWN_UCODE_GP2);
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IWN_DESC(IWN_LED);
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IWN_DESC(IWN_DRAM_INT_TBL);
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IWN_DESC(IWN_GIO_CHICKEN);
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IWN_DESC(IWN_ANA_PLL);
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IWN_DESC(IWN_HW_REV_WA);
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IWN_DESC(IWN_DBG_HPET_MEM);
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default:
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return "UNKNOWN CSR";
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}
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}
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/*
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* This function print firmware register
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*/
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static void
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iwn_debug_register(struct iwn_softc *sc)
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{
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int i;
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static const uint32_t csr_tbl[] = {
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IWN_HW_IF_CONFIG,
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IWN_INT_COALESCING,
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IWN_INT,
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IWN_INT_MASK,
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IWN_FH_INT,
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IWN_GPIO_IN,
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IWN_RESET,
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IWN_GP_CNTRL,
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IWN_HW_REV,
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IWN_EEPROM,
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IWN_EEPROM_GP,
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IWN_OTP_GP,
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IWN_GIO,
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IWN_GP_UCODE,
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IWN_GP_DRIVER,
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IWN_UCODE_GP1,
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IWN_UCODE_GP2,
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IWN_LED,
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IWN_DRAM_INT_TBL,
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IWN_GIO_CHICKEN,
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IWN_ANA_PLL,
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IWN_HW_REV_WA,
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IWN_DBG_HPET_MEM,
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};
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DPRINTF(sc, IWN_DEBUG_REGISTER,
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"CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s",
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"\n");
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for (i = 0; i < COUNTOF(csr_tbl); i++){
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DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ",
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iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i]));
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if ((i+1) % 3 == 0)
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DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n");
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}
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DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n");
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}
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#endif
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@ -62,6 +62,7 @@
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#define IWN_INT 0x008
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#define IWN_INT_MASK 0x00c
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#define IWN_FH_INT 0x010
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#define IWN_GPIO_IN 0x018 /* read external chip pins */
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#define IWN_RESET 0x020
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#define IWN_GP_CNTRL 0x024
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#define IWN_HW_REV 0x028
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@ -69,8 +70,12 @@
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#define IWN_EEPROM_GP 0x030
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#define IWN_OTP_GP 0x034
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#define IWN_GIO 0x03c
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#define IWN_GP_UCODE 0x048
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#define IWN_GP_DRIVER 0x050
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#define IWN_UCODE_GP1 0x054
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#define IWN_UCODE_GP1_SET 0x058
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#define IWN_UCODE_GP1_CLR 0x05c
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#define IWN_UCODE_GP2 0x060
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#define IWN_LED 0x094
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#define IWN_DRAM_INT_TBL 0x0a0
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#define IWN_SHADOW_REG_CTRL 0x0a8
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@ -79,6 +84,7 @@
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#define IWN_HW_REV_WA 0x22c
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#define IWN_DBG_HPET_MEM 0x240
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#define IWN_DBG_LINK_PWR_MGMT 0x250
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/* Need nic_lock for use above */
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#define IWN_MEM_RADDR 0x40c
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#define IWN_MEM_WADDR 0x410
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#define IWN_MEM_WDATA 0x418
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