iicbb: rebuild the bit-banging algorithms using different primitives
I2C_SET was quite inflexible, it used too long delays as well as some unnecessary delays. The new building blocks are iicbb_clockin and iicbb_clockout. The former sets SDA and starts the high period of SCL, the latter executes the low period of SCL. What happens during the high phase depends on the operation. For writes we just hold both lines, for reads we poll SDA. S, Sr and P change SDA in the middle of the high period. Also, the calculation of udelay has been updated, so that the resulting period more closely corresponds the requested bus frequency. There is a new knob, io_delay, that allows to further adjust udelay based on the estimated latency of pin toggling operations. Finally, I slightly changed debug tracing and added error indicators to it. The debug prints are compiled in but disabled by default. This can be of use if there is any fallout from this change. Some ideas for further improvements: - add a function for sub-microsecond delays (e.g., in units of 1/10th of a microsecond) and use it for more precise timing of short delays; - account for the actual time spent in the pin I/O. Some sample debug output with the new code follows. Reading temperature and humidity from HTU21 in the bus hold mode: <<w80+ we3+ <w81+ .....r6d+ rac+ r94- >> <<w80+ we5+ <w81+ .............r47+ re2+ r84- >> where '<<' is S, '<' is Sr, '>>' is P, '.' is one millisecond of clock stretching by the slave. Reading temperature and humidity in the no-hold mode: <<w80+ wf3+ >> <<w81- >> <<w81+ r6d+ r54+ raf- >> <<w80+ wf5+ >> <<w81- >> <<w81+ r48+ r4e+ r9c- >> where '+' is Ack and '-' is NoAck. We see that first read attempts are not acknowledged. MFC after: 4 weeks Differential Revision: https://reviews.freebsd.org/D22206
This commit is contained in:
avg
parent
4b7de30a80
commit
38b534838a
@ -75,6 +75,7 @@ __FBSDID("$FreeBSD$");
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struct iicbb_softc {
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device_t iicbus;
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u_int udelay; /* signal toggle delay in usec */
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u_int io_latency; /* approximate pin toggling latency */
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u_int scl_low_timeout;
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};
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@ -86,6 +87,7 @@ static int iicbb_probe(device_t);
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static int iicbb_callback(device_t, int, caddr_t);
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static int iicbb_start(device_t, u_char, int);
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static int iicbb_repstart(device_t, u_char, int);
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static int iicbb_stop(device_t);
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static int iicbb_write(device_t, const char *, int, int *, int);
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static int iicbb_read(device_t, char *, int, int *, int, int);
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@ -109,7 +111,7 @@ static device_method_t iicbb_methods[] = {
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/* iicbus interface */
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DEVMETHOD(iicbus_callback, iicbb_callback),
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DEVMETHOD(iicbus_start, iicbb_start),
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DEVMETHOD(iicbus_repeated_start, iicbb_start),
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DEVMETHOD(iicbus_repeated_start, iicbb_repstart),
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DEVMETHOD(iicbus_stop, iicbb_stop),
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DEVMETHOD(iicbus_write, iicbb_write),
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DEVMETHOD(iicbus_read, iicbb_read),
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@ -160,6 +162,11 @@ iicbb_attach(device_t dev)
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
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"scl_low_timeout", CTLFLAG_RWTUN, &sc->scl_low_timeout,
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0, "SCL low timeout, microseconds");
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SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
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SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
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"io_latency", CTLFLAG_RWTUN, &sc->io_latency,
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0, "Estimate of pin toggling latency, microseconds");
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bus_generic_attach(dev);
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return (0);
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}
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@ -217,80 +224,105 @@ iicbb_print_child(device_t bus, device_t dev)
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return (retval);
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}
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#define IICBB_DEBUG
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#ifdef IICBB_DEBUG
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static int i2c_debug = 0;
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static SYSCTL_NODE(_hw, OID_AUTO, i2c, CTLFLAG_RW, 0, "i2c debug");
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SYSCTL_INT(_hw_i2c, OID_AUTO, iicbb_debug, CTLFLAG_RWTUN,
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&i2c_debug, 0, "Enable i2c bit-banging driver debug");
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#define I2C_DEBUG(x) do { \
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if (i2c_debug) (x); \
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} while (0)
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#else
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#define I2C_DEBUG(x)
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#endif
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#define I2C_GETSDA(dev) (IICBB_GETSDA(device_get_parent(dev)))
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#define I2C_SETSDA(dev, x) (IICBB_SETSDA(device_get_parent(dev), x))
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#define I2C_GETSCL(dev) (IICBB_GETSCL(device_get_parent(dev)))
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#define I2C_SETSCL(dev, x) (IICBB_SETSCL(device_get_parent(dev), x))
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#define I2C_SET(sc, dev, ctrl, val) do { \
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iicbb_setscl(dev, ctrl); \
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I2C_SETSDA(dev, val); \
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DELAY(sc->udelay); \
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} while (0)
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static int i2c_debug = 0;
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#define I2C_DEBUG(x) do { \
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if (i2c_debug) (x); \
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} while (0)
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#define I2C_LOG(format,args...) do { \
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printf(format, args); \
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} while (0)
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static void
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iicbb_setscl(device_t dev, int val)
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static int
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iicbb_waitforscl(device_t dev)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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sbintime_t now, end;
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int fast_timeout;
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sbintime_t fast_timeout;
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sbintime_t now, timeout;
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I2C_SETSCL(dev, val);
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DELAY(sc->udelay);
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/* Pulling low cannot fail. */
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if (!val)
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return;
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/* Use DELAY for up to 1 ms, then switch to pause. */
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end = sbinuptime() + sc->scl_low_timeout * SBT_1US;
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fast_timeout = MIN(sc->scl_low_timeout, 1000);
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while (fast_timeout > 0) {
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/* Spin for up to 1 ms, then switch to pause. */
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now = sbinuptime();
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fast_timeout = now + SBT_1MS;
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timeout = now + sc->scl_low_timeout * SBT_1US;
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do {
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if (I2C_GETSCL(dev))
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return;
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I2C_SETSCL(dev, 1); /* redundant ? */
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DELAY(sc->udelay);
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fast_timeout -= sc->udelay;
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}
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while (!I2C_GETSCL(dev)) {
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return (0);
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now = sbinuptime();
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if (now >= end)
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break;
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} while (now < fast_timeout);
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do {
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I2C_DEBUG(printf("."));
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pause_sbt("iicbb-scl-low", SBT_1MS, C_PREL(8), 0);
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}
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if (I2C_GETSCL(dev))
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return (0);
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now = sbinuptime();
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} while (now < timeout);
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I2C_DEBUG(printf("*"));
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return (IIC_ETIMEOUT);
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}
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/* Start the high phase of the clock. */
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static int
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iicbb_clockin(device_t dev, int sda)
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{
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/*
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* Precondition: SCL is low.
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* Action:
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* - set SDA to the value;
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* - release SCL and wait until it's high.
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* The caller is responsible for keeping SCL high for udelay.
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*
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* There should be a data set-up time, 250 ns minimum, between setting
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* SDA and raising SCL. It's expected that the I/O access latency will
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* naturally provide that delay.
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*/
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I2C_SETSDA(dev, sda);
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I2C_SETSCL(dev, 1);
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return (iicbb_waitforscl(dev));
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}
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/*
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* End the high phase of the clock and wait out the low phase
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* as nothing interesting happens during it anyway.
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*/
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static void
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iicbb_one(device_t dev, int timeout)
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iicbb_clockout(device_t dev)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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I2C_SET(sc,dev,0,1);
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I2C_SET(sc,dev,1,1);
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I2C_SET(sc,dev,0,1);
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return;
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/*
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* Precondition: SCL is high.
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* Action:
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* - pull SCL low and hold for udelay.
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*/
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I2C_SETSCL(dev, 0);
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DELAY(sc->udelay);
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}
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static void
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iicbb_zero(device_t dev, int timeout)
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static int
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iicbb_sendbit(device_t dev, int bit)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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int err;
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I2C_SET(sc,dev,0,0);
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I2C_SET(sc,dev,1,0);
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I2C_SET(sc,dev,0,0);
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return;
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err = iicbb_clockin(dev, bit);
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if (err != 0)
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return (err);
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DELAY(sc->udelay);
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iicbb_clockout(dev);
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return (0);
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}
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/*
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@ -308,71 +340,84 @@ iicbb_zero(device_t dev, int timeout)
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* line low and then the SLAVE will release the SDA (data) line.
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*/
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static int
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iicbb_ack(device_t dev, int timeout)
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iicbb_getack(device_t dev)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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int noack;
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int k = 0;
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int noack, err;
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int t;
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I2C_SET(sc,dev,0,1);
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I2C_SET(sc,dev,1,1);
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/* Release SDA so that the slave can drive it. */
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err = iicbb_clockin(dev, 1);
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if (err != 0) {
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I2C_DEBUG(printf("! "));
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return (err);
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}
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/* SCL must be high now. */
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if (!I2C_GETSCL(dev))
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return (IIC_ETIMEOUT);
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do {
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/* Sample SDA until ACK (low) or udelay runs out. */
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for (t = 0; t < sc->udelay; t++) {
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noack = I2C_GETSDA(dev);
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if (!noack)
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break;
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DELAY(1);
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k++;
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} while (k < timeout);
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}
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I2C_SET(sc,dev,0,1);
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I2C_DEBUG(printf("%c ",noack?'-':'+'));
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DELAY(sc->udelay - t);
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iicbb_clockout(dev);
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I2C_DEBUG(printf("%c ", noack ? '-' : '+'));
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return (noack ? IIC_ENOACK : 0);
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}
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static void
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iicbb_sendbyte(device_t dev, u_char data, int timeout)
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static int
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iicbb_sendbyte(device_t dev, uint8_t data)
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{
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int i;
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int err, i;
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for (i=7; i>=0; i--) {
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if (data&(1<<i)) {
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iicbb_one(dev, timeout);
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} else {
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iicbb_zero(dev, timeout);
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for (i = 7; i >= 0; i--) {
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err = iicbb_sendbit(dev, (data & (1 << i)) != 0);
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if (err != 0) {
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I2C_DEBUG(printf("w!"));
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return (err);
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}
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}
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I2C_DEBUG(printf("w%02x",(int)data));
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return;
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I2C_DEBUG(printf("w%02x", data));
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return (0);
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}
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static u_char
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iicbb_readbyte(device_t dev, int last, int timeout)
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static int
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iicbb_readbyte(device_t dev, bool last, uint8_t *data)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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int i;
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unsigned char data=0;
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int i, err;
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I2C_SET(sc,dev,0,1);
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for (i=7; i>=0; i--)
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{
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I2C_SET(sc,dev,1,1);
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/*
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* Release SDA so that the slave can drive it.
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* We do not use iicbb_clockin() here because we need to release SDA
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* only once and then we just pulse the SCL.
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*/
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*data = 0;
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I2C_SETSDA(dev, 1);
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for (i = 7; i >= 0; i--) {
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I2C_SETSCL(dev, 1);
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err = iicbb_waitforscl(dev);
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if (err != 0) {
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I2C_DEBUG(printf("r! "));
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return (err);
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}
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DELAY((sc->udelay + 1) / 2);
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if (I2C_GETSDA(dev))
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data |= (1<<i);
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I2C_SET(sc,dev,0,1);
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*data |= 1 << i;
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DELAY((sc->udelay + 1) / 2);
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iicbb_clockout(dev);
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}
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if (last) {
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iicbb_one(dev, timeout);
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} else {
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iicbb_zero(dev, timeout);
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}
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I2C_DEBUG(printf("r%02x%c ",(int)data,last?'-':'+'));
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return (data);
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/*
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* Send master->slave ACK (low) for more data,
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* NoACK (high) otherwise.
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*/
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iicbb_sendbit(dev, last);
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I2C_DEBUG(printf("r%02x%c ", *data, last ? '-' : '+'));
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return (0);
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}
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static int
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@ -389,63 +434,106 @@ iicbb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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}
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static int
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iicbb_start(device_t dev, u_char slave, int timeout)
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iicbb_start_impl(device_t dev, u_char slave, bool repstart)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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int error;
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I2C_DEBUG(printf("<"));
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if (!repstart) {
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I2C_DEBUG(printf("<<"));
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I2C_SET(sc,dev,1,1);
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/* SCL must be high on the idle bus. */
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if (iicbb_waitforscl(dev) != 0) {
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I2C_DEBUG(printf("C!\n"));
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return (IIC_EBUSERR);
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}
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} else {
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I2C_DEBUG(printf("<"));
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error = iicbb_clockin(dev, 1);
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if (error != 0)
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return (error);
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/* SCL must be high now. */
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if (!I2C_GETSCL(dev))
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return (IIC_ETIMEOUT);
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/* SDA will go low in the middle of the SCL high phase. */
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DELAY((sc->udelay + 1) / 2);
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}
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I2C_SET(sc,dev,1,0);
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I2C_SET(sc,dev,0,0);
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/*
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* SDA must be high after the earlier stop condition or the end
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* of Ack/NoAck pulse.
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*/
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if (!I2C_GETSDA(dev)) {
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I2C_DEBUG(printf("D!\n"));
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return (IIC_EBUSERR);
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}
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/* Start: SDA high->low. */
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I2C_SETSDA(dev, 0);
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/* Wait the second half of the SCL high phase. */
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DELAY((sc->udelay + 1) / 2);
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/* Pull SCL low to keep the bus reserved. */
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iicbb_clockout(dev);
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/* send address */
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iicbb_sendbyte(dev, slave, timeout);
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error = iicbb_sendbyte(dev, slave);
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/* check for ack */
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error = iicbb_ack(dev, timeout);
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if (error == 0)
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return (0);
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iicbb_stop(dev);
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error = iicbb_getack(dev);
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if (error != 0)
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(void)iicbb_stop(dev);
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return (error);
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}
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/* NB: the timeout is ignored. */
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static int
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iicbb_start(device_t dev, u_char slave, int timeout)
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{
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return (iicbb_start_impl(dev, slave, false));
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}
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/* NB: the timeout is ignored. */
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static int
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iicbb_repstart(device_t dev, u_char slave, int timeout)
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{
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return (iicbb_start_impl(dev, slave, true));
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}
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static int
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iicbb_stop(device_t dev)
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{
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struct iicbb_softc *sc = device_get_softc(dev);
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int err = 0;
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I2C_SET(sc,dev,0,0);
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I2C_SET(sc,dev,1,0);
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I2C_SET(sc,dev,1,1);
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I2C_DEBUG(printf(">"));
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/*
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* Stop: SDA goes from low to high in the middle of the SCL high phase.
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*/
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err = iicbb_clockin(dev, 0);
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if (err != 0)
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return (err);
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DELAY((sc->udelay + 1) / 2);
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I2C_SETSDA(dev, 1);
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DELAY((sc->udelay + 1) / 2);
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I2C_DEBUG(printf("%s>>", err != 0 ? "!" : ""));
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I2C_DEBUG(printf("\n"));
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/* SCL must be high now. */
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if (!I2C_GETSCL(dev))
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return (IIC_ETIMEOUT);
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return (0);
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return (err);
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}
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/* NB: the timeout is ignored. */
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static int
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iicbb_write(device_t dev, const char *buf, int len, int *sent, int timeout)
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{
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int bytes, error = 0;
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||||
|
||||
bytes = 0;
|
||||
while (len) {
|
||||
while (len > 0) {
|
||||
/* send byte */
|
||||
iicbb_sendbyte(dev,(u_char)*buf++, timeout);
|
||||
iicbb_sendbyte(dev, (uint8_t)*buf++);
|
||||
|
||||
/* check for ack */
|
||||
error = iicbb_ack(dev, timeout);
|
||||
error = iicbb_getack(dev);
|
||||
if (error != 0)
|
||||
break;
|
||||
bytes++;
|
||||
@ -456,22 +544,25 @@ iicbb_write(device_t dev, const char *buf, int len, int *sent, int timeout)
|
||||
return (error);
|
||||
}
|
||||
|
||||
/* NB: whatever delay is, it's ignored. */
|
||||
static int
|
||||
iicbb_read(device_t dev, char * buf, int len, int *read, int last, int delay)
|
||||
iicbb_read(device_t dev, char *buf, int len, int *read, int last, int delay)
|
||||
{
|
||||
int bytes;
|
||||
int bytes = 0;
|
||||
int err = 0;
|
||||
|
||||
bytes = 0;
|
||||
while (len) {
|
||||
/* XXX should insert delay here */
|
||||
*buf++ = (char)iicbb_readbyte(dev, (len == 1) ? last : 0, delay);
|
||||
|
||||
bytes ++;
|
||||
len --;
|
||||
while (len > 0) {
|
||||
err = iicbb_readbyte(dev, (len == 1) ? last : 0,
|
||||
(uint8_t *)buf);
|
||||
if (err != 0)
|
||||
break;
|
||||
buf++;
|
||||
bytes++;
|
||||
len--;
|
||||
}
|
||||
|
||||
*read = bytes;
|
||||
return (0);
|
||||
return (err);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -492,18 +583,15 @@ iicbb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
|
||||
static void
|
||||
iicbb_set_speed(struct iicbb_softc *sc, u_char speed)
|
||||
{
|
||||
u_int busfreq, period;
|
||||
u_int busfreq;
|
||||
int period;
|
||||
|
||||
/*
|
||||
* NB: the resulting frequency will be a quarter (even less) of the
|
||||
* configured bus frequency. This is for historic reasons. The default
|
||||
* bus frequency is 100 kHz. And the historic default udelay is 10
|
||||
* microseconds. The cycle of sending a bit takes four udelay-s plus
|
||||
* SCL is kept low for extra two udelay-s. The actual I/O toggling also
|
||||
* has an overhead.
|
||||
* udelay is half a period, the clock is held high or low for this long.
|
||||
*/
|
||||
busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
|
||||
period = 1000000 / busfreq; /* Hz -> uS */
|
||||
period = 1000000 / 2 / busfreq; /* Hz -> uS */
|
||||
period -= sc->io_latency;
|
||||
sc->udelay = MAX(period, 1);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user