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Replace an outb() during the test for configuration mechanism #1 with a

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DELAY(1) instead.  After wading through old commit logs, I found that the
outb() was added not as part of the test but as an intentional delay. In
fact, according to Shanley's PCI book, the configuration 1 data and address
ports should only be accessed using aligned 32-bit accesses (i.e. inl()
and outl()).  Thus, using outb() to just the last byte of the port violates
the PCI spec it would seem.  On at least one box doing so broke the probe
for PCI, whereas changing it to a DELAY(1) fixed the probe.

Reported by:	Sean Welch <welchsm@earthlink.net>
MFC after:	1 week
This commit is contained in:
jhb 2003-12-31 16:56:32 +00:00
parent ec25118d4b
commit 390a3f79d8
2 changed files with 2 additions and 2 deletions
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2
sys/i386/pci/pci_cfgreg.c
View File

@ -732,7 +732,7 @@ pcireg_cfgopen(void)
devmax = 32; devmax = 32;
outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
outb(CONF1_ADDR_PORT + 3, 0); DELAY(1);
mode1res = inl(CONF1_ADDR_PORT); mode1res = inl(CONF1_ADDR_PORT);
outl(CONF1_ADDR_PORT, oldval1); outl(CONF1_ADDR_PORT, oldval1);

2
sys/i386/pci/pci_pir.c
View File

@ -732,7 +732,7 @@ pcireg_cfgopen(void)
devmax = 32; devmax = 32;
outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
outb(CONF1_ADDR_PORT + 3, 0); DELAY(1);
mode1res = inl(CONF1_ADDR_PORT); mode1res = inl(CONF1_ADDR_PORT);
outl(CONF1_ADDR_PORT, oldval1); outl(CONF1_ADDR_PORT, oldval1);