Moved sk(4) to /sys/dev/sk to sync with HEAD.
This commit is contained in:
yongari
parent
d0023ab87e
commit
3a3faaad1a
@ -791,6 +791,7 @@ dev/si/si_pci.c optional si pci
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dev/sio/sio_pccard.c optional sio pccard
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dev/sio/sio_pci.c optional sio pci
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dev/sio/sio_puc.c optional sio puc pci
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dev/sk/if_sk.c optional sk pci
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dev/smbus/smb.c optional smb
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dev/smbus/smbconf.c optional smbus
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dev/smbus/smbus.c optional smbus
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@ -1775,7 +1776,6 @@ pci/if_pcn.c optional pcn pci
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pci/if_rl.c optional rl pci
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pci/if_sf.c optional sf pci
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pci/if_sis.c optional sis pci
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pci/if_sk.c optional sk pci
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pci/if_ste.c optional ste pci
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pci/if_ti.c optional ti pci
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pci/if_tl.c optional tl pci
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2283
sys/dev/sk/if_sk.c
2283
sys/dev/sk/if_sk.c
File diff suppressed because it is too large
Load Diff
@ -55,23 +55,13 @@
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#define SK_YUKON 0xB0
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#define SK_YUKON_LITE 0xB1
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#define SK_YUKON_LP 0xB2
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#define SK_YUKON_XL 0xB3
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#define SK_YUKON_EC_U 0xB4
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#define SK_YUKON_EC 0xB6
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#define SK_YUKON_FE 0xB7
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#define SK_YUKON_FAMILY(x) ((x) & 0xB0)
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#define SK_IS_YUKON2(sc) \
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((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE)
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/* Known revisions in SK_CONFIG. */
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#define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
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#define SK_YUKON_LITE_REV_A1 0x3
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#define SK_YUKON_LITE_REV_A3 0x7
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#define SK_YUKON_EC_REV_A1 0x0
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#define SK_YUKON_EC_REV_A2 0x1
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#define SK_YUKON_EC_REV_A3 0x2
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/*
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* SysKonnect PCI vendor ID
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*/
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@ -88,13 +78,6 @@
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#define DEVICEID_SK_V1 0x4300
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#define DEVICEID_SK_V2 0x4320
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/*
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* Marvell gigabit ethernet device IDs
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*/
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#define DEVICEID_MRVL_4360 0x4360
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#define DEVICEID_MRVL_4361 0x4361
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#define DEVICEID_MRVL_4362 0x4362
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/*
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* Belkin F5D5005
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*/
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@ -362,10 +345,8 @@
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#define SK_CONFIG 0x011A
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#define SK_CHIPVER 0x011B
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#define SK_EPROM0 0x011C
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#define SK_EPROM1 0x011D /* yukon/genesis */
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#define SK_Y2_CLKGATE 0x011D /* yukon 2 */
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#define SK_EPROM2 0x011E /* yukon/genesis */
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#define SK_Y2_HWRES 0x011E /* yukon 2 */
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#define SK_EPROM1 0x011D
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#define SK_EPROM2 0x011E
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#define SK_EPROM3 0x011F
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#define SK_EP_ADDR 0x0120
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#define SK_EP_DATA 0x0124
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@ -471,13 +452,6 @@
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#define SK_GPIO_DIR8 0x01000000
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#define SK_GPIO_DIR9 0x02000000
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#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */
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#define SK_Y2_HWRES_LINK_1 0x01
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#define SK_Y2_HWRES_LINK_2 0x02
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#define SK_Y2_HWRES_LINK_MASK (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
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#define SK_Y2_HWRES_LINK_DUAL (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
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/* Block 3 Ram interface and MAC arbiter registers */
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#define SK_RAMADDR 0x0180
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#define SK_RAMDATA0 0x0184
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@ -819,13 +793,13 @@
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(SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
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SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
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SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
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SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
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SK_TXBMU_DESC_UNRESET)
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#define SK_TXBMU_OFFLINE \
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(SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
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SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
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SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
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SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
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SK_TXBMU_DESC_RESET)
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/* Block 16 -- Receive RAMbuffer 1 */
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#define SK_RXRB1_START 0x0800
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@ -920,31 +894,24 @@
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#define SK_RXMF1_END 0x0C40
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#define SK_RXMF1_THRESHOLD 0x0C44
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#define SK_RXMF1_CTRL_TEST 0x0C48
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#define SK_RXMF1_FLUSH_MASK 0x0C4C
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#define SK_RXMF1_FLUSH_THRESHOLD 0x0C50
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#define SK_RXMF1_WRITE_PTR 0x0C60
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#define SK_RXMF1_WRITE_LEVEL 0x0C68
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#define SK_RXMF1_READ_PTR 0x0C70
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#define SK_RXMF1_READ_LEVEL 0x0C78
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/* Receive MAC FIFO 1 Control/Test */
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#define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
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#define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
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#define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
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#define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
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#define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
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#define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
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#define SK_RFCTL_FIFO_FLUSH_OFF 0x00000080 /* RX FIFO Flsuh mode off */
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#define SK_RFCTL_FIFO_FLUSH_ON 0x00000040 /* RX FIFO Flush mode on */
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#define SK_RFCTL_RX_FIFO_OVER 0x00000020 /* Clear IRQ RX FIFO Overrun */
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#define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */
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#define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */
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#define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
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#define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
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#define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
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#define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
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#define SK_RFCTL_FIFO_THRESHOLD 0x0a /* flush threshold (default) */
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/* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
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#define SK_RXF2_END 0x0C80
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#define SK_RXF2_WPTR 0x0C84
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@ -1004,7 +971,7 @@
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#define SK_TXLED1_CTL 0x0D28
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#define SK_TXLED1_TST 0x0D29
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/* Transmit MAC FIFO 1 (Yukon Only) */
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/* Receive MAC FIFO 1 (Yukon Only) */
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#define SK_TXMF1_END 0x0D40
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#define SK_TXMF1_THRESHOLD 0x0D44
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#define SK_TXMF1_CTRL_TEST 0x0D48
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@ -1015,7 +982,6 @@
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#define SK_TXMF1_RESTART_PTR 0x0D74
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#define SK_TXMF1_READ_LEVEL 0x0D78
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/* Transmit MAC FIFO Control/Test */
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#define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
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#define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
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#define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
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@ -1073,8 +1039,6 @@
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#define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */
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#define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */
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#define SK_DPT_TIMER_MAX 0x00ffffffff /* 214.75ms at 78.125MHz */
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#define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */
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#define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */
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#define SK_DPT_TCTL_START 0x0002 /* Start Timer */
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@ -1090,7 +1054,7 @@
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#define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */
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#define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */
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#define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */
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#define SK_GMAC_IMR 0x0f0c /* GMAC Interrupt Mask Register */
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#define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */
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#define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */
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#define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */
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#define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */
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@ -1346,11 +1310,6 @@ struct sk_type {
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char *sk_name;
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};
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#define SK_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff)
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#define SK_ADDR_HI(x) ((u_int64_t) (x) >> 32)
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#define SK_RING_ALIGN 64
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/* RX queue descriptor data structure */
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struct sk_rx_desc {
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u_int32_t sk_ctl;
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@ -1359,8 +1318,10 @@ struct sk_rx_desc {
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u_int32_t sk_data_hi;
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u_int32_t sk_xmac_rxstat;
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u_int32_t sk_timestamp;
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u_int32_t sk_csum;
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u_int32_t sk_csum_start;
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u_int16_t sk_csum2;
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u_int16_t sk_csum1;
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u_int16_t sk_csum2_start;
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u_int16_t sk_csum1_start;
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};
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#define SK_OPCODE_DEFAULT 0x00550000
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@ -1378,7 +1339,8 @@ struct sk_rx_desc {
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#define SK_RXCTL_OWN 0x80000000
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#define SK_RXSTAT \
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(SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG|SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
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(SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
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SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
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struct sk_tx_desc {
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u_int32_t sk_ctl;
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@ -1386,8 +1348,10 @@ struct sk_tx_desc {
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u_int32_t sk_data_lo;
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u_int32_t sk_data_hi;
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u_int32_t sk_xmac_txstat;
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u_int32_t sk_csum_startval;
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u_int32_t sk_csum_start;
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u_int16_t sk_rsvd0;
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u_int16_t sk_csum_startval;
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u_int16_t sk_csum_startpos;
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u_int16_t sk_csum_writepos;
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u_int32_t sk_rsvd1;
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};
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@ -1405,14 +1369,11 @@ struct sk_tx_desc {
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#define SK_TXSTAT \
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(SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
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#define SK_RXBYTES(x) ((x) & 0x0000FFFF)
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#define SK_RXBYTES(x) (x) & 0x0000FFFF;
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#define SK_TXBYTES SK_RXBYTES
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#define SK_TX_RING_CNT 512
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#define SK_RX_RING_CNT 256
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#define SK_JUMBO_RX_RING_CNT 256
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#define SK_MAXTXSEGS 32
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#define SK_MAXRXSEGS 32
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/*
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* Jumbo buffer stuff. Note that we must allocate more jumbo
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@ -1424,9 +1385,6 @@ struct sk_tx_desc {
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*/
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#define SK_JUMBO_FRAMELEN 9018
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#define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
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#define SK_MAX_FRAMELEN \
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(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
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#define SK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
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#define SK_JSLOTS ((SK_RX_RING_CNT * 3) / 2)
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#define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
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@ -1441,73 +1399,32 @@ struct sk_jpool_entry {
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SLIST_ENTRY(sk_jpool_entry) jpool_entries;
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};
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struct sk_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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STAILQ_ENTRY(sk_txdesc) tx_q;
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};
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STAILQ_HEAD(sk_txdq, sk_txdesc);
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struct sk_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct sk_chain {
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void *sk_desc;
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struct mbuf *sk_mbuf;
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struct sk_chain *sk_next;
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};
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struct sk_chain_data {
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bus_dma_tag_t sk_parent_tag;
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bus_dma_tag_t sk_tx_tag;
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struct sk_txdesc sk_txdesc[SK_TX_RING_CNT];
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struct sk_txdq sk_txfreeq;
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struct sk_txdq sk_txbusyq;
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bus_dma_tag_t sk_rx_tag;
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struct sk_rxdesc sk_rxdesc[SK_RX_RING_CNT];
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bus_dma_tag_t sk_tx_ring_tag;
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bus_dma_tag_t sk_rx_ring_tag;
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bus_dmamap_t sk_tx_ring_map;
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bus_dmamap_t sk_rx_ring_map;
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bus_dmamap_t sk_rx_sparemap;
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bus_dma_tag_t sk_jumbo_rx_tag;
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bus_dma_tag_t sk_jumbo_tag;
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bus_dmamap_t sk_jumbo_map;
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bus_dma_tag_t sk_jumbo_mtag;
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caddr_t sk_jslots[SK_JSLOTS];
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struct sk_rxdesc sk_jumbo_rxdesc[SK_JUMBO_RX_RING_CNT];
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bus_dma_tag_t sk_jumbo_rx_ring_tag;
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bus_dmamap_t sk_jumbo_rx_ring_map;
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bus_dmamap_t sk_jumbo_rx_sparemap;
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struct sk_chain sk_tx_chain[SK_TX_RING_CNT];
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struct sk_chain sk_rx_chain[SK_RX_RING_CNT];
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int sk_tx_prod;
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int sk_tx_cons;
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int sk_tx_cnt;
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int sk_rx_prod;
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int sk_rx_cons;
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int sk_jumbo_rx_cons;
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int sk_rx_cnt;
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/* Stick the jumbo mem management stuff here too. */
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caddr_t sk_jslots[SK_JSLOTS];
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void *sk_jumbo_buf;
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};
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struct sk_ring_data {
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struct sk_tx_desc *sk_tx_ring;
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bus_addr_t sk_tx_ring_paddr;
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struct sk_rx_desc *sk_rx_ring;
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bus_addr_t sk_rx_ring_paddr;
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struct sk_rx_desc *sk_jumbo_rx_ring;
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bus_addr_t sk_jumbo_rx_ring_paddr;
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void *sk_jumbo_buf;
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bus_addr_t sk_jumbo_buf_paddr;
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struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT];
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struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT];
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};
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#define SK_TX_RING_ADDR(sc, i) \
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((sc)->sk_rdata.sk_tx_ring_paddr + sizeof(struct sk_tx_desc) * (i))
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#define SK_RX_RING_ADDR(sc, i) \
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((sc)->sk_rdata.sk_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
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#define SK_JUMBO_RX_RING_ADDR(sc, i) \
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((sc)->sk_rdata.sk_jumbo_rx_ring_paddr + sizeof(struct sk_rx_desc) * (i))
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#define SK_TX_RING_SZ \
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(sizeof(struct sk_tx_desc) * SK_TX_RING_CNT)
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#define SK_RX_RING_SZ \
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(sizeof(struct sk_rx_desc) * SK_RX_RING_CNT)
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#define SK_JUMBO_RX_RING_SZ \
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(sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT)
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struct sk_bcom_hack {
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int reg;
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int val;
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@ -1525,7 +1442,7 @@ struct sk_softc {
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void *sk_intrhand; /* irq handler handle */
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struct resource *sk_irq; /* IRQ resource handle */
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struct resource *sk_res; /* I/O or shared mem handle */
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device_t sk_dev;
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u_int8_t sk_unit; /* controller number */
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u_int8_t sk_type;
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u_int8_t sk_rev;
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u_int8_t spare;
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@ -1535,14 +1452,11 @@ struct sk_softc {
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u_int32_t sk_rboff; /* RAMbuffer offset */
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u_int32_t sk_ramsize; /* amount of RAM on NIC */
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u_int32_t sk_pmd; /* physical media type */
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u_int32_t sk_coppertype;
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u_int32_t sk_intrmask;
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int sk_int_mod;
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int sk_int_ticks;
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int sk_suspended;
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struct sk_if_softc *sk_if[2];
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device_t sk_devs[2];
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struct mtx sk_mii_mtx;
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struct mtx sk_mtx;
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};
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@ -1552,14 +1466,12 @@ struct sk_softc {
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#define SK_IF_LOCK(_sc) SK_LOCK((_sc)->sk_softc)
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#define SK_IF_UNLOCK(_sc) SK_UNLOCK((_sc)->sk_softc)
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#define SK_IF_LOCK_ASSERT(_sc) SK_LOCK_ASSERT((_sc)->sk_softc)
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#define SK_IF_MII_LOCK(_sc) mtx_lock(&(_sc)->sk_softc->sk_mii_mtx)
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#define SK_IF_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_softc->sk_mii_mtx)
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/* Softc for each logical interface */
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struct sk_if_softc {
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struct ifnet *sk_ifp; /* interface info */
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device_t sk_miibus;
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device_t sk_if_dev;
|
||||
u_int8_t sk_unit; /* interface number */
|
||||
u_int8_t sk_port; /* port # on controller */
|
||||
u_int8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */
|
||||
u_int32_t sk_rx_ramstart;
|
||||
@ -1568,10 +1480,12 @@ struct sk_if_softc {
|
||||
u_int32_t sk_tx_ramend;
|
||||
int sk_phytype;
|
||||
int sk_phyaddr;
|
||||
device_t sk_dev;
|
||||
int sk_cnt;
|
||||
int sk_link;
|
||||
struct callout sk_tick_ch;
|
||||
struct callout_handle sk_tick_ch;
|
||||
struct sk_chain_data sk_cdata;
|
||||
struct sk_ring_data sk_rdata;
|
||||
struct sk_ring_data *sk_rdata;
|
||||
struct sk_softc *sk_softc; /* parent controller */
|
||||
int sk_tx_bmu; /* TX BMU register */
|
||||
int sk_if_flags;
|
||||
@ -1583,4 +1497,11 @@ struct sk_if_softc {
|
||||
#define SK_JLIST_LOCK(_sc) mtx_lock(&(_sc)->sk_jlist_mtx)
|
||||
#define SK_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->sk_jlist_mtx)
|
||||
|
||||
#define SK_MAXUNIT 256
|
||||
#define SK_TIMEOUT 1000
|
||||
#define ETHER_ALIGN 2
|
||||
|
||||
#ifdef __alpha__
|
||||
#undef vtophys
|
||||
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
|
||||
#endif
|
||||
|
||||
@ -317,9 +317,6 @@
|
||||
#define XM_RXSTAT_VLAN_LEV1 0x00010000
|
||||
#define XM_RXSTAT_VLAN_LEV2 0x00020000
|
||||
#define XM_RXSTAT_LEN 0xFFFC0000
|
||||
#define XM_RXSTAT_LENSHIFT 18
|
||||
|
||||
#define XM_RXSTAT_BYTES(x) ((x) >> XM_RXSTAT_LENSHIFT)
|
||||
|
||||
/*
|
||||
* XMAC PHY registers, indirectly accessed through
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
|
||||
#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
|
||||
#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
|
||||
#define YU_GPSR_FCTL_TX 0x2000 /* Tx flow control, 1 - disabled */
|
||||
#define YU_GPSR_FCTL_TX 0x2000 /* flow control */
|
||||
#define YU_GPSR_LINK 0x1000 /* link status (down/up) */
|
||||
#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
|
||||
#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
|
||||
@ -31,26 +31,25 @@
|
||||
#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
|
||||
#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */
|
||||
#define YU_GPSR_PARTITION 0x0008 /* partition mode */
|
||||
#define YU_GPSR_FCTL_RX 0x0004 /* Rx flow control, 1 - disabled */
|
||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode, 1 - enabled */
|
||||
#define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */
|
||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */
|
||||
|
||||
/* General Purpose Control Register (GPCR) */
|
||||
#define YUKON_GPCR 0x0004
|
||||
|
||||
#define YU_GPCR_FCTL_TX_DIS 0x2000 /* Disable Tx flow control 802.3x */
|
||||
#define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */
|
||||
#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */
|
||||
#define YU_GPCR_RXEN 0x0800 /* Receive Enable */
|
||||
#define YU_GPCR_BURSTEN 0x0400 /* Burst Mode Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* MAC Loopback Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* Loopback Enable */
|
||||
#define YU_GPCR_PAR 0x0100 /* Partition Enable */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed 1000Mbps */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed */
|
||||
#define YU_GPCR_FLP 0x0040 /* Force Link Pass */
|
||||
#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */
|
||||
#define YU_GPCR_FCTL_RX_DIS 0x0010 /* Disable Rx flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed 100Mbps */
|
||||
#define YU_GPCR_DPLX_DIS 0x0004 /* Disable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_DIS 0x0002 /* Disable Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_DIS 0x0001 /* Disable Auto-Update for speed */
|
||||
#define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed */
|
||||
#define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */
|
||||
|
||||
/* Transmit Control Register (TCR) */
|
||||
#define YUKON_TCR 0x0008
|
||||
@ -170,21 +169,3 @@
|
||||
|
||||
#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */
|
||||
#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */
|
||||
|
||||
/* Receive status */
|
||||
#define YU_RXSTAT_FOFL 0x00000001 /* Rx FIFO overflow */
|
||||
#define YU_RXSTAT_CRCERR 0x00000002 /* CRC error */
|
||||
#define YU_RXSTAT_FRAGMENT 0x00000008 /* fragment */
|
||||
#define YU_RXSTAT_LONGERR 0x00000010 /* too long packet */
|
||||
#define YU_RXSTAT_MIIERR 0x00000020 /* MII error */
|
||||
#define YU_RXSTAT_BADFC 0x00000040 /* bad flow-control packet */
|
||||
#define YU_RXSTAT_GOODFC 0x00000080 /* good flow-control packet */
|
||||
#define YU_RXSTAT_RXOK 0x00000100 /* receice OK (Good packet) */
|
||||
#define YU_RXSTAT_BROADCAST 0x00000200 /* broadcast packet */
|
||||
#define YU_RXSTAT_MULTICAST 0x00000400 /* multicast packet */
|
||||
#define YU_RXSTAT_RUNT 0x00000800 /* undersize packet */
|
||||
#define YU_RXSTAT_JABBER 0x00001000 /* jabber packet */
|
||||
#define YU_RXSTAT_VLAN 0x00002000 /* VLAN packet */
|
||||
#define YU_RXSTAT_LENSHIFT 16
|
||||
|
||||
#define YU_RXSTAT_BYTES(x) ((x) >> YU_RXSTAT_LENSHIFT)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../pci
|
||||
.PATH: ${.CURDIR}/../../dev/sk
|
||||
|
||||
KMOD= if_sk
|
||||
SRCS= if_sk.c opt_bdg.h device_if.h bus_if.h pci_if.h
|
||||
|
||||
3054
sys/pci/if_sk.c
3054
sys/pci/if_sk.c
File diff suppressed because it is too large
Load Diff
1504
sys/pci/if_skreg.h
1504
sys/pci/if_skreg.h
File diff suppressed because it is too large
Load Diff
@ -1,403 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 1997, 1998, 1999, 2000
|
||||
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Registers and data structures for the XaQti Corporation XMAC II
|
||||
* Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com.
|
||||
* The XMAC can be programmed for 16-bit or 32-bit register access modes.
|
||||
* The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's
|
||||
* how the registers are laid out here.
|
||||
*/
|
||||
|
||||
#define XM_DEVICEID 0x00E0AE20
|
||||
#define XM_XAQTI_OUI 0x00E0AE
|
||||
|
||||
#define XM_XMAC_REV(x) (((x) & 0x000000E0) >> 5)
|
||||
|
||||
#define XM_XMAC_REV_B2 0x0
|
||||
#define XM_XMAC_REV_C1 0x1
|
||||
|
||||
#define XM_MMUCMD 0x0000
|
||||
#define XM_POFF 0x0008
|
||||
#define XM_BURST 0x000C
|
||||
#define XM_VLAN_TAGLEV1 0x0010
|
||||
#define XM_VLAN_TAGLEV2 0x0014
|
||||
#define XM_TXCMD 0x0020
|
||||
#define XM_TX_RETRYLIMIT 0x0024
|
||||
#define XM_TX_SLOTTIME 0x0028
|
||||
#define XM_TX_IPG 0x003C
|
||||
#define XM_RXCMD 0x0030
|
||||
#define XM_PHY_ADDR 0x0034
|
||||
#define XM_PHY_DATA 0x0038
|
||||
#define XM_GPIO 0x0040
|
||||
#define XM_IMR 0x0044
|
||||
#define XM_ISR 0x0048
|
||||
#define XM_HWCFG 0x004C
|
||||
#define XM_TX_LOWAT 0x0060
|
||||
#define XM_TX_HIWAT 0x0062
|
||||
#define XM_TX_REQTHRESH_LO 0x0064
|
||||
#define XM_TX_REQTHRESH_HI 0x0066
|
||||
#define XM_TX_REQTHRESH XM_TX_REQTHRESH_LO
|
||||
#define XM_PAUSEDST0 0x0068
|
||||
#define XM_PAUSEDST1 0x006A
|
||||
#define XM_PAUSEDST2 0x006C
|
||||
#define XM_CTLPARM_LO 0x0070
|
||||
#define XM_CTLPARM_HI 0x0072
|
||||
#define XM_CTLPARM XM_CTLPARM_LO
|
||||
#define XM_OPCODE_PAUSE_TIMER 0x0074
|
||||
#define XM_TXSTAT_LIFO 0x0078
|
||||
|
||||
/*
|
||||
* Perfect filter registers. The XMAC has a table of 16 perfect
|
||||
* filter entries, spaced 8 bytes apart. This is in addition to
|
||||
* the station address registers, which appear below.
|
||||
*/
|
||||
#define XM_RXFILT_BASE 0x0080
|
||||
#define XM_RXFILT_END 0x0107
|
||||
#define XM_RXFILT_MAX 16
|
||||
#define XM_RXFILT_ENTRY(ent) (XM_RXFILT_BASE + ((ent * 8)))
|
||||
|
||||
/* Primary station address. */
|
||||
#define XM_PAR0 0x0108
|
||||
#define XM_PAR1 0x010A
|
||||
#define XM_PAR2 0x010C
|
||||
|
||||
/* 64-bit multicast hash table registers */
|
||||
#define XM_MAR0 0x0110
|
||||
#define XM_MAR1 0x0112
|
||||
#define XM_MAR2 0x0114
|
||||
#define XM_MAR3 0x0116
|
||||
#define XM_RX_LOWAT 0x0118
|
||||
#define XM_RX_HIWAT 0x011A
|
||||
#define XM_RX_REQTHRESH_LO 0x011C
|
||||
#define XM_RX_REQTHRESH_HI 0x011E
|
||||
#define XM_RX_REQTHRESH XM_RX_REQTHRESH_LO
|
||||
#define XM_DEVID_LO 0x0120
|
||||
#define XM_DEVID_HI 0x0122
|
||||
#define XM_DEVID XM_DEVID_LO
|
||||
#define XM_MODE_LO 0x0124
|
||||
#define XM_MODE_HI 0x0126
|
||||
#define XM_MODE XM_MODE_LO
|
||||
#define XM_LASTSRC0 0x0128
|
||||
#define XM_LASTSRC1 0x012A
|
||||
#define XM_LASTSRC2 0x012C
|
||||
#define XM_TSTAMP_READ 0x0130
|
||||
#define XM_TSTAMP_LOAD 0x0134
|
||||
#define XM_STATS_CMD 0x0200
|
||||
#define XM_RXCNT_EVENT_LO 0x0204
|
||||
#define XM_RXCNT_EVENT_HI 0x0206
|
||||
#define XM_RXCNT_EVENT XM_RXCNT_EVENT_LO
|
||||
#define XM_TXCNT_EVENT_LO 0x0208
|
||||
#define XM_TXCNT_EVENT_HI 0x020A
|
||||
#define XM_TXCNT_EVENT XM_TXCNT_EVENT_LO
|
||||
#define XM_RXCNT_EVMASK_LO 0x020C
|
||||
#define XM_RXCNT_EVMASK_HI 0x020E
|
||||
#define XM_RXCNT_EVMASK XM_RXCNT_EVMASK_LO
|
||||
#define XM_TXCNT_EVMASK_LO 0x0210
|
||||
#define XM_TXCNT_EVMASK_HI 0x0212
|
||||
#define XM_TXCNT_EVMASK XM_TXCNT_EVMASK_LO
|
||||
|
||||
/* Statistics command register */
|
||||
#define XM_STATCMD_CLR_TX 0x0001
|
||||
#define XM_STATCMD_CLR_RX 0x0002
|
||||
#define XM_STATCMD_COPY_TX 0x0004
|
||||
#define XM_STATCMD_COPY_RX 0x0008
|
||||
#define XM_STATCMD_SNAP_TX 0x0010
|
||||
#define XM_STATCMD_SNAP_RX 0x0020
|
||||
|
||||
/* TX statistics registers */
|
||||
#define XM_TXSTATS_PKTSOK 0x280
|
||||
#define XM_TXSTATS_BYTESOK_HI 0x284
|
||||
#define XM_TXSTATS_BYTESOK_LO 0x288
|
||||
#define XM_TXSTATS_BCASTSOK 0x28C
|
||||
#define XM_TXSTATS_MCASTSOK 0x290
|
||||
#define XM_TXSTATS_UCASTSOK 0x294
|
||||
#define XM_TXSTATS_GIANTS 0x298
|
||||
#define XM_TXSTATS_BURSTCNT 0x29C
|
||||
#define XM_TXSTATS_PAUSEPKTS 0x2A0
|
||||
#define XM_TXSTATS_MACCTLPKTS 0x2A4
|
||||
#define XM_TXSTATS_SINGLECOLS 0x2A8
|
||||
#define XM_TXSTATS_MULTICOLS 0x2AC
|
||||
#define XM_TXSTATS_EXCESSCOLS 0x2B0
|
||||
#define XM_TXSTATS_LATECOLS 0x2B4
|
||||
#define XM_TXSTATS_DEFER 0x2B8
|
||||
#define XM_TXSTATS_EXCESSDEFER 0x2BC
|
||||
#define XM_TXSTATS_UNDERRUN 0x2C0
|
||||
#define XM_TXSTATS_CARRIERSENSE 0x2C4
|
||||
#define XM_TXSTATS_UTILIZATION 0x2C8
|
||||
#define XM_TXSTATS_64 0x2D0
|
||||
#define XM_TXSTATS_65_127 0x2D4
|
||||
#define XM_TXSTATS_128_255 0x2D8
|
||||
#define XM_TXSTATS_256_511 0x2DC
|
||||
#define XM_TXSTATS_512_1023 0x2E0
|
||||
#define XM_TXSTATS_1024_MAX 0x2E4
|
||||
|
||||
/* RX statistics registers */
|
||||
#define XM_RXSTATS_PKTSOK 0x300
|
||||
#define XM_RXSTATS_BYTESOK_HI 0x304
|
||||
#define XM_RXSTATS_BYTESOK_LO 0x308
|
||||
#define XM_RXSTATS_BCASTSOK 0x30C
|
||||
#define XM_RXSTATS_MCASTSOK 0x310
|
||||
#define XM_RXSTATS_UCASTSOK 0x314
|
||||
#define XM_RXSTATS_PAUSEPKTS 0x318
|
||||
#define XM_RXSTATS_MACCTLPKTS 0x31C
|
||||
#define XM_RXSTATS_BADPAUSEPKTS 0x320
|
||||
#define XM_RXSTATS_BADMACCTLPKTS 0x324
|
||||
#define XM_RXSTATS_BURSTCNT 0x328
|
||||
#define XM_RXSTATS_MISSEDPKTS 0x32C
|
||||
#define XM_RXSTATS_FRAMEERRS 0x330
|
||||
#define XM_RXSTATS_OVERRUN 0x334
|
||||
#define XM_RXSTATS_JABBER 0x338
|
||||
#define XM_RXSTATS_CARRLOSS 0x33C
|
||||
#define XM_RXSTATS_INRNGLENERR 0x340
|
||||
#define XM_RXSTATS_SYMERR 0x344
|
||||
#define XM_RXSTATS_SHORTEVENT 0x348
|
||||
#define XM_RXSTATS_RUNTS 0x34C
|
||||
#define XM_RXSTATS_GIANTS 0x350
|
||||
#define XM_RXSTATS_CRCERRS 0x354
|
||||
#define XM_RXSTATS_CEXTERRS 0x35C
|
||||
#define XM_RXSTATS_UTILIZATION 0x360
|
||||
#define XM_RXSTATS_64 0x368
|
||||
#define XM_RXSTATS_65_127 0x36C
|
||||
#define XM_RXSTATS_128_255 0x370
|
||||
#define XM_RXSTATS_256_511 0x374
|
||||
#define XM_RXSTATS_512_1023 0x378
|
||||
#define XM_RXSTATS_1024_MAX 0x37C
|
||||
|
||||
#define XM_MMUCMD_TX_ENB 0x0001
|
||||
#define XM_MMUCMD_RX_ENB 0x0002
|
||||
#define XM_MMUCMD_GMIILOOP 0x0004
|
||||
#define XM_MMUCMD_RATECTL 0x0008
|
||||
#define XM_MMUCMD_GMIIFDX 0x0010
|
||||
#define XM_MMUCMD_NO_MGMT_PRMB 0x0020
|
||||
#define XM_MMUCMD_SIMCOL 0x0040
|
||||
#define XM_MMUCMD_FORCETX 0x0080
|
||||
#define XM_MMUCMD_LOOPENB 0x0200
|
||||
#define XM_MMUCMD_IGNPAUSE 0x0400
|
||||
#define XM_MMUCMD_PHYBUSY 0x0800
|
||||
#define XM_MMUCMD_PHYDATARDY 0x1000
|
||||
|
||||
#define XM_TXCMD_AUTOPAD 0x0001
|
||||
#define XM_TXCMD_NOCRC 0x0002
|
||||
#define XM_TXCMD_NOPREAMBLE 0x0004
|
||||
#define XM_TXCMD_NOGIGAMODE 0x0008
|
||||
#define XM_TXCMD_SAMPLELINE 0x0010
|
||||
#define XM_TXCMD_ENCBYPASS 0x0020
|
||||
#define XM_TXCMD_XMITBK2BK 0x0040
|
||||
#define XM_TXCMD_FAIRSHARE 0x0080
|
||||
|
||||
#define XM_RXCMD_DISABLE_CEXT 0x0001
|
||||
#define XM_RXCMD_STRIPPAD 0x0002
|
||||
#define XM_RXCMD_SAMPLELINE 0x0004
|
||||
#define XM_RXCMD_SELFRX 0x0008
|
||||
#define XM_RXCMD_STRIPFCS 0x0010
|
||||
#define XM_RXCMD_TRANSPARENT 0x0020
|
||||
#define XM_RXCMD_IPGCAPTURE 0x0040
|
||||
#define XM_RXCMD_BIGPKTOK 0x0080
|
||||
#define XM_RXCMD_LENERROK 0x0100
|
||||
|
||||
#define XM_GPIO_GP0_SET 0x0001
|
||||
#define XM_GPIO_RESETSTATS 0x0004
|
||||
#define XM_GPIO_RESETMAC 0x0008
|
||||
#define XM_GPIO_FORCEINT 0x0020
|
||||
#define XM_GPIO_ANEGINPROG 0x0040
|
||||
|
||||
#define XM_IMR_RX_EOF 0x0001
|
||||
#define XM_IMR_TX_EOF 0x0002
|
||||
#define XM_IMR_TX_UNDERRUN 0x0004
|
||||
#define XM_IMR_RX_OVERRUN 0x0008
|
||||
#define XM_IMR_TX_STATS_OFLOW 0x0010
|
||||
#define XM_IMR_RX_STATS_OFLOW 0x0020
|
||||
#define XM_IMR_TSTAMP_OFLOW 0x0040
|
||||
#define XM_IMR_AUTONEG_DONE 0x0080
|
||||
#define XM_IMR_NEXTPAGE_RDY 0x0100
|
||||
#define XM_IMR_PAGE_RECEIVED 0x0200
|
||||
#define XM_IMR_LP_REQCFG 0x0400
|
||||
#define XM_IMR_GP0_SET 0x0800
|
||||
#define XM_IMR_FORCEINTR 0x1000
|
||||
#define XM_IMR_TX_ABORT 0x2000
|
||||
#define XM_IMR_LINKEVENT 0x4000
|
||||
|
||||
#define XM_INTRS \
|
||||
(~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN))
|
||||
|
||||
#define XM_ISR_RX_EOF 0x0001
|
||||
#define XM_ISR_TX_EOF 0x0002
|
||||
#define XM_ISR_TX_UNDERRUN 0x0004
|
||||
#define XM_ISR_RX_OVERRUN 0x0008
|
||||
#define XM_ISR_TX_STATS_OFLOW 0x0010
|
||||
#define XM_ISR_RX_STATS_OFLOW 0x0020
|
||||
#define XM_ISR_TSTAMP_OFLOW 0x0040
|
||||
#define XM_ISR_AUTONEG_DONE 0x0080
|
||||
#define XM_ISR_NEXTPAGE_RDY 0x0100
|
||||
#define XM_ISR_PAGE_RECEIVED 0x0200
|
||||
#define XM_ISR_LP_REQCFG 0x0400
|
||||
#define XM_ISR_GP0_SET 0x0800
|
||||
#define XM_ISR_FORCEINTR 0x1000
|
||||
#define XM_ISR_TX_ABORT 0x2000
|
||||
#define XM_ISR_LINKEVENT 0x4000
|
||||
|
||||
#define XM_HWCFG_GENEOP 0x0008
|
||||
#define XM_HWCFG_SIGSTATCKH 0x0004
|
||||
#define XM_HWCFG_GMIIMODE 0x0001
|
||||
|
||||
#define XM_MODE_FLUSH_RXFIFO 0x00000001
|
||||
#define XM_MODE_FLUSH_TXFIFO 0x00000002
|
||||
#define XM_MODE_BIGENDIAN 0x00000004
|
||||
#define XM_MODE_RX_PROMISC 0x00000008
|
||||
#define XM_MODE_RX_NOBROAD 0x00000010
|
||||
#define XM_MODE_RX_NOMULTI 0x00000020
|
||||
#define XM_MODE_RX_NOUNI 0x00000040
|
||||
#define XM_MODE_RX_BADFRAMES 0x00000080
|
||||
#define XM_MODE_RX_CRCERRS 0x00000100
|
||||
#define XM_MODE_RX_GIANTS 0x00000200
|
||||
#define XM_MODE_RX_INRANGELEN 0x00000400
|
||||
#define XM_MODE_RX_RUNTS 0x00000800
|
||||
#define XM_MODE_RX_MACCTL 0x00001000
|
||||
#define XM_MODE_RX_USE_PERFECT 0x00002000
|
||||
#define XM_MODE_RX_USE_STATION 0x00004000
|
||||
#define XM_MODE_RX_USE_HASH 0x00008000
|
||||
#define XM_MODE_RX_ADDRPAIR 0x00010000
|
||||
#define XM_MODE_PAUSEONHI 0x00020000
|
||||
#define XM_MODE_PAUSEONLO 0x00040000
|
||||
#define XM_MODE_TIMESTAMP 0x00080000
|
||||
#define XM_MODE_SENDPAUSE 0x00100000
|
||||
#define XM_MODE_SENDCONTINUOUS 0x00200000
|
||||
#define XM_MODE_LE_STATUSWORD 0x00400000
|
||||
#define XM_MODE_AUTOFIFOPAUSE 0x00800000
|
||||
#define XM_MODE_EXPAUSEGEN 0x02000000
|
||||
#define XM_MODE_RX_INVERSE 0x04000000
|
||||
|
||||
#define XM_RXSTAT_MACCTL 0x00000001
|
||||
#define XM_RXSTAT_ERRFRAME 0x00000002
|
||||
#define XM_RXSTAT_CRCERR 0x00000004
|
||||
#define XM_RXSTAT_GIANT 0x00000008
|
||||
#define XM_RXSTAT_RUNT 0x00000010
|
||||
#define XM_RXSTAT_FRAMEERR 0x00000020
|
||||
#define XM_RXSTAT_INRANGEERR 0x00000040
|
||||
#define XM_RXSTAT_CARRIERERR 0x00000080
|
||||
#define XM_RXSTAT_COLLERR 0x00000100
|
||||
#define XM_RXSTAT_802_3 0x00000200
|
||||
#define XM_RXSTAT_CARREXTERR 0x00000400
|
||||
#define XM_RXSTAT_BURSTMODE 0x00000800
|
||||
#define XM_RXSTAT_UNICAST 0x00002000
|
||||
#define XM_RXSTAT_MULTICAST 0x00004000
|
||||
#define XM_RXSTAT_BROADCAST 0x00008000
|
||||
#define XM_RXSTAT_VLAN_LEV1 0x00010000
|
||||
#define XM_RXSTAT_VLAN_LEV2 0x00020000
|
||||
#define XM_RXSTAT_LEN 0xFFFC0000
|
||||
|
||||
/*
|
||||
* XMAC PHY registers, indirectly accessed through
|
||||
* XM_PHY_ADDR and XM_PHY_REG.
|
||||
*/
|
||||
|
||||
#define XM_PHY_BMCR 0x0000 /* control */
|
||||
#define XM_PHY_BMSR 0x0001 /* status */
|
||||
#define XM_PHY_VENID 0x0002 /* vendor id */
|
||||
#define XM_PHY_DEVID 0x0003 /* device id */
|
||||
#define XM_PHY_ANAR 0x0004 /* autoneg advertisenemt */
|
||||
#define XM_PHY_LPAR 0x0005 /* link partner ability */
|
||||
#define XM_PHY_ANEXP 0x0006 /* autoneg expansion */
|
||||
#define XM_PHY_NEXTP 0x0007 /* nextpage */
|
||||
#define XM_PHY_LPNEXTP 0x0008 /* link partner's nextpage */
|
||||
#define XM_PHY_EXTSTS 0x000F /* extented status */
|
||||
#define XM_PHY_RESAB 0x0010 /* resolved ability */
|
||||
|
||||
#define XM_BMCR_DUPLEX 0x0100
|
||||
#define XM_BMCR_RENEGOTIATE 0x0200
|
||||
#define XM_BMCR_AUTONEGENBL 0x1000
|
||||
#define XM_BMCR_LOOPBACK 0x4000
|
||||
#define XM_BMCR_RESET 0x8000
|
||||
|
||||
#define XM_BMSR_EXTCAP 0x0001
|
||||
#define XM_BMSR_LINKSTAT 0x0004
|
||||
#define XM_BMSR_AUTONEGABLE 0x0008
|
||||
#define XM_BMSR_REMFAULT 0x0010
|
||||
#define XM_BMSR_AUTONEGDONE 0x0020
|
||||
#define XM_BMSR_EXTSTAT 0x0100
|
||||
|
||||
#define XM_VENID_XAQTI 0xD14C
|
||||
#define XM_DEVID_XMAC 0x0002
|
||||
|
||||
#define XM_ANAR_FULLDUPLEX 0x0020
|
||||
#define XM_ANAR_HALFDUPLEX 0x0040
|
||||
#define XM_ANAR_PAUSEBITS 0x0180
|
||||
#define XM_ANAR_REMFAULTBITS 0x1800
|
||||
#define XM_ANAR_ACK 0x4000
|
||||
#define XM_ANAR_NEXTPAGE 0x8000
|
||||
|
||||
#define XM_LPAR_FULLDUPLEX 0x0020
|
||||
#define XM_LPAR_HALFDUPLEX 0x0040
|
||||
#define XM_LPAR_PAUSEBITS 0x0180
|
||||
#define XM_LPAR_REMFAULTBITS 0x1800
|
||||
#define XM_LPAR_ACK 0x4000
|
||||
#define XM_LPAR_NEXTPAGE 0x8000
|
||||
|
||||
#define XM_PAUSE_NOPAUSE 0x0000
|
||||
#define XM_PAUSE_SYMPAUSE 0x0080
|
||||
#define XM_PAUSE_ASYMPAUSE 0x0100
|
||||
#define XM_PAUSE_BOTH 0x0180
|
||||
|
||||
#define XM_REMFAULT_LINKOK 0x0000
|
||||
#define XM_REMFAULT_LINKFAIL 0x0800
|
||||
#define XM_REMFAULT_OFFLINE 0x1000
|
||||
#define XM_REMFAULT_ANEGERR 0x1800
|
||||
|
||||
#define XM_ANEXP_GOTPAGE 0x0002
|
||||
#define XM_ANEXP_NEXTPAGE_SELF 0x0004
|
||||
#define XM_ANEXP_NEXTPAGE_LP 0x0008
|
||||
|
||||
#define XM_NEXTP_MESSAGE 0x07FF
|
||||
#define XM_NEXTP_TOGGLE 0x0800
|
||||
#define XM_NEXTP_ACK2 0x1000
|
||||
#define XM_NEXTP_MPAGE 0x2000
|
||||
#define XM_NEXTP_ACK1 0x4000
|
||||
#define XM_NEXTP_NPAGE 0x8000
|
||||
|
||||
#define XM_LPNEXTP_MESSAGE 0x07FF
|
||||
#define XM_LPNEXTP_TOGGLE 0x0800
|
||||
#define XM_LPNEXTP_ACK2 0x1000
|
||||
#define XM_LPNEXTP_MPAGE 0x2000
|
||||
#define XM_LPNEXTP_ACK1 0x4000
|
||||
#define XM_LPNEXTP_NPAGE 0x8000
|
||||
|
||||
#define XM_EXTSTS_HALFDUPLEX 0x4000
|
||||
#define XM_EXTSTS_FULLDUPLEX 0x8000
|
||||
|
||||
#define XM_RESAB_PAUSEMISMATCH 0x0008
|
||||
#define XM_RESAB_ABLMISMATCH 0x0010
|
||||
#define XM_RESAB_FDMODESEL 0x0020
|
||||
#define XM_RESAB_HDMODESEL 0x0040
|
||||
#define XM_RESAB_PAUSEBITS 0x0180
|
||||
@ -1,171 +0,0 @@
|
||||
/* $OpenBSD: yukonreg.h,v 1.2 2003/08/12 05:23:06 nate Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* General Purpose Status Register (GPSR) */
|
||||
#define YUKON_GPSR 0x0000
|
||||
|
||||
#define YU_GPSR_SPEED 0x8000 /* speed 0 - 10Mbps, 1 - 100Mbps */
|
||||
#define YU_GPSR_DUPLEX 0x4000 /* 0 - half duplex, 1 - full duplex */
|
||||
#define YU_GPSR_FCTL_TX 0x2000 /* flow control */
|
||||
#define YU_GPSR_LINK 0x1000 /* link status (down/up) */
|
||||
#define YU_GPSR_PAUSE 0x0800 /* flow control enable/disable */
|
||||
#define YU_GPSR_TX_IN_PROG 0x0400 /* transmit in progress */
|
||||
#define YU_GPSR_EXCESS_COL 0x0200 /* excessive collisions occurred */
|
||||
#define YU_GPSR_LATE_COL 0x0100 /* late collision occurred */
|
||||
#define YU_GPSR_MII_PHY_STC 0x0020 /* MII PHY status change */
|
||||
#define YU_GPSR_GIG_SPEED 0x0010 /* Gigabit Speed (0 - use speed bit) */
|
||||
#define YU_GPSR_PARTITION 0x0008 /* partition mode */
|
||||
#define YU_GPSR_FCTL_RX 0x0004 /* flow control enable/disable */
|
||||
#define YU_GPSR_PROMS_EN 0x0002 /* promiscuous mode enable/disable */
|
||||
|
||||
/* General Purpose Control Register (GPCR) */
|
||||
#define YUKON_GPCR 0x0004
|
||||
|
||||
#define YU_GPCR_FCTL_TX 0x2000 /* Transmit flow control 802.3x */
|
||||
#define YU_GPCR_TXEN 0x1000 /* Transmit Enable */
|
||||
#define YU_GPCR_RXEN 0x0800 /* Receive Enable */
|
||||
#define YU_GPCR_LPBK 0x0200 /* Loopback Enable */
|
||||
#define YU_GPCR_PAR 0x0100 /* Partition Enable */
|
||||
#define YU_GPCR_GIG 0x0080 /* Gigabit Speed */
|
||||
#define YU_GPCR_FLP 0x0040 /* Force Link Pass */
|
||||
#define YU_GPCR_DUPLEX 0x0020 /* Duplex Enable */
|
||||
#define YU_GPCR_FCTL_RX 0x0010 /* Receive flow control 802.3x */
|
||||
#define YU_GPCR_SPEED 0x0008 /* Port Speed */
|
||||
#define YU_GPCR_DPLX_EN 0x0004 /* Enable Auto-Update for duplex */
|
||||
#define YU_GPCR_FCTL_EN 0x0002 /* Enabel Auto-Update for 802.3x */
|
||||
#define YU_GPCR_SPEED_EN 0x0001 /* Enable Auto-Update for speed */
|
||||
|
||||
/* Transmit Control Register (TCR) */
|
||||
#define YUKON_TCR 0x0008
|
||||
|
||||
#define YU_TCR_FJ 0x8000 /* force jam / flow control */
|
||||
#define YU_TCR_CRCD 0x4000 /* insert CRC (0 - enable) */
|
||||
#define YU_TCR_PADD 0x2000 /* pad packets to 64b (0 - enable) */
|
||||
#define YU_TCR_COLTH 0x1c00 /* collision threshold */
|
||||
|
||||
/* Receive Control Register (RCR) */
|
||||
#define YUKON_RCR 0x000c
|
||||
|
||||
#define YU_RCR_UFLEN 0x8000 /* unicast filter enable */
|
||||
#define YU_RCR_MUFLEN 0x4000 /* multicast filter enable */
|
||||
#define YU_RCR_CRCR 0x2000 /* remove CRC */
|
||||
#define YU_RCR_PASSFC 0x1000 /* pass flow control packets */
|
||||
|
||||
/* Transmit Flow Control Register (TFCR) */
|
||||
#define YUKON_TFCR 0x0010 /* Pause Time */
|
||||
|
||||
/* Transmit Parameter Register (TPR) */
|
||||
#define YUKON_TPR 0x0014
|
||||
|
||||
#define YU_TPR_JAM_LEN(x) (((x) & 0x3) << 14)
|
||||
#define YU_TPR_JAM_IPG(x) (((x) & 0x1f) << 9)
|
||||
#define YU_TPR_JAM2DATA_IPG(x) (((x) & 0x1f) << 4)
|
||||
|
||||
/* Serial Mode Register (SMR) */
|
||||
#define YUKON_SMR 0x0018
|
||||
|
||||
#define YU_SMR_DATA_BLIND(x) (((x) & 0x1f) << 11)
|
||||
#define YU_SMR_LIMIT4 0x0400 /* reset after 16 / 4 collisions */
|
||||
#define YU_SMR_MFL_JUMBO 0x0100 /* max frame length for jumbo frames */
|
||||
#define YU_SMR_MFL_VLAN 0x0200 /* max frame length + vlan tag */
|
||||
#define YU_SMR_IPG_DATA(x) ((x) & 0x1f)
|
||||
|
||||
/* Source Address Low #1 (SAL1) */
|
||||
#define YUKON_SAL1 0x001c /* SA1[15:0] */
|
||||
|
||||
/* Source Address Middle #1 (SAM1) */
|
||||
#define YUKON_SAM1 0x0020 /* SA1[31:16] */
|
||||
|
||||
/* Source Address High #1 (SAH1) */
|
||||
#define YUKON_SAH1 0x0024 /* SA1[47:32] */
|
||||
|
||||
/* Source Address Low #2 (SAL2) */
|
||||
#define YUKON_SAL2 0x0028 /* SA2[15:0] */
|
||||
|
||||
/* Source Address Middle #2 (SAM2) */
|
||||
#define YUKON_SAM2 0x002c /* SA2[31:16] */
|
||||
|
||||
/* Source Address High #2 (SAH2) */
|
||||
#define YUKON_SAH2 0x0030 /* SA2[47:32] */
|
||||
|
||||
/* Multicatst Address Hash Register 1 (MCAH1) */
|
||||
#define YUKON_MCAH1 0x0034
|
||||
|
||||
/* Multicatst Address Hash Register 2 (MCAH2) */
|
||||
#define YUKON_MCAH2 0x0038
|
||||
|
||||
/* Multicatst Address Hash Register 3 (MCAH3) */
|
||||
#define YUKON_MCAH3 0x003c
|
||||
|
||||
/* Multicatst Address Hash Register 4 (MCAH4) */
|
||||
#define YUKON_MCAH4 0x0040
|
||||
|
||||
/* Transmit Interrupt Register (TIR) */
|
||||
#define YUKON_TIR 0x0044
|
||||
|
||||
#define YU_TIR_OUT_UNICAST 0x0001 /* Num Unicast Packets Transmitted */
|
||||
#define YU_TIR_OUT_BROADCAST 0x0002 /* Num Broadcast Packets Transmitted */
|
||||
#define YU_TIR_OUT_PAUSE 0x0004 /* Num Pause Packets Transmitted */
|
||||
#define YU_TIR_OUT_MULTICAST 0x0008 /* Num Multicast Packets Transmitted */
|
||||
#define YU_TIR_OUT_OCTETS 0x0030 /* Num Bytes Transmitted */
|
||||
#define YU_TIR_OUT_64_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_127_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_255_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_511_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_1023_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_1518_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_MAX_OCTETS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_SPARE 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_COLLISIONS 0x0000 /* Num Packets Transmitted */
|
||||
#define YU_TIR_OUT_LATE 0x0000 /* Num Packets Transmitted */
|
||||
|
||||
/* Receive Interrupt Register (RIR) */
|
||||
#define YUKON_RIR 0x0048
|
||||
|
||||
/* Transmit and Receive Interrupt Register (TRIR) */
|
||||
#define YUKON_TRIR 0x004c
|
||||
|
||||
/* Transmit Interrupt Mask Register (TIMR) */
|
||||
#define YUKON_TIMR 0x0050
|
||||
|
||||
/* Receive Interrupt Mask Register (RIMR) */
|
||||
#define YUKON_RIMR 0x0054
|
||||
|
||||
/* Transmit and Receive Interrupt Mask Register (TRIMR) */
|
||||
#define YUKON_TRIMR 0x0058
|
||||
|
||||
/* SMI Control Register (SMICR) */
|
||||
#define YUKON_SMICR 0x0080
|
||||
|
||||
#define YU_SMICR_PHYAD(x) (((x) & 0x1f) << 11)
|
||||
#define YU_SMICR_REGAD(x) (((x) & 0x1f) << 6)
|
||||
#define YU_SMICR_OPCODE 0x0020 /* opcode (0 - write, 1 - read) */
|
||||
#define YU_SMICR_OP_READ 0x0020 /* opcode read */
|
||||
#define YU_SMICR_OP_WRITE 0x0000 /* opcode write */
|
||||
#define YU_SMICR_READ_VALID 0x0010 /* read valid */
|
||||
#define YU_SMICR_BUSY 0x0008 /* busy (writing) */
|
||||
|
||||
/* SMI Data Register (SMIDR) */
|
||||
#define YUKON_SMIDR 0x0084
|
||||
|
||||
/* PHY Addres Register (PAR) */
|
||||
#define YUKON_PAR 0x0088
|
||||
|
||||
#define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */
|
||||
#define YU_PAR_LOAD_TSTCNT 0x0010 /* Load count 0xfffffff0 into cntr */
|
||||
Loading…
Reference in New Issue
Block a user