Add hardware MAC statistics support. Also added some reserved
statistics register definition. Users can get current MAC statistics from dev.msk.%d.stats sysctl node(%d is unit number of a device).
This commit is contained in:
Pyun YongHyeon
parent
ff036ed64f
commit
3a91ee716b
@ -291,6 +291,11 @@ static void msk_setmulti(struct msk_if_softc *);
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static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
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static void msk_setpromisc(struct msk_if_softc *);
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static void msk_stats_clear(struct msk_if_softc *);
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static void msk_stats_update(struct msk_if_softc *);
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static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
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static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
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static void msk_sysctl_node(struct msk_if_softc *);
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static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
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static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
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@ -1435,6 +1440,7 @@ msk_attach(device_t dev)
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callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
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TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if);
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msk_sysctl_node(sc_if);
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/* Disable jumbo frame for Yukon FE. */
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if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE)
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@ -3544,15 +3550,8 @@ msk_init_locked(struct msk_if_softc *sc_if)
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/* Dummy read the Interrupt Source Register. */
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CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
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/* Set MIB Clear Counter Mode. */
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gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
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/* Read all MIB Counters with Clear Mode set. */
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for (i = 0; i < GM_MIB_CNT_SIZE; i++)
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GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i);
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/* Clear MIB Clear Counter Mode. */
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gmac &= ~GM_PAR_MIB_CLR;
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
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/* Clear MIB stats. */
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msk_stats_clear(sc_if);
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/* Disable FCS. */
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
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@ -3838,6 +3837,8 @@ msk_stop(struct msk_if_softc *sc_if)
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
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/* Read again to ensure writing. */
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GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
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/* Update stats and clear counters. */
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msk_stats_update(sc_if);
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/* Stop Tx BMU. */
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CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
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@ -3953,6 +3954,295 @@ msk_stop(struct msk_if_softc *sc_if)
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sc_if->msk_link = 0;
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}
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/*
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* When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
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* counter clears high 16 bits of the counter such that accessing
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* lower 16 bits should be the last operation.
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*/
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#define MSK_READ_MIB32(x, y) \
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(((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \
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(uint32_t)GMAC_READ_2(sc, x, y)
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#define MSK_READ_MIB64(x, y) \
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(((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \
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(uint64_t)MSK_READ_MIB32(x, y)
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static void
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msk_stats_clear(struct msk_if_softc *sc_if)
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{
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struct msk_softc *sc;
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uint32_t reg;
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uint16_t gmac;
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int i;
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MSK_IF_LOCK_ASSERT(sc_if);
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sc = sc_if->msk_softc;
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/* Set MIB Clear Counter Mode. */
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gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
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/* Read all MIB Counters with Clear Mode set. */
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for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i++)
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reg = MSK_READ_MIB32(sc_if->msk_port, i);
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/* Clear MIB Clear Counter Mode. */
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gmac &= ~GM_PAR_MIB_CLR;
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
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}
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static void
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msk_stats_update(struct msk_if_softc *sc_if)
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{
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struct msk_softc *sc;
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struct ifnet *ifp;
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struct msk_hw_stats *stats;
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uint16_t gmac;
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uint32_t reg;
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MSK_IF_LOCK_ASSERT(sc_if);
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ifp = sc_if->msk_ifp;
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if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
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return;
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sc = sc_if->msk_softc;
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stats = &sc_if->msk_stats;
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/* Set MIB Clear Counter Mode. */
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gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
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/* Rx stats. */
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stats->rx_ucast_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
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stats->rx_bcast_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
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stats->rx_pause_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
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stats->rx_mcast_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
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stats->rx_crc_errs +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
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reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1);
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stats->rx_good_octets +=
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MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
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stats->rx_bad_octets +=
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MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
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stats->rx_runts +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
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stats->rx_runt_errs +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
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stats->rx_pkts_64 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
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stats->rx_pkts_65_127 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
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stats->rx_pkts_128_255 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
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stats->rx_pkts_256_511 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
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stats->rx_pkts_512_1023 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
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stats->rx_pkts_1024_1518 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
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stats->rx_pkts_1519_max +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
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stats->rx_pkts_too_long +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
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stats->rx_pkts_jabbers +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
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reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2);
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stats->rx_fifo_oflows +=
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MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
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reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3);
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/* Tx stats. */
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stats->tx_ucast_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
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stats->tx_bcast_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
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stats->tx_pause_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
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stats->tx_mcast_frames +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
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stats->tx_octets +=
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MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
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stats->tx_pkts_64 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
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stats->tx_pkts_65_127 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
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stats->tx_pkts_128_255 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
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stats->tx_pkts_256_511 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
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stats->tx_pkts_512_1023 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
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stats->tx_pkts_1024_1518 +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
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stats->tx_pkts_1519_max +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
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reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1);
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stats->tx_colls +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
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stats->tx_late_colls +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
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stats->tx_excess_colls +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
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stats->tx_multi_colls +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
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stats->tx_single_colls +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
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stats->tx_underflows +=
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MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
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/* Clear MIB Clear Counter Mode. */
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gmac &= ~GM_PAR_MIB_CLR;
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GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
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}
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static int
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msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
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{
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struct msk_softc *sc;
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struct msk_if_softc *sc_if;
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uint32_t result, *stat;
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int off;
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sc_if = (struct msk_if_softc *)arg1;
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sc = sc_if->msk_softc;
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off = arg2;
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stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
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MSK_IF_LOCK(sc_if);
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result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
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result += *stat;
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MSK_IF_UNLOCK(sc_if);
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return (sysctl_handle_int(oidp, &result, 0, req));
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}
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static int
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msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
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{
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struct msk_softc *sc;
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struct msk_if_softc *sc_if;
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uint64_t result, *stat;
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int off;
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sc_if = (struct msk_if_softc *)arg1;
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sc = sc_if->msk_softc;
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off = arg2;
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stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
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MSK_IF_LOCK(sc_if);
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result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
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result += *stat;
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MSK_IF_UNLOCK(sc_if);
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return (sysctl_handle_quad(oidp, &result, 0, req));
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}
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#undef MSK_READ_MIB32
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#undef MSK_READ_MIB64
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#define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \
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SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \
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sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \
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"IU", d)
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#define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \
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SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \
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sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \
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"Q", d)
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static void
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msk_sysctl_node(struct msk_if_softc *sc_if)
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{
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid_list *child, *schild;
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struct sysctl_oid *tree;
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ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
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child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
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tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
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NULL, "MSK Statistics");
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schild = child = SYSCTL_CHILDREN(tree);
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tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
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NULL, "MSK RX Statistics");
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child = SYSCTL_CHILDREN(tree);
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MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
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child, rx_ucast_frames, "Good unicast frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
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child, rx_bcast_frames, "Good broadcast frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
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child, rx_pause_frames, "Pause frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
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child, rx_mcast_frames, "Multicast frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
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child, rx_crc_errs, "CRC errors");
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MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
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child, rx_good_octets, "Good octets");
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MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
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child, rx_bad_octets, "Bad octets");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
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child, rx_pkts_64, "64 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
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child, rx_pkts_65_127, "65 to 127 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
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child, rx_pkts_128_255, "128 to 255 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
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child, rx_pkts_256_511, "256 to 511 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
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child, rx_pkts_512_1023, "512 to 1023 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
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child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
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child, rx_pkts_1519_max, "1519 to max frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
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child, rx_pkts_too_long, "frames too long");
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MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
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child, rx_pkts_jabbers, "Jabber errors");
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MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
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child, rx_fifo_oflows, "FIFO overflows");
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tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
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NULL, "MSK TX Statistics");
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child = SYSCTL_CHILDREN(tree);
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MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
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child, tx_ucast_frames, "Unicast frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
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child, tx_bcast_frames, "Broadcast frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
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child, tx_pause_frames, "Pause frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
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child, tx_mcast_frames, "Multicast frames");
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MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
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child, tx_octets, "Octets");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
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child, tx_pkts_64, "64 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
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child, tx_pkts_65_127, "65 to 127 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
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child, tx_pkts_128_255, "128 to 255 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
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child, tx_pkts_256_511, "256 to 511 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
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child, tx_pkts_512_1023, "512 to 1023 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
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child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
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child, tx_pkts_1519_max, "1519 to max frames");
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MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
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child, tx_colls, "Collisions");
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MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
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child, tx_late_colls, "Late collisions");
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MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
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child, tx_excess_colls, "Excessive collisions");
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MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
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child, tx_multi_colls, "Multiple collisions");
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MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
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child, tx_single_colls, "Single collisions");
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MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
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child, tx_underflows, "FIFO underflows");
|
||||
}
|
||||
|
||||
#undef MSK_SYSCTL_STAT32
|
||||
#undef MSK_SYSCTL_STAT64
|
||||
|
||||
static int
|
||||
sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
|
||||
{
|
||||
|
||||
@ -1614,6 +1614,8 @@
|
||||
(GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */
|
||||
#define GM_RXF_FCS_ERR \
|
||||
(GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
|
||||
#define GM_RXF_SPARE1 \
|
||||
(GM_MIB_CNT_BASE + 40) /* Rx spare 1 */
|
||||
#define GM_RXO_OK_LO \
|
||||
(GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */
|
||||
#define GM_RXO_OK_HI \
|
||||
@ -1644,8 +1646,12 @@
|
||||
(GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
|
||||
#define GM_RXF_JAB_PKT \
|
||||
(GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
|
||||
#define GM_RXF_SPARE2 \
|
||||
(GM_MIB_CNT_BASE + 168) /* Rx spare 2 */
|
||||
#define GM_RXE_FIFO_OV \
|
||||
(GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
|
||||
#define GM_RXF_SPARE3 \
|
||||
(GM_MIB_CNT_BASE + 184) /* Rx spare 3 */
|
||||
#define GM_TXF_UC_OK \
|
||||
(GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */
|
||||
#define GM_TXF_BC_OK \
|
||||
@ -1672,6 +1678,8 @@
|
||||
(GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
|
||||
#define GM_TXF_MAX_SZ \
|
||||
(GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
|
||||
#define GM_TXF_SPARE1 \
|
||||
(GM_MIB_CNT_BASE + 296) /* Tx spare 1 */
|
||||
#define GM_TXF_COL \
|
||||
(GM_MIB_CNT_BASE + 304) /* Tx Collision */
|
||||
#define GM_TXF_LAT_COL \
|
||||
@ -2270,6 +2278,52 @@ struct msk_ring_data {
|
||||
/* Forward decl. */
|
||||
struct msk_if_softc;
|
||||
|
||||
struct msk_hw_stats {
|
||||
/* Rx stats. */
|
||||
uint32_t rx_ucast_frames;
|
||||
uint32_t rx_bcast_frames;
|
||||
uint32_t rx_pause_frames;
|
||||
uint32_t rx_mcast_frames;
|
||||
uint32_t rx_crc_errs;
|
||||
uint32_t rx_spare1;
|
||||
uint64_t rx_good_octets;
|
||||
uint64_t rx_bad_octets;
|
||||
uint32_t rx_runts;
|
||||
uint32_t rx_runt_errs;
|
||||
uint32_t rx_pkts_64;
|
||||
uint32_t rx_pkts_65_127;
|
||||
uint32_t rx_pkts_128_255;
|
||||
uint32_t rx_pkts_256_511;
|
||||
uint32_t rx_pkts_512_1023;
|
||||
uint32_t rx_pkts_1024_1518;
|
||||
uint32_t rx_pkts_1519_max;
|
||||
uint32_t rx_pkts_too_long;
|
||||
uint32_t rx_pkts_jabbers;
|
||||
uint32_t rx_spare2;
|
||||
uint32_t rx_fifo_oflows;
|
||||
uint32_t rx_spare3;
|
||||
/* Tx stats. */
|
||||
uint32_t tx_ucast_frames;
|
||||
uint32_t tx_bcast_frames;
|
||||
uint32_t tx_pause_frames;
|
||||
uint32_t tx_mcast_frames;
|
||||
uint64_t tx_octets;
|
||||
uint32_t tx_pkts_64;
|
||||
uint32_t tx_pkts_65_127;
|
||||
uint32_t tx_pkts_128_255;
|
||||
uint32_t tx_pkts_256_511;
|
||||
uint32_t tx_pkts_512_1023;
|
||||
uint32_t tx_pkts_1024_1518;
|
||||
uint32_t tx_pkts_1519_max;
|
||||
uint32_t tx_spare1;
|
||||
uint32_t tx_colls;
|
||||
uint32_t tx_late_colls;
|
||||
uint32_t tx_excess_colls;
|
||||
uint32_t tx_multi_colls;
|
||||
uint32_t tx_single_colls;
|
||||
uint32_t tx_underflows;
|
||||
};
|
||||
|
||||
/* Softc for the Marvell Yukon II controller. */
|
||||
struct msk_softc {
|
||||
struct resource *msk_res[1]; /* I/O resource */
|
||||
@ -2340,6 +2394,7 @@ struct msk_if_softc {
|
||||
struct msk_chain_data msk_cdata;
|
||||
struct msk_ring_data msk_rdata;
|
||||
struct msk_softc *msk_softc; /* parent controller */
|
||||
struct msk_hw_stats msk_stats;
|
||||
struct task msk_link_task;
|
||||
struct task msk_tx_task;
|
||||
int msk_if_flags;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user