From 3a97344265b4319c4ecd8d3f86e0ff7925b106c8 Mon Sep 17 00:00:00 2001 From: Alexander Motin Date: Sun, 15 Sep 2019 23:56:39 +0000 Subject: [PATCH] Relax TX draining in ns8250_bus_transmit(). Since TX interrupt is generated when THRE is set, wait for TEMT set means wait for full character transmission time. At low speeds that may take awhile, burning CPU time while holding sc_hwmtx lock, also congested. This is partial revert of r317659. PR: 240121 MFC after: 2 weeks --- sys/dev/uart/uart_dev_ns8250.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c index be883185aac2..4460a2d029b3 100644 --- a/sys/dev/uart/uart_dev_ns8250.c +++ b/sys/dev/uart/uart_dev_ns8250.c @@ -1029,13 +1029,8 @@ ns8250_bus_transmit(struct uart_softc *sc) bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - if (sc->sc_txdatasz > 1) { - if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) - ns8250_drain(bas, UART_DRAIN_TRANSMITTER); - } else { - while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) - DELAY(4); - } + while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) + DELAY(4); for (i = 0; i < sc->sc_txdatasz; i++) { uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); uart_barrier(bas);