Use generic MII #defines instead of private ones when the registers
are IEEE defined. Object file comes out the same.
This commit is contained in:
Poul-Henning Kamp
parent
1aad4b2a52
commit
3aae18bde8
@ -100,8 +100,8 @@ static void nsgphy_status(struct mii_softc *);
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static int nsgphy_mii_phy_auto(struct mii_softc *, int);
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extern void mii_phy_auto_timeout(void *);
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static int nsgphy_probe(dev)
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device_t dev;
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static int
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nsgphy_probe(device_t dev)
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{
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struct mii_attach_args *ma;
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@ -121,8 +121,8 @@ static int nsgphy_probe(dev)
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return(ENXIO);
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}
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static int nsgphy_attach(dev)
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device_t dev;
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static int
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nsgphy_attach(device_t dev)
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{
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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@ -157,23 +157,23 @@ static int nsgphy_attach(dev)
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device_printf(dev, " ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst),
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NSGPHY_S1000|NSGPHY_BMCR_FDX);
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BMCR_S1000|BMCR_FDX);
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PRINT("1000baseTX-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst),
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NSGPHY_S1000);
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BMCR_S1000);
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PRINT("1000baseTX");
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sc->mii_capabilities =
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(PHY_READ(sc, MII_BMSR) |
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(BMSR_10TFDX|BMSR_10THDX)) & ma->mii_capmask;
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
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NSGPHY_S100|NSGPHY_BMCR_FDX);
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BMCR_S100|BMCR_FDX);
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PRINT("100baseTX-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), NSGPHY_S100);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), BMCR_S100);
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PRINT("100baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
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NSGPHY_S10|NSGPHY_BMCR_FDX);
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BMCR_S10|BMCR_FDX);
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PRINT("10baseT-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), NSGPHY_S10);
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), BMCR_S10);
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PRINT("10baseT");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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PRINT("auto");
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@ -185,8 +185,8 @@ static int nsgphy_attach(dev)
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return(0);
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}
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static int nsgphy_detach(dev)
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device_t dev;
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static int
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nsgphy_detach(device_t dev)
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{
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struct mii_softc *sc;
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struct mii_data *mii;
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@ -200,11 +200,9 @@ static int nsgphy_detach(dev)
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return(0);
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}
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int
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nsgphy_service(sc, mii, cmd)
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struct mii_softc *sc;
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struct mii_data *mii;
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int cmd;
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static int
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nsgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg;
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@ -242,20 +240,20 @@ nsgphy_service(sc, mii, cmd)
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, NSGPHY_MII_BMCR) & NSGPHY_BMCR_AUTOEN)
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if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
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return (0);
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#endif
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(void) nsgphy_mii_phy_auto(sc, 0);
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break;
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case IFM_1000_TX:
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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PHY_WRITE(sc, NSGPHY_MII_BMCR,
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NSGPHY_BMCR_FDX|NSGPHY_BMCR_SPD1);
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PHY_WRITE(sc, MII_BMCR,
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BMCR_FDX|BMCR_SPEED1);
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} else {
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PHY_WRITE(sc, NSGPHY_MII_BMCR,
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NSGPHY_BMCR_SPD1);
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PHY_WRITE(sc, MII_BMCR,
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BMCR_SPEED1);
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}
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PHY_WRITE(sc, NSGPHY_MII_ANAR, NSGPHY_SEL_TYPE);
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PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
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/*
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* When setting the link manually, one side must
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@ -266,11 +264,10 @@ nsgphy_service(sc, mii, cmd)
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, NSGPHY_MII_1000CTL,
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NSGPHY_1000CTL_MSE|NSGPHY_1000CTL_MSC);
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PHY_WRITE(sc, MII_100T2CR,
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GTCR_MAN_MS|GTCR_ADV_MS);
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} else {
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PHY_WRITE(sc, NSGPHY_MII_1000CTL,
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NSGPHY_1000CTL_MSE);
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PHY_WRITE(sc, MII_100T2CR, GTCR_MAN_MS);
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}
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break;
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case IFM_100_T4:
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@ -285,8 +282,7 @@ nsgphy_service(sc, mii, cmd)
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/*
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* BMCR data is stored in the ifmedia entry.
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*/
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PHY_WRITE(sc, MII_ANAR,
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mii_anar(ife->ifm_media));
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PHY_WRITE(sc, MII_ANAR, mii_anar(ife->ifm_media));
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PHY_WRITE(sc, MII_BMCR, ife->ifm_data);
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break;
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}
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@ -344,8 +340,7 @@ nsgphy_service(sc, mii, cmd)
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}
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static void
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nsgphy_status(sc)
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struct mii_softc *sc;
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nsgphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr, physup, anlpar, gstat;
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@ -353,58 +348,64 @@ nsgphy_status(sc)
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, NSGPHY_MII_BMSR);
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bmsr = PHY_READ(sc, MII_BMSR);
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physup = PHY_READ(sc, NSGPHY_MII_PHYSUP);
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if (physup & NSGPHY_PHYSUP_LNKSTS)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, NSGPHY_MII_BMCR);
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bmcr = PHY_READ(sc, MII_BMCR);
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if (bmcr & NSGPHY_BMCR_LOOP)
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if (bmcr & BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & NSGPHY_BMCR_AUTOEN) {
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if ((bmsr & NSGPHY_BMSR_ACOMP) == 0) {
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if (bmcr & BMCR_AUTOEN) {
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/*
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* The media status bits are only valid if autonegotiation
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* has completed (or it's disabled).
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*/
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if ((bmsr & BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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anlpar = PHY_READ(sc, NSGPHY_MII_ANLPAR);
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gstat = PHY_READ(sc, NSGPHY_MII_1000STS);
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if (gstat & NSGPHY_1000STS_LPFD)
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anlpar = PHY_READ(sc, MII_ANLPAR);
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gstat = PHY_READ(sc, MII_100T2SR);
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if (gstat & GTSR_LP_1000TFDX)
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mii->mii_media_active |= IFM_1000_TX|IFM_FDX;
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else if (gstat & NSGPHY_1000STS_LPHD)
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else if (gstat & GTSR_LP_1000THDX)
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mii->mii_media_active |= IFM_1000_TX|IFM_HDX;
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else if (anlpar & NSGPHY_ANLPAR_100T4)
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else if (anlpar & ANLPAR_T4)
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mii->mii_media_active |= IFM_100_T4;
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else if (anlpar & NSGPHY_ANLPAR_100FDX)
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else if (anlpar & ANLPAR_TX_FD)
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mii->mii_media_active |= IFM_100_TX|IFM_FDX;
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else if (anlpar & NSGPHY_ANLPAR_100HDX)
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else if (anlpar & ANLPAR_TX)
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mii->mii_media_active |= IFM_100_TX;
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else if (anlpar & NSGPHY_ANLPAR_10FDX)
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else if (anlpar & ANLPAR_10_FD)
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mii->mii_media_active |= IFM_10_T|IFM_FDX;
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else if (anlpar & NSGPHY_ANLPAR_10HDX)
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else if (anlpar & ANLPAR_10)
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mii->mii_media_active |= IFM_10_T|IFM_HDX;
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else
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch(bmcr & (NSGPHY_BMCR_SPD1|NSGPHY_BMCR_SPD0)) {
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case NSGPHY_S1000:
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switch(bmcr & (BMCR_SPEED1|BMCR_SPEED0)) {
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case BMCR_S1000:
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mii->mii_media_active |= IFM_1000_TX;
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break;
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case NSGPHY_S100:
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case BMCR_S100:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case NSGPHY_S10:
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case BMCR_S10:
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mii->mii_media_active |= IFM_10_T;
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break;
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default:
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break;
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}
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if (bmcr & NSGPHY_BMCR_FDX)
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if (bmcr & BMCR_FDX)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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@ -414,33 +415,30 @@ nsgphy_status(sc)
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static int
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nsgphy_mii_phy_auto(mii, waitfor)
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struct mii_softc *mii;
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int waitfor;
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nsgphy_mii_phy_auto(struct mii_softc *mii, int waitfor)
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{
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int bmsr, ktcr = 0, i;
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if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
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mii_phy_reset(mii);
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PHY_WRITE(mii, NSGPHY_MII_BMCR, 0);
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PHY_WRITE(mii, MII_BMCR, 0);
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DELAY(1000);
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ktcr = PHY_READ(mii, NSGPHY_MII_1000CTL);
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PHY_WRITE(mii, NSGPHY_MII_1000CTL, ktcr |
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(NSGPHY_1000CTL_AFD|NSGPHY_1000CTL_AHD));
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ktcr = PHY_READ(mii, NSGPHY_MII_1000CTL);
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ktcr = PHY_READ(mii, MII_100T2CR);
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PHY_WRITE(mii, MII_100T2CR, ktcr |
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(GTCR_ADV_1000TFDX|GTCR_ADV_1000THDX));
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ktcr = PHY_READ(mii, MII_100T2CR);
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DELAY(1000);
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PHY_WRITE(mii, NSGPHY_MII_ANAR,
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PHY_WRITE(mii, MII_ANAR,
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BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
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DELAY(1000);
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PHY_WRITE(mii, NSGPHY_MII_BMCR,
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NSGPHY_BMCR_AUTOEN | NSGPHY_BMCR_STARTNEG);
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PHY_WRITE(mii, MII_BMCR,
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BMCR_AUTOEN | BMCR_STARTNEG);
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}
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if (waitfor) {
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/* Wait 500ms for it to complete. */
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for (i = 0; i < 500; i++) {
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if ((bmsr = PHY_READ(mii, NSGPHY_MII_BMSR)) &
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NSGPHY_BMSR_ACOMP)
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if ((bmsr = PHY_READ(mii, MII_BMSR)) & BMSR_ACOMP)
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return (0);
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DELAY(1000);
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#if 0
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@ -40,110 +40,6 @@
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* NatSemi DP83891 registers
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*/
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#define NSGPHY_MII_BMCR 0x00
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#define NSGPHY_BMCR_RESET 0x8000
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#define NSGPHY_BMCR_LOOP 0x4000
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#define NSGPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
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#define NSGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
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#define NSGPHY_BMCR_PDOWN 0x0800 /* Power down */
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#define NSGPHY_BMCR_ISO 0x0400 /* Isolate */
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#define NSGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
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#define NSGPHY_BMCR_FDX 0x0100 /* Duplex mode */
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#define NSGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
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#define NSGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
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#define NSGPHY_S1000 NSGPHY_BMCR_SPD1 /* 1000mbps */
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#define NSGPHY_S100 NSGPHY_BMCR_SPD0 /* 100mpbs */
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#define NSGPHY_S10 0 /* 10mbps */
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#define NSGPHY_MII_BMSR 0x01
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#define NSGPHY_BMSR_100BT4 0x8000 /* 100baseT4 support */
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#define NSGPHY_BMSR_100FDX 0x4000 /* 100baseTX full duplex */
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#define NSGPHY_BMSR_100HDX 0x2000 /* 100baseTX half duplex */
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#define NSGPHY_BMSR_10FDX 0x1000 /* 10baseT full duplex */
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#define NSGPHY_BMSR_10HDX 0x0800 /* 10baseT half duplex */
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#define NSGPHY_BMSR_100T2FDX 0x0400 /* 100baseT2 full duplex */
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#define NSGPHY_BMSR_100T2HDX 0x0200 /* 100baseT2 full duplex */
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#define NSGPHY_BMSR_EXTSTS 0x0100 /* 1000baseT Extended status present */
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#define NSGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
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#define NSGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
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#define NSGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
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#define NSGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
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#define NSGPHY_BMSR_LINK 0x0004 /* Link status */
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#define NSGPHY_BMSR_JABBER 0x0002 /* Jabber detected */
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#define NSGPHY_BMSR_EXT 0x0001 /* Extended capability */
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#define NSGPHY_MII_ANAR 0x04
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#define NSGPHY_ANAR_NP 0x8000 /* Next page */
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#define NSGPHY_ANAR_RF 0x2000 /* Remote fault */
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#define NSGPHY_ANAR_ASP 0x0800 /* Asymetric Pause */
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#define NSGPHY_ANAR_PC 0x0400 /* Pause capable */
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#define NSGPHY_ANAR_100T4 0x0200 /* 100baseT4 support */
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#define NSGPHY_ANAR_100FDX 0x0100 /* 100baseTX full duplex support */
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#define NSGPHY_ANAR_100HDX 0x0080 /* 100baseTX half duplex support */
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#define NSGPHY_ANAR_10FDX 0x0040 /* 10baseT full duplex support */
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#define NSGPHY_ANAR_10HDX 0x0020 /* 10baseT half duplex support */
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#define NSGPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
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#define NSGPHY_MII_ANLPAR 0x05
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#define NSGPHY_ANLPAR_NP 0x8000 /* Next page */
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#define NSGPHY_ANLPAR_RF 0x2000 /* Remote fault */
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#define NSGPHY_ANLPAR_ASP 0x0800 /* Asymetric Pause */
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#define NSGPHY_ANLPAR_PC 0x0400 /* Pause capable */
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#define NSGPHY_ANLPAR_100T4 0x0200 /* 100baseT4 support */
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#define NSGPHY_ANLPAR_100FDX 0x0100 /* 100baseTX full duplex support */
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#define NSGPHY_ANLPAR_100HDX 0x0080 /* 100baseTX half duplex support */
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#define NSGPHY_ANLPAR_10FDX 0x0040 /* 10baseT full duplex support */
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#define NSGPHY_ANLPAR_10HDX 0x0020 /* 10baseT half duplex support */
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#define NSGPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
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#define NSGPHY_SEL_TYPE 0x0001 /* ethernet */
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#define NSGPHY_MII_ANER 0x06
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#define NSGPHY_ANER_PDF 0x0010 /* Parallel detection fault */
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#define NSGPHY_ANER_LPNP 0x0008 /* Link partner can next page */
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#define NSGPHY_ANER_NP 0x0004 /* Local PHY can next page */
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#define NSGPHY_ANER_RX 0x0002 /* Next page received */
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#define NSGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
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#define NSGPHY_MII_NEXTP 0x07 /* Next page */
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#define NSGPHY_NEXTP_NP 0x8000 /* Next page indication */
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#define NSGPHY_NEXTP_MP 0x2000 /* Message page */
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#define NSGPHY_NEXTP_ACK2 0x1000 /* Acknowledge 2 */
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#define NSGPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
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#define NSGPHY_NEXTP_CODE 0x07FF /* Code field */
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#define NSGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
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#define NSGPHY_NEXTPLP_NP 0x8000 /* Next page indication */
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#define NSGPHY_NEXTPLP_MP 0x2000 /* Message page */
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#define NSGPHY_NEXTPLP_ACK2 0x1000 /* Acknowledge 2 */
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#define NSGPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
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#define NSGPHY_NEXTPLP_CODE 0x07FF /* Code field */
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#define NSGPHY_MII_1000CTL 0x09 /* 1000baseT control */
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#define NSGPHY_1000CTL_TST 0xE000 /* test modes */
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#define NSGPHY_1000CTL_MSE 0x1000 /* Master/Slave config enable */
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#define NSGPHY_1000CTL_MSC 0x0800 /* Master/Slave setting */
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#define NSGPHY_1000CTL_RD 0x0400 /* Port type: Repeater/DTE */
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#define NSGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
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#define NSGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
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#define NSGPHY_MII_1000STS 0x0A /* 1000baseT status */
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#define NSGPHY_1000STS_MSF 0x8000 /* Master/slave fault */
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#define NSGPHY_1000STS_MSR 0x4000 /* Master/slave result */
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#define NSGPHY_1000STS_LRS 0x2000 /* Local receiver status */
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#define NSGPHY_1000STS_RRS 0x1000 /* Remote receiver status */
|
||||
#define NSGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
|
||||
#define NSGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
|
||||
#define NSGPHY_1000STS_ASM_DIR 0x0200 /* Asymetric pause capable */
|
||||
#define NSGPHY_1000STS_IEC 0x00FF /* Idle error count */
|
||||
|
||||
#define NSGPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define NSGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
|
||||
#define NSGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
|
||||
#define NSGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
|
||||
#define NSGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
|
||||
|
||||
#define NSGPHY_MII_STRAPOPT 0x10 /* Strap options */
|
||||
#define NSGPHY_STRAPOPT_PHYADDR 0xF800 /* PHY address */
|
||||
#define NSGPHY_STRAPOPT_COMPAT 0x0400 /* Broadcom compat mode */
|
||||
@ -153,10 +49,14 @@
|
||||
#define NSGPHY_STRAPOPT_1000HDX 0x0010 /* Advertise 1000 half-duplex */
|
||||
#define NSGPHY_STRAPOPT_1000FDX 0x0008 /* Advertise 1000 full-duplex */
|
||||
#define NSGPHY_STRAPOPT_100_ADV 0x0004 /* Advertise 100 full/half-duplex */
|
||||
#define NSGPHY_STRAPOPT_SPDSEL 0x0003 /* speed selection */
|
||||
#define NSGPHY_STRAPOPT_SPEED1 0x0002 /* speed selection */
|
||||
#define NSGPHY_STRAPOPT_SPEED0 0x0001 /* speed selection */
|
||||
#define NSGPHY_STRAPOPT_SPDSEL (NSGPHY_STRAPOPT_SPEED1|NSGPHY_STRAPOPT_SPEED0)
|
||||
|
||||
#define NSGPHY_MII_PHYSUP 0x11 /* PHY support/current status */
|
||||
#define NSGPHY_PHYSUP_SPDSTS 0x0018 /* speed status */
|
||||
#define NSGPHY_PHYSUP_SPEED1 0x0010 /* speed status */
|
||||
#define NSGPHY_PHYSUP_SPEED0 0x0008 /* speed status */
|
||||
#define NSGPHY_PHYSUP_SPDSTS (NSGPHY_PHYSUP_SPEED1|NSGPHY_PHYSUP_SPEED0)
|
||||
#define NSGPHY_PHYSUP_LNKSTS 0x0004 /* link status */
|
||||
#define NSGPHY_PHYSUP_DUPSTS 0x0002 /* duplex status 1 == full */
|
||||
#define NSGPHY_PHYSUP_10BT 0x0001 /* 10baseT resolved */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user