Provide a single implementation for each of the arm64 atomic(9) ops.
Parameterize the macros by type width as well as acq/rel semantics. This makes modifying the implementations much less tedious and error-prone and makes it easier to support alternate LSE-based implementations. No functional change intended. Reviewed by: andrew, kib MFC after: 1 month Sponsored by: The FreeBSD Foundation, Amazon (hardware) Differential Revision: https://reviews.freebsd.org/D23322
This commit is contained in:
Mark Johnston
parent
62612737d6
commit
3ad6c736cf
@ -59,173 +59,79 @@
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#include <sys/atomic_common.h>
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#define ATOMIC_OP(op, asm_op, bar, a, l) \
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#define _ATOMIC_OP_IMPL(t, w, s, op, asm_op, bar, a, l) \
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static __inline void \
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atomic_##op##_##bar##8(volatile uint8_t *p, uint8_t val) \
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atomic_##op##_##bar##t(volatile uint##t##_t *p, uint##t##_t val) \
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{ \
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uint8_t tmp; \
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uint##t##_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: ld"#a"xrb %w0, [%2] \n" \
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" "#asm_op" %w0, %w0, %w3 \n" \
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" st"#l"xrb %w1, %w0, [%2] \n" \
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" cbnz %w1, 1b \n" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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} \
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\
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static __inline void \
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atomic_##op##_##bar##16(volatile uint16_t *p, uint16_t val) \
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{ \
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uint16_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: ld"#a"xrh %w0, [%2] \n" \
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" "#asm_op" %w0, %w0, %w3 \n" \
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" st"#l"xrh %w1, %w0, [%2] \n" \
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" cbnz %w1, 1b \n" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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} \
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\
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static __inline void \
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atomic_##op##_##bar##32(volatile uint32_t *p, uint32_t val) \
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{ \
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uint32_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: ld"#a"xr %w0, [%2] \n" \
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" "#asm_op" %w0, %w0, %w3 \n" \
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" st"#l"xr %w1, %w0, [%2] \n" \
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" cbnz %w1, 1b \n" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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} \
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\
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static __inline void \
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atomic_##op##_##bar##64(volatile uint64_t *p, uint64_t val) \
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{ \
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uint64_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: ld"#a"xr %0, [%2] \n" \
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" "#asm_op" %0, %0, %3 \n" \
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" st"#l"xr %w1, %0, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"1: ld"#a"xr"#s" %"#w"0, [%2]\n" \
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" "#asm_op" %"#w"0, %"#w"0, %"#w"3\n" \
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" st"#l"xr"#s" %w1, %"#w"0, [%2]\n" \
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" cbnz %w1, 1b\n" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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}
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#define ATOMIC(op, asm_op) \
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ATOMIC_OP(op, asm_op, , , ) \
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ATOMIC_OP(op, asm_op, acq_, a, ) \
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ATOMIC_OP(op, asm_op, rel_, , l) \
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#define __ATOMIC_OP(op, asm_op, bar, a, l) \
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_ATOMIC_OP_IMPL(8, w, b, op, asm_op, bar, a, l) \
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_ATOMIC_OP_IMPL(16, w, h, op, asm_op, bar, a, l) \
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_ATOMIC_OP_IMPL(32, w, , op, asm_op, bar, a, l) \
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_ATOMIC_OP_IMPL(64, , , op, asm_op, bar, a, l)
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ATOMIC(add, add)
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ATOMIC(clear, bic)
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ATOMIC(set, orr)
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ATOMIC(subtract, sub)
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#define _ATOMIC_OP(op, asm_op) \
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__ATOMIC_OP(op, asm_op, , , ) \
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__ATOMIC_OP(op, asm_op, acq_, a, ) \
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__ATOMIC_OP(op, asm_op, rel_, , l)
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#define ATOMIC_FCMPSET(bar, a, l) \
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_ATOMIC_OP(add, add)
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_ATOMIC_OP(clear, bic)
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_ATOMIC_OP(set, orr)
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_ATOMIC_OP(subtract, sub)
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#define _ATOMIC_CMPSET_IMPL(t, w, s, bar, a, l) \
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static __inline int \
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atomic_fcmpset_##bar##8(volatile uint8_t *p, uint8_t *cmpval, \
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uint8_t newval) \
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atomic_cmpset_##bar##t(volatile uint##t##_t *p, uint##t##_t cmpval, \
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uint##t##_t newval) \
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{ \
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uint8_t tmp; \
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uint8_t _cmpval = *cmpval; \
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uint##t##_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xrb %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xrb %w1, %w4, [%2]\n" \
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"1: mov %w1, #1\n" \
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" ld"#a"xr"#s" %"#w"0, [%2]\n" \
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" cmp %"#w"0, %"#w"3\n" \
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" b.ne 2f\n" \
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" st"#l"xr"#s" %w1, %"#w"4, [%2]\n" \
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" cbnz %w1, 1b\n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (_cmpval), "r" (newval) \
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: "r" (p), "r" (cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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*cmpval = tmp; \
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\
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return (!res); \
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} \
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\
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static __inline int \
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atomic_fcmpset_##bar##16(volatile uint16_t *p, uint16_t *cmpval, \
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uint16_t newval) \
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atomic_fcmpset_##bar##t(volatile uint##t##_t *p, uint##t##_t *cmpval, \
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uint##t##_t newval) \
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{ \
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uint16_t tmp; \
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uint16_t _cmpval = *cmpval; \
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uint##t##_t _cmpval, tmp; \
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int res; \
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\
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_cmpval = *cmpval; \
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xrh %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xrh %w1, %w4, [%2] \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (_cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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*cmpval = tmp; \
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\
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return (!res); \
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} \
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\
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static __inline int \
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atomic_fcmpset_##bar##32(volatile uint32_t *p, uint32_t *cmpval, \
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uint32_t newval) \
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{ \
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uint32_t tmp; \
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uint32_t _cmpval = *cmpval; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %w4, [%2] \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (_cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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*cmpval = tmp; \
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\
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return (!res); \
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} \
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\
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static __inline int \
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atomic_fcmpset_##bar##64(volatile uint64_t *p, uint64_t *cmpval, \
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uint64_t newval) \
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{ \
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uint64_t tmp; \
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uint64_t _cmpval = *cmpval; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %0, [%2] \n" \
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" cmp %0, %3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %4, [%2] \n" \
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"2:" \
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" mov %w1, #1\n" \
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" ld"#a"xr"#s" %"#w"0, [%2]\n" \
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" cmp %"#w"0, %"#w"3\n" \
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" b.ne 1f\n" \
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" st"#l"xr"#s" %w1, %"#w"4, [%2]\n" \
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"1:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (_cmpval), "r" (newval) \
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: "cc", "memory" \
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@ -235,399 +141,142 @@ atomic_fcmpset_##bar##64(volatile uint64_t *p, uint64_t *cmpval, \
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return (!res); \
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}
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ATOMIC_FCMPSET( , , )
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ATOMIC_FCMPSET(acq_, a, )
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ATOMIC_FCMPSET(rel_, ,l)
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#define _ATOMIC_CMPSET(bar, a, l) \
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_ATOMIC_CMPSET_IMPL(8, w, b, bar, a, l) \
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_ATOMIC_CMPSET_IMPL(16, w, h, bar, a, l) \
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_ATOMIC_CMPSET_IMPL(32, w, , bar, a, l) \
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_ATOMIC_CMPSET_IMPL(64, , , bar, a, l)
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#undef ATOMIC_FCMPSET
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_ATOMIC_CMPSET( , , )
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_ATOMIC_CMPSET(acq_, a, )
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_ATOMIC_CMPSET(rel_, ,l)
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#define ATOMIC_CMPSET(bar, a, l) \
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static __inline int \
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atomic_cmpset_##bar##8(volatile uint8_t *p, uint8_t cmpval, \
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uint8_t newval) \
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#define _ATOMIC_FETCHADD_IMPL(t, w) \
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static __inline uint##t##_t \
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atomic_fetchadd_##t(volatile uint##t##_t *p, uint##t##_t val) \
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{ \
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uint8_t tmp; \
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uint##t##_t tmp, ret; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xrb %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xrb %w1, %w4, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (cmpval), "r" (newval) \
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: "cc", "memory" \
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"1: ldxr %"#w"2, [%3]\n" \
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" add %"#w"0, %"#w"2, %"#w"4\n" \
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" stxr %w1, %"#w"0, [%3]\n" \
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" cbnz %w1, 1b\n" \
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: "=&r" (tmp), "=&r" (res), "=&r" (ret) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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\
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return (!res); \
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return (ret); \
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}
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_ATOMIC_FETCHADD_IMPL(32, w)
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_ATOMIC_FETCHADD_IMPL(64, )
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#define _ATOMIC_SWAP_IMPL(t, w, zreg) \
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static __inline uint##t##_t \
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atomic_swap_##t(volatile uint##t##_t *p, uint##t##_t val) \
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{ \
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uint##t##_t ret; \
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int res; \
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\
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__asm __volatile( \
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"1: ldxr %"#w"1, [%2]\n" \
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" stxr %w0, %"#w"3, [%2]\n" \
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" cbnz %w0, 1b\n" \
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: "=&r" (res), "=&r" (ret) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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\
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return (ret); \
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} \
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\
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static __inline int \
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atomic_cmpset_##bar##16(volatile uint16_t *p, uint16_t cmpval, \
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uint16_t newval) \
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static __inline uint##t##_t \
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atomic_readandclear_##t(volatile uint##t##_t *p) \
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{ \
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uint16_t tmp; \
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uint##t##_t ret; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xrh %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xrh %w1, %w4, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (cmpval), "r" (newval) \
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: "cc", "memory" \
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"1: ldxr %"#w"1, [%2]\n" \
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" stxr %w0, "#zreg", [%2]\n" \
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" cbnz %w0, 1b\n" \
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: "=&r" (res), "=&r" (ret) \
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: "r" (p) \
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: "memory" \
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); \
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\
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return (!res); \
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} \
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\
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return (ret); \
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}
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_ATOMIC_SWAP_IMPL(32, w, wzr)
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_ATOMIC_SWAP_IMPL(64, , xzr)
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#define _ATOMIC_TEST_OP_IMPL(t, w, op, asm_op) \
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static __inline int \
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atomic_cmpset_##bar##32(volatile uint32_t *p, uint32_t cmpval, \
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uint32_t newval) \
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atomic_testand##op##_##t(volatile uint##t##_t *p, u_int val) \
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{ \
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uint32_t tmp; \
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uint##t##_t mask, old, tmp; \
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int res; \
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\
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mask = 1u << (val & 0x1f); \
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %w4, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (cmpval), "r" (newval) \
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: "cc", "memory" \
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"1: ldxr %"#w"2, [%3]\n" \
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" "#asm_op" %"#w"0, %"#w"2, %"#w"4\n" \
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" stxr %w1, %"#w"0, [%3]\n" \
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" cbnz %w1, 1b\n" \
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: "=&r" (tmp), "=&r" (res), "=&r" (old) \
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: "r" (p), "r" (mask) \
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: "memory" \
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); \
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\
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return (!res); \
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} \
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\
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static __inline int \
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atomic_cmpset_##bar##64(volatile uint64_t *p, uint64_t cmpval, \
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uint64_t newval) \
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return ((old & mask) != 0); \
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}
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#define _ATOMIC_TEST_OP(op, asm_op) \
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_ATOMIC_TEST_OP_IMPL(32, w, op, asm_op) \
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_ATOMIC_TEST_OP_IMPL(64, , op, asm_op)
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_ATOMIC_TEST_OP(clear, bic)
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_ATOMIC_TEST_OP(set, orr)
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#define _ATOMIC_LOAD_ACQ_IMPL(t, w, s) \
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static __inline uint##t##_t \
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atomic_load_acq_##t(volatile uint##t##_t *p) \
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{ \
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uint64_t tmp; \
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int res; \
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uint##t##_t ret; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %0, [%2] \n" \
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" cmp %0, %3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %4, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"2:" \
|
||||
: "=&r"(tmp), "=&r"(res) \
|
||||
: "r" (p), "r" (cmpval), "r" (newval) \
|
||||
: "cc", "memory" \
|
||||
); \
|
||||
"ldar"#s" %"#w"0, [%1]\n" \
|
||||
: "=&r" (ret) \
|
||||
: "r" (p) \
|
||||
: "memory"); \
|
||||
\
|
||||
return (!res); \
|
||||
return (ret); \
|
||||
}
|
||||
|
||||
ATOMIC_CMPSET( , , )
|
||||
ATOMIC_CMPSET(acq_, a, )
|
||||
ATOMIC_CMPSET(rel_, ,l)
|
||||
_ATOMIC_LOAD_ACQ_IMPL(8, w, b)
|
||||
_ATOMIC_LOAD_ACQ_IMPL(16, w, h)
|
||||
_ATOMIC_LOAD_ACQ_IMPL(32, w, )
|
||||
_ATOMIC_LOAD_ACQ_IMPL(64, , )
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
|
||||
{
|
||||
uint32_t tmp, ret;
|
||||
int res;
|
||||
|
||||
__asm __volatile(
|
||||
"1: ldxr %w2, [%3] \n"
|
||||
" add %w0, %w2, %w4 \n"
|
||||
" stxr %w1, %w0, [%3] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(tmp), "=&r"(res), "=&r"(ret)
|
||||
: "r" (p), "r" (val)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
uint64_t tmp, ret;
|
||||
int res;
|
||||
|
||||
__asm __volatile(
|
||||
"1: ldxr %2, [%3] \n"
|
||||
" add %0, %2, %4 \n"
|
||||
" stxr %w1, %0, [%3] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(tmp), "=&r"(res), "=&r"(ret)
|
||||
: "r" (p), "r" (val)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_readandclear_32(volatile uint32_t *p)
|
||||
{
|
||||
uint32_t ret;
|
||||
int res;
|
||||
|
||||
__asm __volatile(
|
||||
"1: ldxr %w1, [%2] \n"
|
||||
" stxr %w0, wzr, [%2] \n"
|
||||
" cbnz %w0, 1b \n"
|
||||
: "=&r"(res), "=&r"(ret)
|
||||
: "r" (p)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_readandclear_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret;
|
||||
int res;
|
||||
|
||||
__asm __volatile(
|
||||
"1: ldxr %1, [%2] \n"
|
||||
" stxr %w0, xzr, [%2] \n"
|
||||
" cbnz %w0, 1b \n"
|
||||
: "=&r"(res), "=&r"(ret)
|
||||
: "r" (p)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_swap_32(volatile uint32_t *p, uint32_t val)
|
||||
{
|
||||
uint32_t ret;
|
||||
int res;
|
||||
|
||||
__asm __volatile(
|
||||
"1: ldxr %w0, [%2] \n"
|
||||
" stxr %w1, %w3, [%2] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(ret), "=&r"(res)
|
||||
: "r" (p), "r" (val)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_swap_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
uint64_t ret;
|
||||
int res;
|
||||
|
||||
__asm __volatile(
|
||||
"1: ldxr %0, [%2] \n"
|
||||
" stxr %w1, %3, [%2] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(ret), "=&r"(res)
|
||||
: "r" (p), "r" (val)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint8_t
|
||||
atomic_load_acq_8(volatile uint8_t *p)
|
||||
{
|
||||
uint8_t ret;
|
||||
|
||||
__asm __volatile(
|
||||
"ldarb %w0, [%1] \n"
|
||||
: "=&r" (ret)
|
||||
: "r" (p)
|
||||
: "memory");
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint16_t
|
||||
atomic_load_acq_16(volatile uint16_t *p)
|
||||
{
|
||||
uint16_t ret;
|
||||
|
||||
__asm __volatile(
|
||||
"ldarh %w0, [%1] \n"
|
||||
: "=&r" (ret)
|
||||
: "r" (p)
|
||||
: "memory");
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
atomic_load_acq_32(volatile uint32_t *p)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
__asm __volatile(
|
||||
"ldar %w0, [%1] \n"
|
||||
: "=&r" (ret)
|
||||
: "r" (p)
|
||||
: "memory");
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
atomic_load_acq_64(volatile uint64_t *p)
|
||||
{
|
||||
uint64_t ret;
|
||||
|
||||
__asm __volatile(
|
||||
"ldar %0, [%1] \n"
|
||||
: "=&r" (ret)
|
||||
: "r" (p)
|
||||
: "memory");
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_8(volatile uint8_t *p, uint8_t val)
|
||||
{
|
||||
|
||||
__asm __volatile(
|
||||
"stlrb %w0, [%1] \n"
|
||||
:
|
||||
: "r" (val), "r" (p)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_16(volatile uint16_t *p, uint16_t val)
|
||||
{
|
||||
|
||||
__asm __volatile(
|
||||
"stlrh %w0, [%1] \n"
|
||||
:
|
||||
: "r" (val), "r" (p)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_32(volatile uint32_t *p, uint32_t val)
|
||||
{
|
||||
|
||||
__asm __volatile(
|
||||
"stlr %w0, [%1] \n"
|
||||
:
|
||||
: "r" (val), "r" (p)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static __inline void
|
||||
atomic_store_rel_64(volatile uint64_t *p, uint64_t val)
|
||||
{
|
||||
|
||||
__asm __volatile(
|
||||
"stlr %0, [%1] \n"
|
||||
:
|
||||
: "r" (val), "r" (p)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static __inline int
|
||||
atomic_testandclear_32(volatile uint32_t *p, u_int val)
|
||||
{
|
||||
uint32_t mask, old, tmp;
|
||||
int res;
|
||||
|
||||
mask = 1u << (val & 0x1f);
|
||||
__asm __volatile(
|
||||
"1: ldxr %w2, [%3] \n"
|
||||
" bic %w0, %w2, %w4 \n"
|
||||
" stxr %w1, %w0, [%3] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(tmp), "=&r"(res), "=&r"(old)
|
||||
: "r" (p), "r" (mask)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return ((old & mask) != 0);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
atomic_testandclear_64(volatile uint64_t *p, u_int val)
|
||||
{
|
||||
uint64_t mask, old, tmp;
|
||||
int res;
|
||||
|
||||
mask = 1ul << (val & 0x1f);
|
||||
__asm __volatile(
|
||||
"1: ldxr %2, [%3] \n"
|
||||
" bic %0, %2, %4 \n"
|
||||
" stxr %w1, %0, [%3] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(tmp), "=&r"(res), "=&r"(old)
|
||||
: "r" (p), "r" (mask)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return ((old & mask) != 0);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
atomic_testandset_32(volatile uint32_t *p, u_int val)
|
||||
{
|
||||
uint32_t mask, old, tmp;
|
||||
int res;
|
||||
|
||||
mask = 1u << (val & 0x1f);
|
||||
__asm __volatile(
|
||||
"1: ldxr %w2, [%3] \n"
|
||||
" orr %w0, %w2, %w4 \n"
|
||||
" stxr %w1, %w0, [%3] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(tmp), "=&r"(res), "=&r"(old)
|
||||
: "r" (p), "r" (mask)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return ((old & mask) != 0);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
atomic_testandset_64(volatile uint64_t *p, u_int val)
|
||||
{
|
||||
uint64_t mask, old, tmp;
|
||||
int res;
|
||||
|
||||
mask = 1ul << (val & 0x1f);
|
||||
__asm __volatile(
|
||||
"1: ldxr %2, [%3] \n"
|
||||
" orr %0, %2, %4 \n"
|
||||
" stxr %w1, %0, [%3] \n"
|
||||
" cbnz %w1, 1b \n"
|
||||
: "=&r"(tmp), "=&r"(res), "=&r"(old)
|
||||
: "r" (p), "r" (mask)
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return ((old & mask) != 0);
|
||||
#define _ATOMIC_STORE_REL_IMPL(t, w, s) \
|
||||
static __inline void \
|
||||
atomic_store_rel_##t(volatile uint##t##_t *p, uint##t##_t val) \
|
||||
{ \
|
||||
__asm __volatile( \
|
||||
"stlr"#s" %"#w"0, [%1]\n" \
|
||||
: \
|
||||
: "r" (val), "r" (p) \
|
||||
: "memory"); \
|
||||
}
|
||||
|
||||
_ATOMIC_STORE_REL_IMPL(8, w, b)
|
||||
_ATOMIC_STORE_REL_IMPL(16, w, h)
|
||||
_ATOMIC_STORE_REL_IMPL(32, w, )
|
||||
_ATOMIC_STORE_REL_IMPL(64, , )
|
||||
|
||||
#define atomic_add_int atomic_add_32
|
||||
#define atomic_fcmpset_int atomic_fcmpset_32
|
||||
@ -742,4 +391,3 @@ atomic_thread_fence_seq_cst(void)
|
||||
#endif /* KCSAN && !KCSAN_RUNTIME */
|
||||
|
||||
#endif /* _MACHINE_ATOMIC_H_ */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user