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Try to make the style consistent (including regarding NetBSD bits not yet

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merged) and adhere style(9).
This commit is contained in:
Marius Strobl 2010-10-31 22:46:39 +00:00
parent 4a446e3e8e
commit 3b18190fe9
1 changed files with 39 additions and 44 deletions
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83
sys/dev/mii/mii_physubr.c
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@ -107,8 +107,8 @@ mii_phy_setmedia(struct mii_softc *sc)
if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
if ((PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN) == 0 ||
(sc->mii_flags & MIIF_FORCEANEG))
(void) mii_phy_auto(sc);
(sc->mii_flags & MIIF_FORCEANEG) != 0)
(void)mii_phy_auto(sc);
return;
}
@ -124,10 +124,10 @@ mii_phy_setmedia(struct mii_softc *sc)
bmcr = mii_media_table[ife->ifm_data].mm_bmcr;
gtcr = mii_media_table[ife->ifm_data].mm_gtcr;
if (mii->mii_media.ifm_media & IFM_ETH_MASTER) {
if ((mii->mii_media.ifm_media & IFM_ETH_MASTER) != 0) {
switch (IFM_SUBTYPE(ife->ifm_media)) {
case IFM_1000_T:
gtcr |= GTCR_MAN_MS|GTCR_ADV_MS;
gtcr |= GTCR_MAN_MS | GTCR_ADV_MS;
break;
default:
@ -135,53 +135,48 @@ mii_phy_setmedia(struct mii_softc *sc)
}
}
if (ife->ifm_media & IFM_LOOP)
if ((ife->ifm_media & IFM_LOOP) != 0)
bmcr |= BMCR_LOOP;
PHY_WRITE(sc, MII_ANAR, anar);
PHY_WRITE(sc, MII_BMCR, bmcr);
if (sc->mii_flags & MIIF_HAVE_GTCR)
if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0)
PHY_WRITE(sc, MII_100T2CR, gtcr);
}
int
mii_phy_auto(struct mii_softc *sc)
{
int anar, gtcr;
/*
* Check for 1000BASE-X. Autonegotiation is a bit
* different on such devices.
*/
if (sc->mii_flags & MIIF_IS_1000X) {
uint16_t anar = 0;
if (sc->mii_extcapabilities & EXTSR_1000XFDX)
if ((sc->mii_flags & MIIF_IS_1000X) != 0) {
anar = 0;
if ((sc->mii_extcapabilities & EXTSR_1000XFDX) != 0)
anar |= ANAR_X_FD;
if (sc->mii_extcapabilities & EXTSR_1000XHDX)
if ((sc->mii_extcapabilities & EXTSR_1000XHDX) != 0)
anar |= ANAR_X_HD;
if (sc->mii_flags & MIIF_DOPAUSE) {
if ((sc->mii_flags & MIIF_DOPAUSE) != 0) {
/* XXX Asymmetric vs. symmetric? */
anar |= ANLPAR_X_PAUSE_TOWARDS;
}
PHY_WRITE(sc, MII_ANAR, anar);
} else {
uint16_t anar;
anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) |
ANAR_CSMA;
if (sc->mii_flags & MIIF_DOPAUSE)
if ((sc->mii_flags & MIIF_DOPAUSE) != 0)
anar |= ANAR_FC;
PHY_WRITE(sc, MII_ANAR, anar);
if (sc->mii_flags & MIIF_HAVE_GTCR) {
uint16_t gtcr = 0;
if (sc->mii_extcapabilities & EXTSR_1000TFDX)
if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
gtcr = 0;
if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0)
gtcr |= GTCR_ADV_1000TFDX;
if (sc->mii_extcapabilities & EXTSR_1000THDX)
if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0)
gtcr |= GTCR_ADV_1000THDX;
PHY_WRITE(sc, MII_100T2CR, gtcr);
}
}
@ -213,7 +208,7 @@ mii_phy_tick(struct mii_softc *sc)
/* Read the status register twice; BMSR_LINK is latch-low. */
reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
if (reg & BMSR_LINK) {
if ((reg & BMSR_LINK) != 0) {
sc->mii_ticks = 0; /* reset autonegotiation timer. */
/* See above. */
return (0);
@ -243,7 +238,7 @@ mii_phy_reset(struct mii_softc *sc)
struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
int reg, i;
if (sc->mii_flags & MIIF_NOISOLATE)
if ((sc->mii_flags & MIIF_NOISOLATE) != 0)
reg = BMCR_RESET;
else
reg = BMCR_RESET | BMCR_ISO;
@ -303,7 +298,10 @@ mii_phy_add_media(struct mii_softc *sc)
return;
}
/* Set aneg timer for 10/100 media. Gigabit media handled below. */
/*
* Set the autonegotiation timer for 10/100 media. Gigabit media is
* handled below.
*/
sc->mii_anegticks = MII_ANEGTICKS;
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
@ -318,55 +316,54 @@ mii_phy_add_media(struct mii_softc *sc)
* HomePNA PHYs. And there is really only one media type
* that is supported.
*/
if (sc->mii_flags & MIIF_IS_HPNA) {
if (sc->mii_capabilities & BMSR_10THDX) {
if ((sc->mii_flags & MIIF_IS_HPNA) != 0) {
if ((sc->mii_capabilities & BMSR_10THDX) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_HPNA_1, 0,
sc->mii_inst),
MII_MEDIA_10_T);
sc->mii_inst), MII_MEDIA_10_T);
PRINT("HomePNA1");
}
return;
}
if (sc->mii_capabilities & BMSR_10THDX) {
if ((sc->mii_capabilities & BMSR_10THDX) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
MII_MEDIA_10_T);
PRINT("10baseT");
}
if (sc->mii_capabilities & BMSR_10TFDX) {
if ((sc->mii_capabilities & BMSR_10TFDX) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
MII_MEDIA_10_T_FDX);
PRINT("10baseT-FDX");
}
if (sc->mii_capabilities & BMSR_100TXHDX) {
if ((sc->mii_capabilities & BMSR_100TXHDX) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
MII_MEDIA_100_TX);
PRINT("100baseTX");
}
if (sc->mii_capabilities & BMSR_100TXFDX) {
if ((sc->mii_capabilities & BMSR_100TXFDX) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
MII_MEDIA_100_TX_FDX);
PRINT("100baseTX-FDX");
}
if (sc->mii_capabilities & BMSR_100T4) {
if ((sc->mii_capabilities & BMSR_100T4) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_T4, 0, sc->mii_inst),
MII_MEDIA_100_T4);
PRINT("100baseT4");
}
if (sc->mii_extcapabilities & EXTSR_MEDIAMASK) {
if ((sc->mii_extcapabilities & EXTSR_MEDIAMASK) != 0) {
/*
* XXX Right now only handle 1000SX and 1000TX. Need
* XXX to handle 1000LX and 1000CX some how.
* XXX to handle 1000LX and 1000CX somehow.
*/
if (sc->mii_extcapabilities & EXTSR_1000XHDX) {
if ((sc->mii_extcapabilities & EXTSR_1000XHDX) != 0) {
sc->mii_anegticks = MII_ANEGTICKS_GIGE;
sc->mii_flags |= MIIF_IS_1000X;
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0,
sc->mii_inst), MII_MEDIA_1000_X);
PRINT("1000baseSX");
}
if (sc->mii_extcapabilities & EXTSR_1000XFDX) {
if ((sc->mii_extcapabilities & EXTSR_1000XFDX) != 0) {
sc->mii_anegticks = MII_ANEGTICKS_GIGE;
sc->mii_flags |= MIIF_IS_1000X;
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX,
@ -382,7 +379,7 @@ mii_phy_add_media(struct mii_softc *sc)
*
* All 1000baseT PHYs have a 1000baseT control register.
*/
if (sc->mii_extcapabilities & EXTSR_1000THDX) {
if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0) {
sc->mii_anegticks = MII_ANEGTICKS_GIGE;
sc->mii_flags |= MIIF_HAVE_GTCR;
mii->mii_media.ifm_mask |= IFM_ETH_MASTER;
@ -390,7 +387,7 @@ mii_phy_add_media(struct mii_softc *sc)
sc->mii_inst), MII_MEDIA_1000_T);
PRINT("1000baseT");
}
if (sc->mii_extcapabilities & EXTSR_1000TFDX) {
if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0) {
sc->mii_anegticks = MII_ANEGTICKS_GIGE;
sc->mii_flags |= MIIF_HAVE_GTCR;
mii->mii_media.ifm_mask |= IFM_ETH_MASTER;
@ -400,7 +397,7 @@ mii_phy_add_media(struct mii_softc *sc)
}
}
if (sc->mii_capabilities & BMSR_ANEG) {
if ((sc->mii_capabilities & BMSR_ANEG) != 0) {
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst),
MII_NMEDIA); /* intentionally invalid index */
PRINT("auto");
@ -418,8 +415,7 @@ mii_phy_detach(device_t dev)
mii_phy_down(sc);
sc->mii_dev = NULL;
LIST_REMOVE(sc, mii_list);
return(0);
return (0);
}
const struct mii_phydesc *
@ -452,6 +448,5 @@ mii_phy_dev_probe(device_t dev, const struct mii_phydesc *mpd, int mrv)
device_set_desc(dev, mpd->mpd_name);
return (mrv);
}
return (ENXIO);
}