Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.
Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.
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@ -564,6 +564,8 @@
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#define SVR_MPC8533E 0x8034
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#define SVR_MPC8533E 0x8034
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#define SVR_MPC8541 0x8072
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#define SVR_MPC8541 0x8072
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#define SVR_MPC8541E 0x807a
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#define SVR_MPC8541E 0x807a
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#define SVR_MPC8548 0x8031
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#define SVR_MPC8548E 0x8039
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#define SVR_MPC8555 0x8071
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#define SVR_MPC8555 0x8071
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#define SVR_MPC8555E 0x8079
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#define SVR_MPC8555E 0x8079
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#define SVR_MPC8572 0x80e0
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#define SVR_MPC8572 0x80e0
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@ -61,7 +61,7 @@ ccsr_write4(uintptr_t addr, uint32_t val)
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__asm __volatile("eieio; sync");
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__asm __volatile("eieio; sync");
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}
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}
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static __inline int
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int
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law_getmax(void)
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law_getmax(void)
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{
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{
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uint32_t ver;
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uint32_t ver;
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@ -69,6 +69,8 @@ law_getmax(void)
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ver = SVR_VER(mfspr(SPR_SVR));
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
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return (12);
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return (12);
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else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
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return (10);
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else
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else
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return (8);
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return (8);
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}
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}
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@ -132,7 +134,8 @@ cpu_reset(void)
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{
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{
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uint32_t ver = SVR_VER(mfspr(SPR_SVR));
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uint32_t ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
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ver == SVR_MPC8548E || ver == SVR_MPC8548)
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/* Systems with dedicated reset register */
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/* Systems with dedicated reset register */
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ccsr_write4(OCP85XX_RSTCR, 2);
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ccsr_write4(OCP85XX_RSTCR, 2);
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else {
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else {
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@ -33,5 +33,6 @@ uint32_t ccsr_read4(uintptr_t addr);
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void ccsr_write4(uintptr_t addr, uint32_t val);
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void ccsr_write4(uintptr_t addr, uint32_t val);
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int law_enable(int trgt, u_long addr, u_long size);
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int law_enable(int trgt, u_long addr, u_long size);
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int law_disable(int trgt, u_long addr, u_long size);
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int law_disable(int trgt, u_long addr, u_long size);
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int law_getmax(void);
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#endif /* _MPC85XX_H_ */
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#endif /* _MPC85XX_H_ */
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@ -114,8 +114,6 @@ devclass_t ocpbus_devclass;
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DRIVER_MODULE(ocpbus, nexus, ocpbus_driver, ocpbus_devclass, 0, 0);
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DRIVER_MODULE(ocpbus, nexus, ocpbus_driver, ocpbus_devclass, 0, 0);
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static int law_max = 0;
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static device_t
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static device_t
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ocpbus_mk_child(device_t dev, int type, int unit)
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ocpbus_mk_child(device_t dev, int type, int unit)
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{
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{
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@ -189,16 +187,6 @@ ocpbus_write_law(int trgt, int type, u_long *startp, u_long *countp)
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static int
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static int
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ocpbus_probe(device_t dev)
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ocpbus_probe(device_t dev)
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{
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{
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struct ocpbus_softc *sc;
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uint32_t ver;
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sc = device_get_softc(dev);
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ver = SVR_VER(mfspr(SPR_SVR));
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if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
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law_max = 12;
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else
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law_max = 8;
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device_set_desc(dev, "On-Chip Peripherals bus");
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device_set_desc(dev, "On-Chip Peripherals bus");
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return (BUS_PROBE_DEFAULT);
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return (BUS_PROBE_DEFAULT);
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@ -208,7 +196,7 @@ static int
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ocpbus_attach(device_t dev)
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ocpbus_attach(device_t dev)
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{
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{
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struct ocpbus_softc *sc;
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struct ocpbus_softc *sc;
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int error, i, tgt;
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int error, i, tgt, law_max;
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uint32_t sr;
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uint32_t sr;
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u_long start, end;
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u_long start, end;
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@ -261,6 +249,7 @@ ocpbus_attach(device_t dev)
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* Clear local access windows. Skip DRAM entries, so we don't shoot
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* Clear local access windows. Skip DRAM entries, so we don't shoot
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* ourselves in the foot.
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* ourselves in the foot.
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*/
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*/
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law_max = law_getmax();
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for (i = 0; i < law_max; i++) {
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for (i = 0; i < law_max; i++) {
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sr = ccsr_read4(OCP85XX_LAWSR(i));
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sr = ccsr_read4(OCP85XX_LAWSR(i));
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if ((sr & 0x80000000) == 0)
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if ((sr & 0x80000000) == 0)
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