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attilio 2011-06-02 14:09:30 +00:00
commit 3c36d05669
66 changed files with 2857 additions and 295 deletions
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6
lib/libc/iconv/iconvctl.3
View File

@ -150,6 +150,9 @@ facility is a non-standard extension, which appeared in
the GNU implementation and was adopted in
.Fx 9
for compatibility's sake.
.Sh AUTHORS
This manual page was written by
.An Gabor Kovesdan Aq gabor@FreeBSD.org .
.Sh BUGS
Transliteration is enabled in this implementation by default, so it
is impossible by design to turn it off.
@ -157,6 +160,3 @@ Accordingly, trying to turn it off will always fail and \-1 will be
returned.
Getting the transliteration state will always succeed and indicate
that it is turned on, though.
.Sh AUTHORS
This manual page was written by
.An Gabor Kovesdan Aq gabor@FreeBSD.org .

1
sbin/geom/class/part/gpart.8
View File

@ -818,6 +818,7 @@ GEOM class verifies all generic partition parameters that it gets from the
disk metadata. If some inconsistency is detected, partition table will be
rejected with a diagnostic message:
.Pa GEOM_PART: Integrity check failed (provider, scheme) .
.El
.Sh EXIT STATUS
Exit status is 0 on success, and 1 if the command fails.
.Sh EXAMPLES

5
sbin/setkey/setkey.8
View File

@ -441,13 +441,14 @@ protocols other than TCP, UDP and ICMP may not be suitable to use with IPsec.
.It Ar policy
.Ar policy
is expressed in one of the following three formats:
.Bd -ragged -offset indent
.Pp
.Bl -tag -compact
.It Fl P Ar direction Li discard
.It Fl P Ar direction Li none
.It Xo Fl P Ar direction Li ipsec
.Ar protocol/mode/src-dst/level Op ...
.Xc
.Ed
.El
.Pp
The direction of a policy must be specified as
one of:

1
share/man/man4/Makefile
View File

@ -475,6 +475,7 @@ MAN= aac.4 \
ukbd.4 \
ulpt.4 \
umass.4 \
umcs7840.4 \
umct.4 \
umodem.4 \
ums.4 \

6
share/man/man4/bwn.4
View File

@ -142,9 +142,6 @@ The
.Nm
driver first appeared in
.Fx 8.1 .
.Sh CAVEATS
Some LP PHY devices have DMA operation problems that in that case try to
use PIO mode.
.Sh AUTHORS
.An -nosplit
The
@ -155,3 +152,6 @@ driver was written by
.\".Sh BUGS
.\"Some card based on the BCM4306 and BCM4309 chips do not work properly
.\"on channel 1, 2 and 3.
.Sh CAVEATS
Some LP PHY devices have DMA operation problems that in that case try to
use PIO mode.

28
share/man/man4/em.4
View File

@ -227,6 +227,20 @@ If
is non-zero, this tunable limits the maximum delay in which a transmit
interrupt is generated.
.El
.Sh FILES
.Bl -tag -width /dev/led/em*
.It Pa /dev/led/em*
identification LED device nodes
.El
.Sh EXAMPLES
Make the identification LED of em0 blink:
.Pp
.Dl "echo f2 > /dev/led/em0"
.Pp
Turn the identification LED of em0 off again:
.Pp
.Dl "echo 0 > /dev/led/em0"
.Pp
.Sh DIAGNOSTICS
.Bl -diag
.It "em%d: Unable to allocate bus resource: memory"
@ -246,20 +260,6 @@ If an issue is identified with the released source code on the supported kernel
with a supported adapter, email the specific information related to the
issue to
.Aq freebsdnic@mailbox.intel.com .
.Sh FILES
.Bl -tag -width /dev/led/em*
.It Pa /dev/led/em*
identification LED device nodes
.El
.Sh EXAMPLES
Make the identification LED of em0 blink:
.Pp
.Dl "echo f2 > /dev/led/em0"
.Pp
Turn the identification LED of em0 off again:
.Pp
.Dl "echo 0 > /dev/led/em0"
.Pp
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,

28
share/man/man4/igb.4
View File

@ -161,6 +161,20 @@ The minimum is 80, and the maximum is 4096.
If set to 1, enable Adaptive Interrupt Moderation.
The default is to enable Adaptive Interrupt Moderation.
.El
.Sh FILES
.Bl -tag -width /dev/led/igb*
.It Pa /dev/led/igb*
identification LED device nodes
.El
.Sh EXAMPLES
Make the identification LED of igb0 blink:
.Pp
.Dl "echo f2 > /dev/led/igb0"
.Pp
Turn the identification LED of igb0 off again:
.Pp
.Dl "echo 0 > /dev/led/igb0"
.Pp
.Sh DIAGNOSTICS
.Bl -diag
.It "igb%d: Unable to allocate bus resource: memory"
@ -180,20 +194,6 @@ If an issue is identified with the released source code on the supported kernel
with a supported adapter, email the specific information related to the
issue to
.Aq freebsdnic@mailbox.intel.com .
.Sh FILES
.Bl -tag -width /dev/led/igb*
.It Pa /dev/led/igb*
identification LED device nodes
.El
.Sh EXAMPLES
Make the identification LED of igb0 blink:
.Pp
.Dl "echo f2 > /dev/led/igb0"
.Pp
Turn the identification LED of igb0 off again:
.Pp
.Dl "echo 0 > /dev/led/igb0"
.Pp
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,

26
share/man/man4/mps.4
View File

@ -143,6 +143,19 @@ Enable prints for controller events.
.Xr sa 4 ,
.Xr scsi 4 ,
.Xr targ 4
.Sh HISTORY
The
.Nm
driver first appeared in
.Fx 9.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was originally written by
.An Scott Long Aq scottl@FreeBSD.org .
This man page was written by
.An Ken Merry Aq ken@FreeBSD.org .
.Sh BUGS
This driver is still in development, it has only been tested on the amd64
architecture and has some known shortcomings:
@ -158,16 +171,3 @@ times, without user intervention.
.It
The error recovery code isn't complete.
.El
.Sh HISTORY
The
.Nm
driver first appeared in
.Fx 9.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was originally written by
.An Scott Long Aq scottl@FreeBSD.org .
This man page was written by
.An Ken Merry Aq ken@FreeBSD.org .

1
share/man/man4/ucom.4
View File

@ -78,6 +78,7 @@ multiple external ports.
.Xr uark 4 ,
.Xr uchcom 4 ,
.Xr uftdi 4 ,
.Xr umcs7840 4 ,
.Xr umct 4 ,
.Xr umodem 4 ,
.Xr uplcom 4 ,

10
share/man/man4/uep.4
View File

@ -57,11 +57,6 @@ To get mouse working in
.Xr X 7 ,
one needs to install
.Pa ports/x11-drivers/xf86-input-egalax .
.Sh BUGS
.Nm
can't act like
.Xr sysmouse 4 ,
since the latter does not support absolute motion events.
.Sh FILES
.Nm
creates a blocking pseudo\-device file,
@ -77,3 +72,8 @@ The
.Nm
driver was written by
.An Gleb Smirnoff Aq glebius@FreeBSD.org
.Sh BUGS
.Nm
can't act like
.Xr sysmouse 4 ,
since the latter does not support absolute motion events.

97
share/man/man4/umcs7840.4 Normal file
View File

@ -0,0 +1,97 @@
.\"
.\" Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>.
.\" All rights reserved.
.\"
.\" This code is derived from software contributed to The NetBSD Foundation
.\" by Lennart Augustsson.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd December 10, 2010
.Dt UMCS7840 4
.Os
.Sh NAME
.Nm umcs7840
.Nd USB support for serial adapters based on the MCS7820 and MCS7840 chips
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device umcs7840"
.Ed
.Pp
Alternatively, to load the driver as a
module at boot time, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
umcs7840_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver provides support for various multiport serial adapters based on the MosCom
MCS7820 and MCS7840 chips. They are 2- or 4-port adapters with full-featured
16550-compatible UARTs and very flexible baud generators. Also, these chips
support RS422/RS485 and IrDA oprations.
.Pp
The device is accessed through the
.Xr ucom 4
driver which makes it behave like a
.Xr tty 4 .
.Pp
Different ports on device are presented as sub-units, like
.Pa /dev/ttyU0.1
and
.Pa /dev/ttyU0.2
.Sh HARDWARE
The
.Nm
driver was tested on the following adapters:
.Pp
.Bl -bullet -compact
.It
ST Lab U-360 two-port serial USB adapter
.It
ST Lab U-400 four-port serial USB adapter
.El
.Sh SEE ALSO
.Xr tty 4 ,
.Xr ucom 4 ,
.Xr usb 4
.Sh HISTORY
The
.Nm
driver
appeared in ports since December of 2010.
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was written by
.An Lev Serebryakov
.Aq lev@FreeBSD.org .
.Sh BUGS
This driver doesn't support access to any fine tunes of
chip, like RS522/RS485 mode, non-standard baudrates, etc.

18
share/man/man9/bus_adjust_resource.9
View File

@ -67,6 +67,15 @@ It is the caller's responsibility to enforce any such requirements.
The
.Fn bus_adjust_resource
method returns zero on success or an error code on failure.
.Sh EXAMPLES
Grow an existing memory resource by 4096 bytes.
.Bd -literal
struct resource *res;
int error;
error = bus_adjust_resource(dev, SYS_RES_MEMORY, res,
rman_get_start(res), rman_get_end(res) + 0x1000);
.Ed
.Sh ERRORS
.Fn bus_adjust_resource
will fail if:
@ -85,15 +94,6 @@ The new address range does not overlap with the existing address range of
.It Bq Er EBUSY
The new address range conflicts with another allocated resource.
.El
.Sh EXAMPLES
Grow an existing memory resource by 4096 bytes.
.Bd -literal
struct resource *res;
int error;
error = bus_adjust_resource(dev, SYS_RES_MEMORY, res,
rman_get_start(res), rman_get_end(res) + 0x1000);
.Ed
.Sh SEE ALSO
.Xr bus_alloc_resource 9 ,
.Xr bus_release_resource 9 ,

1
share/misc/mdoc.template
View File

@ -33,3 +33,4 @@
.\" .Sh HISTORY
.\" .Sh AUTHORS
.\" .Sh BUGS
.\" .Sh SECURITY CONSIDERATIONS

2
sys/boot/forth/check-password.4th.8
View File

@ -67,7 +67,7 @@ variable in
.Pp
Subsequent calls after a successful password
has been entered will not cause reprompting
.Nd the function will silently return.
\(em the function will silently return.
.El
.Pp
The environment variables that effect its behavior are:

8
sys/conf/files
View File

@ -846,7 +846,10 @@ dev/ath/ath_rate/onoe/onoe.c optional ath_rate_onoe \
compile-with "${NORMAL_C} -I$S/dev/ath"
dev/ath/ath_rate/sample/sample.c optional ath_rate_sample \
compile-with "${NORMAL_C} -I$S/dev/ath"
#
# ath DFS modules
dev/ath/ath_dfs/null/dfs_null.c optional ath \
compile-with "${NORMAL_C} -I$S/dev/ath"
#
dev/bce/if_bce.c optional bce
dev/bfe/if_bfe.c optional bfe
dev/bge/if_bge.c optional bge
@ -1955,6 +1958,7 @@ dev/usb/serial/uftdi.c optional uftdi
dev/usb/serial/ugensa.c optional ugensa
dev/usb/serial/uipaq.c optional uipaq
dev/usb/serial/ulpt.c optional ulpt
dev/usb/serial/umcs7840.c optional umcs7840
dev/usb/serial/umct.c optional umct
dev/usb/serial/umodem.c optional umodem
dev/usb/serial/umoscom.c optional umoscom
@ -1964,7 +1968,7 @@ dev/usb/serial/uvisor.c optional uvisor
dev/usb/serial/uvscom.c optional uvscom
dev/usb/serial/usb_serial.c optional ucom | u3g | uark | ubsa | ubser | \
uchcom | ucycom | ufoma | uftdi | \
ugensa | uipaq | umct | \
ugensa | uipaq | umcs7840 | umct | \
umodem | umoscom | uplcom | uslcom | \
uvisor | uvscom
#

160
sys/dev/ath/ath_dfs/null/dfs_null.c Normal file
View File

@ -0,0 +1,160 @@
/*-
* Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* This implements an empty DFS module.
*/
#include "opt_inet.h"
#include "opt_wlan.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysctl.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/errno.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <sys/socket.h>
#include <net/if.h>
#include <net/if_media.h>
#include <net/if_arp.h>
#include <net/ethernet.h> /* XXX for ether_sprintf */
#include <net80211/ieee80211_var.h>
#include <net/bpf.h>
#ifdef INET
#include <netinet/in.h>
#include <netinet/if_ether.h>
#endif
#include <dev/ath/if_athvar.h>
#include <dev/ath/if_athdfs.h>
#include <dev/ath/ath_hal/ah_desc.h>
/*
* Methods which are required
*/
/*
* Attach DFS to the given interface
*/
int
ath_dfs_attach(struct ath_softc *sc)
{
return 1;
}
/*
* Detach DFS from the given interface
*/
int
ath_dfs_detach(struct ath_softc *sc)
{
return 1;
}
/*
* Enable radar check
*/
void
ath_dfs_radar_enable(struct ath_softc *sc, struct ieee80211_channel *chan)
{
/* Check if the current channel is radar-enabled */
if (! IEEE80211_IS_CHAN_DFS(chan))
return;
}
/*
* Process DFS related PHY errors
*/
void
ath_dfs_process_phy_err(struct ath_softc *sc, struct ath_desc *ds,
uint64_t tsf, struct ath_rx_status *rxstat)
{
}
/*
* Process the radar events and determine whether a DFS event has occured.
*
* This is designed to run outside of the RX processing path.
* The RX path will call ath_dfs_tasklet_needed() to see whether
* the task/callback running this routine needs to be called.
*/
int
ath_dfs_process_radar_event(struct ath_softc *sc,
struct ieee80211_channel *chan)
{
return 0;
}
/*
* Determine whether the the DFS check task needs to be queued.
*
* This is called in the RX task when the current batch of packets
* have been received. It will return whether there are any radar
* events for ath_dfs_process_radar_event() to handle.
*/
int
ath_dfs_tasklet_needed(struct ath_softc *sc, struct ieee80211_channel *chan)
{
return 0;
}
/*
* Handle ioctl requests from the diagnostic interface
*/
int
ath_ioctl_phyerr(struct ath_softc *sc, struct ath_diag *ad)
{
return 1;
}
/*
* Get the current DFS thresholds from the HAL
*/
int
ath_dfs_get_thresholds(struct ath_softc *sc, HAL_PHYERR_PARAM *param)
{
ath_hal_getdfsthresh(sc->sc_ah, param);
return 1;
}

6
sys/dev/ath/ath_hal/ah.c
View File

@ -610,6 +610,10 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
return HAL_OK;
case HAL_CAP_4ADDR_AGGR:
return pCap->hal4AddrAggrSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_EXT_CHAN_DFS:
return pCap->halExtChanDfsSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_COMBINED_RADAR_RSSI:
return pCap->halUseCombinedRadarRssi ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_AUTO_SLEEP:
return pCap->halAutoSleepSupport ? HAL_OK : HAL_ENOTSUPP;
case HAL_CAP_MBSSID_AGGR_SUPPORT:
@ -626,6 +630,8 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
case HAL_CAP_RXTSTAMP_PREC: /* rx desc tstamp precision (bits) */
*result = pCap->halTstampPrecision;
return HAL_OK;
case HAL_CAP_ENHANCED_DFS_SUPPORT:
return pCap->halEnhancedDfsSupport ? HAL_OK : HAL_ENOTSUPP;
/* FreeBSD-specific entries for now */
case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */

38
sys/dev/ath/ath_hal/ah.h
View File

@ -121,6 +121,9 @@ typedef enum {
HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */
HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */
HAL_CAP_DFS_DMN = 44, /* current DFS domain */
HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */
HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */
HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep
automatically after waking up to receive TIM */
@ -133,6 +136,7 @@ typedef enum {
HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */
HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */
HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */
/* The following are private to the FreeBSD HAL (224 onward) */
@ -703,6 +707,34 @@ typedef enum {
HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
} HAL_CAP_INTMIT_CMD;
typedef struct {
int32_t pe_firpwr; /* FIR pwr out threshold */
int32_t pe_rrssi; /* Radar rssi thresh */
int32_t pe_height; /* Pulse height thresh */
int32_t pe_prssi; /* Pulse rssi thresh */
int32_t pe_inband; /* Inband thresh */
/* The following params are only for AR5413 and later */
u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */
u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */
u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */
HAL_BOOL pe_usefir128; /* Use the average in-band power measured over 128 cycles */
HAL_BOOL pe_blockradar; /*
* Enable to block radar check if pkt detect is done via OFDM
* weak signal detect or pkt is detected immediately after tx
* to rx transition
*/
HAL_BOOL pe_enmaxrssi; /*
* Enable to use the max rssi instead of the last rssi during
* fine gain changes for radar detection
*/
HAL_BOOL pe_extchannel; /* Enable DFS on ext channel */
} HAL_PHYERR_PARAM;
#define HAL_PHYERR_PARAM_NOVAL 65535
#define HAL_PHYERR_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
/*
* Hardware Access Layer (HAL) API.
*
@ -878,6 +910,12 @@ struct ath_hal {
HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
/* DFS functions */
void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
HAL_PHYERR_PARAM *pe);
/* Key Cache Functions */
uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);

3
sys/dev/ath/ath_hal/ah_desc.h
View File

@ -144,7 +144,7 @@ enum {
HAL_PHYERR_RADAR = 5, /* Radar detect */
HAL_PHYERR_SERVICE = 6, /* Illegal service */
HAL_PHYERR_TOR = 7, /* Transmit override receive */
/* NB: these are specific to the 5212 */
/* NB: these are specific to the 5212 and later */
HAL_PHYERR_OFDM_TIMING = 17, /* */
HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
@ -152,6 +152,7 @@ enum {
HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
HAL_PHYERR_OFDM_SERVICE = 22, /* */
HAL_PHYERR_OFDM_RESTART = 23, /* */
HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */
HAL_PHYERR_CCK_TIMING = 25, /* */
HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */

2
sys/dev/ath/ath_hal/ah_internal.h
View File

@ -200,8 +200,10 @@ typedef struct {
halRifsTxSupport : 1,
hal4AddrAggrSupport : 1,
halExtChanDfsSupport : 1,
halUseCombinedRadarRssi : 1,
halForcePpmSupport : 1,
halEnhancedPmSupport : 1,
halEnhancedDfsSupport : 1,
halMbssidAggrSupport : 1,
halBssidMatchSupport : 1,
hal4kbSplitTransSupport : 1,

2
sys/dev/ath/ath_hal/ar5212/ar5212.h
View File

@ -618,5 +618,7 @@ extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *,
extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);
extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);
extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
#endif /* _ATH_AR5212_H_ */

4
sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
View File

@ -128,6 +128,10 @@ static const struct ath_hal_private ar5212hal = {{
.ah_setDecompMask = ar5212SetDecompMask,
.ah_setCoverageClass = ar5212SetCoverageClass,
/* DFS Functions */
.ah_enableDfs = ar5212EnableDfs,
.ah_getDfsThresh = ar5212GetDfsThresh,
/* Key Cache Functions */
.ah_getKeyCacheSize = ar5212GetKeyCacheSize,
.ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry,

51
sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
View File

@ -1115,3 +1115,54 @@ ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
}
return AH_FALSE;
}
void
ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
uint32_t val;
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_FIRPWR;
val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
}
if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_RRSSI;
val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
}
if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_HEIGHT;
val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
}
if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_PRSSI;
val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
}
if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_INBAND;
val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
}
void
ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
uint32_t val,temp;
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
temp = MS(val,AR_PHY_RADAR_0_FIRPWR);
temp |= 0xFFFFFF80;
pe->pe_firpwr = temp;
pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT);
pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
pe->pe_relpwr = 0;
pe->pe_relstep = 0;
pe->pe_maxlen = 0;
pe->pe_extchannel = AH_FALSE;
}

2
sys/dev/ath/ath_hal/ar5416/ar5416.h
View File

@ -201,6 +201,8 @@ extern HAL_BOOL ar5416GetDiagState(struct ath_hal *ah, int request,
void **result, uint32_t *resultsize);
extern HAL_BOOL ar5416SetRifsDelay(struct ath_hal *ah,
const struct ieee80211_channel *chan, HAL_BOOL enable);
extern void ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern void ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
extern HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
int setChip);

5
sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
View File

@ -143,6 +143,10 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
/* DFS Functions */
ah->ah_enableDfs = ar5416EnableDfs;
ah->ah_getDfsThresh = ar5416GetDfsThresh;
/* Power Management Functions */
ah->ah_setPowerMode = ar5416SetPowerMode;
@ -878,6 +882,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
pCap->halBssidMatchSupport = AH_TRUE;
pCap->halGTTSupport = AH_TRUE;
pCap->halCSTSupport = AH_TRUE;
pCap->halEnhancedDfsSupport = AH_FALSE;
if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {

103
sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
View File

@ -560,3 +560,106 @@ ar5416DetectBBHang(struct ath_hal *ah)
#undef N
}
#undef NUM_STATUS_READS
/*
* Get the radar parameter values and return them in the pe
* structure
*/
void
ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
uint32_t val, temp;
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
temp = MS(val,AR_PHY_RADAR_0_FIRPWR);
temp |= 0xFFFFFF80;
pe->pe_firpwr = temp;
pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT);
pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
val = OS_REG_READ(ah, AR_PHY_RADAR_1);
temp = val & AR_PHY_RADAR_1_RELPWR_ENA;
pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH);
if (temp)
pe->pe_relpwr |= HAL_PHYERR_PARAM_ENABLE;
temp = val & AR_PHY_RADAR_1_RELSTEP_CHECK;
pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH);
if (temp)
pe->pe_relstep |= HAL_PHYERR_PARAM_ENABLE;
pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN);
pe->pe_extchannel = !! (OS_REG_READ(ah, AR_PHY_RADAR_EXT) &
AR_PHY_RADAR_EXT_ENA);
}
/*
* Enable radar detection and set the radar parameters per the
* values in pe
*/
void
ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{
uint32_t val;
val = OS_REG_READ(ah, AR_PHY_RADAR_0);
if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_FIRPWR;
val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
}
if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_RRSSI;
val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
}
if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_HEIGHT;
val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
}
if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_PRSSI;
val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
}
if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_0_INBAND;
val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
}
/*Enable FFT data*/
val |= AR_PHY_RADAR_0_FFT_ENA;
OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
val = OS_REG_READ(ah, AR_PHY_RADAR_1);
val |= (AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK);
if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) {
val &= ~AR_PHY_RADAR_1_MAXLEN;
val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
}
OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
/*
* Enable HT/40 if the upper layer asks;
* it should check the channel is HT/40 and HAL_CAP_EXT_CHAN_DFS
* is available.
*/
if (pe->pe_extchannel)
OS_REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
else
OS_REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) {
val = OS_REG_READ(ah, AR_PHY_RADAR_1);
val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH;
val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH);
OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
}
if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) {
val = OS_REG_READ(ah, AR_PHY_RADAR_1);
val &= ~AR_PHY_RADAR_1_RELPWR_THRESH;
val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH);
OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
}
}

19
sys/dev/ath/ath_hal/ar5416/ar5416phy.h
View File

@ -21,6 +21,25 @@
#include "ar5212/ar5212phy.h"
/* For AR_PHY_RADAR0 */
#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
#define AR_PHY_RADAR_EXT 0x9940
#define AR_PHY_RADAR_EXT_ENA 0x00004000
#define AR_PHY_RADAR_1 0x9958
#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
#define AR_PHY_RADAR_1_MAXLEN_S 0
#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */

1
sys/dev/ath/ath_hal/ar9001/ar9130_attach.c
View File

@ -289,6 +289,7 @@ ar9130FillCapabilityInfo(struct ath_hal *ah)
pCap->halRifsTxSupport = AH_TRUE;
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
pCap->halExtChanDfsSupport = AH_TRUE;
pCap->halUseCombinedRadarRssi = AH_TRUE;
pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
/*
* MBSSID aggregation is broken in Howl v1.1, v1.2, v1.3

1
sys/dev/ath/ath_hal/ar9001/ar9160_attach.c
View File

@ -293,6 +293,7 @@ ar9160FillCapabilityInfo(struct ath_hal *ah)
pCap->halRifsTxSupport = AH_TRUE;
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
pCap->halExtChanDfsSupport = AH_TRUE;
pCap->halUseCombinedRadarRssi = AH_TRUE;
pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
pCap->halMbssidAggrSupport = AH_TRUE;
pCap->hal4AddrAggrSupport = AH_TRUE;

2
sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
View File

@ -783,6 +783,7 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
pCap->halRifsTxSupport = AH_TRUE;
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
pCap->halExtChanDfsSupport = AH_TRUE;
pCap->halUseCombinedRadarRssi = AH_TRUE;
#if 0
/* XXX bluetooth */
pCap->halBtCoexSupport = AH_TRUE;
@ -804,6 +805,7 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
}
pCap->halRxStbcSupport = 1;
pCap->halTxStbcSupport = 1;
pCap->halEnhancedDfsSupport = AH_TRUE;
return AH_TRUE;
}

1
sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
View File

@ -414,6 +414,7 @@ ar9285FillCapabilityInfo(struct ath_hal *ah)
pCap->halRifsTxSupport = AH_TRUE;
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
pCap->halExtChanDfsSupport = AH_TRUE;
pCap->halUseCombinedRadarRssi = AH_TRUE;
#if 0
/* XXX bluetooth */
pCap->halBtCoexSupport = AH_TRUE;

3
sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
View File

@ -430,6 +430,7 @@ ar9287FillCapabilityInfo(struct ath_hal *ah)
pCap->halRifsTxSupport = AH_TRUE;
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
pCap->halExtChanDfsSupport = AH_TRUE;
pCap->halUseCombinedRadarRssi = AH_TRUE;
#if 0
/* XXX bluetooth */
pCap->halBtCoexSupport = AH_TRUE;
@ -447,6 +448,8 @@ ar9287FillCapabilityInfo(struct ath_hal *ah)
/* Hardware supports short-GI w/ 20MHz */
pCap->halHTSGI20Support = 1;
pCap->halEnhancedDfsSupport = AH_TRUE;
return AH_TRUE;
}

51
sys/dev/ath/if_ath.c
View File

@ -95,11 +95,13 @@ __FBSDID("$FreeBSD$");
#include <dev/ath/if_ath_tx.h>
#include <dev/ath/if_ath_sysctl.h>
#include <dev/ath/if_ath_keycache.h>
#include <dev/ath/if_athdfs.h>
#ifdef ATH_TX99_DIAG
#include <dev/ath/ath_tx99/ath_tx99.h>
#endif
/*
* ATH_BCBUF determines the number of vap's that can transmit
* beacons and also (currently) the number of vap's that can
@ -199,6 +201,8 @@ static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
static void ath_announce(struct ath_softc *);
static void ath_dfs_tasklet(void *, int);
#ifdef IEEE80211_SUPPORT_TDMA
static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
u_int32_t bintval);
@ -471,6 +475,16 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
goto bad2;
}
/* Attach DFS module */
if (! ath_dfs_attach(sc)) {
device_printf(sc->sc_dev, "%s: unable to attach DFS\n", __func__);
error = EIO;
goto bad2;
}
/* Start DFS processing tasklet */
TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
sc->sc_blinking = 0;
sc->sc_ledstate = 1;
sc->sc_ledon = 0; /* low true */
@ -771,6 +785,8 @@ ath_detach(struct ath_softc *sc)
sc->sc_tx99->detach(sc->sc_tx99);
#endif
ath_rate_detach(sc->sc_rc);
ath_dfs_detach(sc);
ath_desc_free(sc);
ath_tx_cleanup(sc);
ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
@ -1554,6 +1570,9 @@ ath_init(void *arg)
}
ath_chan_change(sc, ic->ic_curchan);
/* Let DFS at it in case it's a DFS channel */
ath_dfs_radar_enable(sc, ic->ic_curchan);
/*
* Likewise this is set during reset so update
* state cached in the driver.
@ -1699,6 +1718,10 @@ ath_reset(struct ifnet *ifp)
if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
__func__, status);
sc->sc_diversity = ath_hal_getdiversity(ah);
/* Let DFS at it in case it's a DFS channel */
ath_dfs_radar_enable(sc, ic->ic_curchan);
if (ath_startrecv(sc) != 0) /* restart recv */
if_printf(ifp, "%s: unable to start recv logic\n", __func__);
/*
@ -3441,6 +3464,9 @@ ath_rx_proc(void *arg, int npending)
sc->sc_stats.ast_rx_fifoerr++;
if (rs->rs_status & HAL_RXERR_PHY) {
sc->sc_stats.ast_rx_phyerr++;
/* Process DFS radar events */
ath_dfs_process_phy_err(sc, ds, tsf, rs);
/* Be suitably paranoid about receiving phy errors out of the stats array bounds */
if (rs->rs_phyerr < 64)
sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
@ -3682,6 +3708,10 @@ ath_rx_proc(void *arg, int npending)
if (ngood)
sc->sc_lastrx = tsf;
/* Queue DFS tasklet if needed */
if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
#ifdef IEEE80211_SUPPORT_SUPERG
ieee80211_ff_age_all(ic, 100);
@ -4399,6 +4429,9 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
}
sc->sc_diversity = ath_hal_getdiversity(ah);
/* Let DFS at it in case it's a DFS channel */
ath_dfs_radar_enable(sc, ic->ic_curchan);
/*
* Re-enable rx framework.
*/
@ -5665,5 +5698,23 @@ ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
}
#endif /* IEEE80211_SUPPORT_TDMA */
static void
ath_dfs_tasklet(void *p, int npending)
{
struct ath_softc *sc = (struct ath_softc *) p;
struct ifnet *ifp = sc->sc_ifp;
struct ieee80211com *ic = ifp->if_l2com;
/*
* If previous processing has found a radar event,
* signal this to the net80211 layer to begin DFS
* processing.
*/
if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
/* DFS event found, initiate channel change */
ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
}
}
MODULE_VERSION(if_ath, 1);
MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */

47
sys/dev/ath/if_athdfs.h Normal file
View File

@ -0,0 +1,47 @@
/*-
* Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
#ifndef __IF_ATHDFS_H__
#define __IF_ATHDFS_H__
extern int ath_dfs_attach(struct ath_softc *sc);
extern int ath_dfs_detach(struct ath_softc *sc);
extern void ath_dfs_radar_enable(struct ath_softc *,
struct ieee80211_channel *chan);
extern void ath_dfs_process_phy_err(struct ath_softc *sc, struct ath_desc *ds,
uint64_t tsf, struct ath_rx_status *rxstat);
extern int ath_dfs_process_radar_event(struct ath_softc *sc,
struct ieee80211_channel *chan);
extern int ath_dfs_tasklet_needed(struct ath_softc *sc,
struct ieee80211_channel *chan);
extern int ath_ioctl_phyerr(struct ath_softc *sc, struct ath_diag *ad);
extern int ath_dfs_get_thresholds(struct ath_softc *sc, HAL_PHYERR_PARAM *param);
#endif /* __IF_ATHDFS_H__ */

15
sys/dev/ath/if_athvar.h
View File

@ -357,6 +357,10 @@ struct ath_softc {
uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */
int sc_txchainmask; /* currently configured TX chainmask */
int sc_rxchainmask; /* currently configured RX chainmask */
/* DFS related state */
void *sc_dfs; /* Used by an optional DFS module */
struct task sc_dfstask; /* DFS processing task */
};
#define ATH_LOCK_INIT(_sc) \
@ -694,6 +698,17 @@ void ath_intr(void *);
#define ath_hal_set11nburstduration(_ah, _ds, _dur) \
((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
/*
* This is badly-named; you need to set the correct parameters
* to begin to receive useful radar events; and even then
* it doesn't "enable" DFS. See the ath_dfs/null/ module for
* more information.
*/
#define ath_hal_enabledfs(_ah, _param) \
((*(_ah)->ah_enableDfs)((_ah), (_param)))
#define ath_hal_getdfsthresh(_ah, _param) \
((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
#define ath_hal_gpioset(_ah, _gpio, _b) \

2
sys/dev/ixgbe/LICENSE
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
Copyright (c) 2001-2011, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without

245
sys/dev/ixgbe/README
View File

@ -1,8 +1,8 @@
FreeBSD Driver for 10 Gigabit PCI Express Server Adapters
=============================================
FreeBSD Driver for Intel(R) Ethernet 10 Gigabit PCI Express Server Adapters
============================================================================
/*$FreeBSD$*/
May 14, 2008
November 12, 2010
Contents
@ -11,15 +11,15 @@ Contents
- Overview
- Supported Adapters
- Building and Installation
- Additional Configurations
- Additional Configurations and Tuning
- Known Limitations
Overview
========
This file describes the FreeBSD* driver for the 10 Gigabit PCIE Family of
Adapters. Drivers has been developed for use with FreeBSD 7 or later.
This file describes the FreeBSD* driver for the Intel(R) Ethernet 10 Gigabit
Family of Adapters. Driver has been developed for use with FreeBSD 7.2 or later.
For questions related to hardware requirements, refer to the documentation
supplied with your Intel 10GbE adapter. All hardware requirements listed
@ -29,100 +29,98 @@ apply to use with FreeBSD.
Supported Adapters
==================
The following Intel network adapters are compatible with the drivers in this
release:
Controller Adapter Name Physical Layer
---------- ------------ --------------
82598EB Intel(R) 10 Gigabit XF SR/AF 10G Base -LR (850 nm optical fiber)
Dual Port Server Adapter 10G Base -SR (1310 nm optical fiber)
82598EB Intel(R) 10 Gigabit XF SR/LR
Server Adapter
Intel(R) 82598EB 10 Gigabit AF
Network Connection
Intel(R) 82598EB 10 Gigabit AT
CX4 Network Connection
The driver in this release is compatible with 82598 and 82599-based Intel
Network Connections.
SFP+ Devices with Pluggable Optics
----------------------------------
Building and Installation
=========================
82599-BASED ADAPTERS
NOTE: You must have kernel sources installed in order to compile the driver
module.
NOTE: If your 82599-based Intel(R) Ethernet Network Adapter came with Intel
optics, or is an Intel(R) Ethernet Server Adapter X520-2, then it only supports
Intel optics and/or the direct attach cables listed below.
In the instructions below, x.x.x is the driver version as indicated in
the name of the driver tar.
When 82599-based SFP+ devices are connected back to back, they should be set to
the same Speed setting via Ethtool. Results may vary if you mix speed settings.
Supplier Type Part Numbers
1. Move the base driver tar file to the directory of your choice. For
example, use /home/username/ixgbe or /usr/local/src/ixgbe.
SR Modules
Intel DUAL RATE 1G/10G SFP+ SR (bailed) FTLX8571D3BCV-IT
Intel DUAL RATE 1G/10G SFP+ SR (bailed) AFBR-703SDZ-IN2
Intel DUAL RATE 1G/10G SFP+ SR (bailed) AFBR-703SDDZ-IN1
LR Modules
Intel DUAL RATE 1G/10G SFP+ LR (bailed) FTLX1471D3BCV-IT
Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDZ-IN2
Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDDZ-IN1
2. Untar/unzip the archive:
tar xfz ixgbe-x.x.x.tar.gz
The following is a list of 3rd party SFP+ modules and direct attach cables that
have received some testing. Not all modules are applicable to all devices.
3. To install man page:
cd ixgbe-x.x.x
gzip -c ixgbe.4 > /usr/share/man/man4/ixgbee.4.gz
Supplier Type Part Numbers
4. To load the driver onto a running system:
cd ixgbe-x.x.x/src
make load
Finisar SFP+ SR bailed, 10g single rate FTLX8571D3BCL
Avago SFP+ SR bailed, 10g single rate AFBR-700SDZ
Finisar SFP+ LR bailed, 10g single rate FTLX8571D3BCV-IT
Finisar DUAL RATE 1G/10G SFP+ SR (No Bail) FTLX8571D3QCV-IT
Avago DUAL RATE 1G/10G SFP+ SR (No Bail) AFBR-703SDZ-IN1
Finisar DUAL RATE 1G/10G SFP+ LR (No Bail) FTLX1471D3QCV-IT
Avago DUAL RATE 1G/10G SFP+ LR (No Bail) AFCT-701SDZ-IN1
Finistar 1000BASE-T SFP FCLF8522P2BTL
Avago 1000BASE-T SFP ABCU-5710RZ
82599-based adapters support all passive and active limiting direct attach
cables that comply with SFF-8431 v4.1 and SFF-8472 v10.4 specifications.
5. To assign an IP address to the interface, enter the following:
ifconfig ix<interface_num> <IP_address>
Laser turns off for SFP+ when ifconfig down
--------------------------------------------------------
"ifconfig down" turns off the laser for 82599-based SFP+ fiber adapters.
"ifconfig up" turns on the later.
6. Verify that the interface works. Enter the following, where <IP_address>
is the IP address for another machine on the same subnet as the interface
that is being tested:
ping <IP_address>
82598-BASED ADAPTERS
7. If you want the driver to load automatically when the system is booted:
NOTES for 82598-Based Adapters:
- Intel(R) Ethernet Network Adapters that support removable optical modules
only support their original module type (i.e., the Intel(R) 10 Gigabit SR
Dual Port Express Module only supports SR optical modules). If you plug
in a different type of module, the driver will not load.
- Hot Swapping/hot plugging optical modules is not supported.
- Only single speed, 10 gigabit modules are supported.
- LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
types are not supported. Please see your system documentation for details.
cd ixgbe-x.x.x/src
make
make install
Edit /boot/loader.conf, and add the following line:
ixgbe_load="YES"
The following is a list of 3rd party SFP+ modules and direct attach cables that have
received some testing. Not all modules are applicable to all devices.
OR
Supplier Type Part Numbers
compile the driver into the kernel (see item 8).
Edit /etc/rc.conf, and create the appropriate ifconfig_ixgbe<interface_num>
entry:
ifconfig_ix<interface_num>="<ifconfig_settings>"
Example usage:
ifconfig_ix0="inet 192.168.10.1 netmask 255.255.255.0"
NOTE: For assistance, see the ifconfig man page.
8. If you want to compile the driver into the kernel, enter:
FreeBSD 7 or later:
cd ixgbe-x.x.x/src
cp *.[ch] /usr/src/sys/dev/ixgbe
cp Makefile.kernel /usr/src/sys/modules/ixgbe/Makefile
Edit the kernel configuration file (i.e., GENERIC or MYKERNEL) in
/usr/src/sys/i386/conf (replace "i386" with the appropriate system
architecture if necessary), and ensure the following line is present:
device ixgbe
Compile and install the kernel. The system must be reboot for the kernel
updates to take affect. For additional information on compiling the kernel,
consult the FreeBSD operating system documentation.
Finisar SFP+ SR bailed, 10g single rate FTLX8571D3BCL
Avago SFP+ SR bailed, 10g single rate AFBR-700SDZ
Finisar SFP+ LR bailed, 10g single rate FTLX1471D3BCL
82598-based adapters support all passive direct attach cables that comply
with SFF-8431 v4.1 and SFF-8472 v10.4 specifications. Active direct attach
cables are not supported.
Third party optic modules and cables referred to above are listed only for the
purpose of highlighting third party specifications and potential compatibility,
and are not recommendations or endorsements or sponsorship of any third party's
product by Intel. Intel is not endorsing or promoting products made by any
third party and the third party reference is provided only to share information
regarding certain optic modules and cables with the above specifications. There
may be other manufacturers or suppliers, producing or supplying optic modules
and cables with similar or matching descriptions. Customers must use their own
discretion and diligence to purchase optic modules and cables from any third
party of their choice. Customer are solely responsible for assessing the
suitability of the product and/or devices and for the selection of the vendor
for purchasing any product. INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
SUCH THIRD PARTY PRODUCTS OR SELECTION OF VENDOR BY CUSTOMERS.
Configuration and Tuning
=========================
========================
The driver supports Transmit/Receive Checksum Offload and Jumbo Frames on
all 10 Gigabit adapters.
@ -143,7 +141,7 @@ all 10 Gigabit adapters.
The Jumbo Frames MTU range for Intel Adapters is 1500 to 16114. The default
MTU range is 1500. To modify the setting, enter the following:
ifconfig ix <interface_num> <hostname or IP address> mtu 9000
ifconfig ix<interface_num> <hostname or IP address> mtu 9000
To confirm an interface's MTU value, use the ifconfig command. To confirm
the MTU used between two specific devices, use:
@ -200,6 +198,8 @@ all 10 Gigabit adapters.
TSO
---
TSO is enabled by default.
To disable:
ifconfig <interface_num> -tso
@ -209,23 +209,21 @@ all 10 Gigabit adapters.
ifconfig <interface_num> tso
LRO
___
---
Large Receive Offload is available in version 1.4.4, it is on
by default. It can be toggled off and on by using:
sysctl dev.ix.X.enable_lro=[0,1]
Large Receive Offload is available in the driver; it is on by default.
It can be disabled by using:
ifconfig <interface_num> -lro
To enable:
ifconfig <interface_num> lro
NOTE: when changing this feature you MUST be sure the interface
is reinitialized, it is easy to do this with ifconfig down/up.
The LRO code will ultimately move into the kernel stack code,
but for this first release it was included with the driver.
Important system configuration changes:
---------------------------------------
When there is a choice run on a 64bit OS rather than 32, it makes
a significant difference in improvement.
When there is a choice run on a 64bit OS rather than 32, it makes a
significant difference in improvement.
The default scheduler SCHED_4BSD is not smart about SMP locality issues.
Significant improvement can be achieved by switching to the ULE scheduler.
@ -233,34 +231,79 @@ all 10 Gigabit adapters.
SCHED_ULE. Note that this is only advisable on FreeBSD 7, on 6.X there have
been stability problems with ULE.
Change the file /etc/sysctl.conf, add the line:
The interface can generate high number of interrupts. To avoid running
into the limit set by the kernel, adjust hw.intr_storm_threshold
setting using sysctl:
hw.intr_storm_threshold: 8000 (the default is 1000)
sysctl hw.intr_storm_threshold=9000 (the default is 1000)
For this change to take effect on boot, edit /etc/sysctl.conf and add the
line:
hw.intr_storm_threshold=9000
If you still see Interrupt Storm detected messages, increase the limit to a
higher number.
Best throughput results are seen with a large MTU; use 9000 if possible.
The default number of descriptors is 256, increasing this to 1024 or even
2048 may improve performance.
The default number of descriptors is 1024, increasing this to 2K or even
4K may improve performance in some workloads, but change carefully.
Known Limitations
=================
For known hardware and troubleshooting issues, refer to the following website.
http://support.intel.com/support/go/network/adapter/home.htm
Either select the link for your adapter or perform a search for the adapter
number. The adapter's page lists many issues. For a complete list of hardware
issues download your adapter's user guide and read the Release Notes.
UDP stress test with 10GbE driver
---------------------------------
Under small packets UDP stress test with 10GbE driver, the FreeBSD system
will drop UDP packets due to the fullness of socket buffers. You may want
to change the driver's Flow Control variables to the minimum value for
controlling packet reception.
Attempting to configure larger MTUs with a large numbers of processors may
generate the error message "ix0:could not setup receive structures"
--------------------------------------------------------------------------
When using the ixgbe driver with RSS autoconfigured based on the number of
cores (the default setting) and that number is larger than 4, increase the
memory resources allocated for the mbuf pool as follows:
Add to the sysctl.conf file for the system:
kern.ipc.nmbclusters=262144
kern.ipc.nmbjumbop=262144
Lower than expected performance on dual port 10GbE devices
----------------------------------------------------------
Some PCI-E x8 slots are actually configured as x4 slots. These slots have
insufficient bandwidth for full 10Gbe line rate with dual port 10GbE devices.
The driver can detect this situation and will write the following message in
the system log: "PCI-Express bandwidth available for this card is not
sufficient for optimal performance. For optimal performance a x8 PCI-Express
slot is required."
If this error occurs, moving your adapter to a true x8 slot will resolve the
issue.
Support
=======
For general information and support, go to the Intel support website at:
http://support.intel.com
www.intel.com/support/
If an issue is identified with the released source code on the supported
kernel with a supported adapter, email the specific information related to
the issue to freebsd@intel.com.
the issue to freebsd@intel.com

79
sys/dev/ixgbe/ixgbe.c
View File

@ -34,6 +34,7 @@
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_inet.h"
#include "opt_inet6.h"
#endif
#include "ixgbe.h"
@ -46,7 +47,7 @@ int ixgbe_display_debug_stats = 0;
/*********************************************************************
* Driver version
*********************************************************************/
char ixgbe_driver_version[] = "2.3.10";
char ixgbe_driver_version[] = "2.3.11";
/*********************************************************************
* PCI Device ID Table
@ -318,7 +319,7 @@ static int fdir_pballoc = 1;
* ixgbe_probe determines if the driver should be loaded on
* adapter based on PCI vendor/device id of the adapter.
*
* return 0 on success, positive on failure
* return BUS_PROBE_DEFAULT on success, positive on failure
*********************************************************************/
static int
@ -357,7 +358,7 @@ ixgbe_probe(device_t dev)
ixgbe_driver_version);
device_set_desc_copy(dev, adapter_name);
++ixgbe_total_ports;
return (0);
return (BUS_PROBE_DEFAULT);
}
ent++;
}
@ -385,6 +386,11 @@ ixgbe_attach(device_t dev)
INIT_DEBUGOUT("ixgbe_attach: begin");
if (resource_disabled("ixgbe", device_get_unit(dev))) {
device_printf(dev, "Disabled by device hint\n");
return (ENXIO);
}
/* Allocate, clear, and link in our adapter structure */
adapter = device_get_softc(dev);
adapter->dev = adapter->osdep.dev = dev;
@ -862,8 +868,9 @@ ixgbe_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
{
struct adapter *adapter = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
#ifdef INET
#if defined(INET) || defined(INET6)
struct ifaddr *ifa = (struct ifaddr *)data;
bool avoid_reset = FALSE;
#endif
int error = 0;
@ -871,26 +878,28 @@ ixgbe_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
case SIOCSIFADDR:
#ifdef INET
if (ifa->ifa_addr->sa_family == AF_INET) {
/*
* Since resetting hardware takes a very long time
* and results in link renegotiation we only
* initialize the hardware only when it is absolutely
* required.
*/
if (ifa->ifa_addr->sa_family == AF_INET)
avoid_reset = TRUE;
#endif
#ifdef INET6
if (ifa->ifa_addr->sa_family == AF_INET6)
avoid_reset = TRUE;
#endif
#if defined(INET) || defined(INET6)
/*
** Calling init results in link renegotiation,
** so we avoid doing it when possible.
*/
if (avoid_reset) {
ifp->if_flags |= IFF_UP;
if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
IXGBE_CORE_LOCK(adapter);
ixgbe_init_locked(adapter);
IXGBE_CORE_UNLOCK(adapter);
}
if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
ixgbe_init(adapter);
if (!(ifp->if_flags & IFF_NOARP))
arp_ifinit(ifp, ifa);
} else
#endif
error = ether_ioctl(ifp, command, data);
break;
#endif
case SIOCSIFMTU:
IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)");
if (ifr->ifr_mtu > IXGBE_MAX_FRAME_SIZE - ETHER_HDR_LEN) {
@ -951,6 +960,8 @@ ixgbe_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
if (mask & IFCAP_VLAN_HWFILTER)
ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
if (mask & IFCAP_VLAN_HWTSO)
ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
IXGBE_CORE_LOCK(adapter);
ixgbe_init_locked(adapter);
@ -1338,7 +1349,7 @@ ixgbe_legacy_irq(void *arg)
/*********************************************************************
*
* MSI Queue Interrupt Service routine
* MSIX Queue Interrupt Service routine
*
**********************************************************************/
void
@ -1357,6 +1368,17 @@ ixgbe_msix_que(void *arg)
IXGBE_TX_LOCK(txr);
more_tx = ixgbe_txeof(txr);
/*
** Make certain that if the stack
** has anything queued the task gets
** scheduled to handle it.
*/
#if __FreeBSD_version < 800000
if (!IFQ_DRV_IS_EMPTY(&adapter->ifp->if_snd))
#else
if (!drbr_empty(adapter->ifp, txr->br))
#endif
more_tx = 1;
IXGBE_TX_UNLOCK(txr);
/* Do AIM now? */
@ -1570,7 +1592,7 @@ ixgbe_xmit(struct tx_ring *txr, struct mbuf **m_headp)
struct mbuf *m_head;
bus_dma_segment_t segs[adapter->num_segs];
bus_dmamap_t map;
struct ixgbe_tx_buf *txbuf, *txbuf_mapped;
struct ixgbe_tx_buf *txbuf;
union ixgbe_adv_tx_desc *txd = NULL;
m_head = *m_headp;
@ -1589,7 +1611,6 @@ ixgbe_xmit(struct tx_ring *txr, struct mbuf **m_headp)
*/
first = txr->next_avail_desc;
txbuf = &txr->tx_buffers[first];
txbuf_mapped = txbuf;
map = txbuf->map;
/*
@ -1708,6 +1729,8 @@ ixgbe_xmit(struct tx_ring *txr, struct mbuf **m_headp)
txr->next_avail_desc = i;
txbuf->m_head = m_head;
/* Swap the dma map between the first and last descriptor */
txr->tx_buffers[first].map = txbuf->map;
txbuf->map = map;
bus_dmamap_sync(txr->txtag, map, BUS_DMASYNC_PREWRITE);
@ -2265,7 +2288,9 @@ ixgbe_setup_msix(struct adapter *adapter)
msi:
msgs = pci_msi_count(dev);
if (msgs == 1 && pci_alloc_msi(dev, &msgs) == 0)
device_printf(adapter->dev,"Using MSI interrupt\n");
device_printf(adapter->dev,"Using an MSI interrupt\n");
else
device_printf(adapter->dev,"Using a Legacy interrupt\n");
return (msgs);
}
@ -2412,19 +2437,21 @@ ixgbe_setup_interface(device_t dev, struct adapter *adapter)
ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4 | IFCAP_VLAN_HWCSUM;
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
ifp->if_capabilities |= IFCAP_JUMBO_MTU;
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
| IFCAP_VLAN_HWTSO
| IFCAP_VLAN_MTU;
ifp->if_capenable = ifp->if_capabilities;
/* Don't enable LRO by default */
ifp->if_capabilities |= IFCAP_LRO;
/*
** Dont turn this on by default, if vlans are
** Don't turn this on by default, if vlans are
** created on another pseudo device (eg. lagg)
** then vlan events are not passed thru, breaking
** operation, but with HW FILTER off it works. If
** using vlans directly on the em driver you can
** using vlans directly on the ixgbe driver you can
** enable this and get full hardware tag filtering.
*/
ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
@ -5333,7 +5360,7 @@ ixgbe_add_rx_process_limit(struct adapter *adapter, const char *name,
static int
ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
{
int error;
int error = 0;
struct adapter *adapter;
struct ixgbe_hw *hw;
ixgbe_link_speed speed, last;

58
sys/dev/ixgbe/ixv.c
View File

@ -1,6 +1,6 @@
/******************************************************************************
Copyright (c) 2001-2010, Intel Corporation
Copyright (c) 2001-2011, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -33,7 +33,8 @@
/*$FreeBSD$*/
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
#include "opt_inet.h"
#include "opt_inet6.h"
#endif
#include "ixv.h"
@ -41,7 +42,7 @@
/*********************************************************************
* Driver version
*********************************************************************/
char ixv_driver_version[] = "1.0.0";
char ixv_driver_version[] = "1.0.1";
/*********************************************************************
* PCI Device ID Table
@ -234,7 +235,7 @@ static u32 ixv_shadow_vfta[VFTA_SIZE];
* ixv_probe determines if the driver should be loaded on
* adapter based on PCI vendor/device id of the adapter.
*
* return 0 on success, positive on failure
* return BUS_PROBE_DEFAULT on success, positive on failure
*********************************************************************/
static int
@ -271,7 +272,7 @@ ixv_probe(device_t dev)
ixv_strings[ent->index],
ixv_driver_version);
device_set_desc_copy(dev, adapter_name);
return (0);
return (BUS_PROBE_DEFAULT);
}
ent++;
}
@ -297,6 +298,11 @@ ixv_attach(device_t dev)
INIT_DEBUGOUT("ixv_attach: begin");
if (resource_disabled("ixgbe", device_get_unit(dev))) {
device_printf(dev, "Disabled by device hint\n");
return (ENXIO);
}
/* Allocate, clear, and link in our adapter structure */
adapter = device_get_softc(dev);
adapter->dev = adapter->osdep.dev = dev;
@ -690,10 +696,38 @@ ixv_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
{
struct adapter *adapter = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
#if defined(INET) || defined(INET6)
struct ifaddr *ifa = (struct ifaddr *) data;
bool avoid_reset = FALSE;
#endif
int error = 0;
switch (command) {
case SIOCSIFADDR:
#ifdef INET
if (ifa->ifa_addr->sa_family == AF_INET)
avoid_reset = TRUE;
#endif
#ifdef INET6
if (ifa->ifa_addr->sa_family == AF_INET6)
avoid_reset = TRUE;
#endif
#if defined(INET) || defined(INET6)
/*
** Calling init results in link renegotiation,
** so we avoid doing it when possible.
*/
if (avoid_reset) {
ifp->if_flags |= IFF_UP;
if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
ixv_init(adapter);
if (!(ifp->if_flags & IFF_NOARP))
arp_ifinit(ifp, ifa);
} else
error = ether_ioctl(ifp, command, data);
break;
#endif
case SIOCSIFMTU:
IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)");
if (ifr->ifr_mtu > IXV_MAX_FRAME_SIZE - ETHER_HDR_LEN) {
@ -1161,7 +1195,7 @@ ixv_xmit(struct tx_ring *txr, struct mbuf **m_headp)
struct mbuf *m_head;
bus_dma_segment_t segs[32];
bus_dmamap_t map;
struct ixv_tx_buf *txbuf, *txbuf_mapped;
struct ixv_tx_buf *txbuf;
union ixgbe_adv_tx_desc *txd = NULL;
m_head = *m_headp;
@ -1180,7 +1214,6 @@ ixv_xmit(struct tx_ring *txr, struct mbuf **m_headp)
*/
first = txr->next_avail_desc;
txbuf = &txr->tx_buffers[first];
txbuf_mapped = txbuf;
map = txbuf->map;
/*
@ -1283,6 +1316,7 @@ ixv_xmit(struct tx_ring *txr, struct mbuf **m_headp)
txr->next_avail_desc = i;
txbuf->m_head = m_head;
txr->tx_buffers[first].map = txbuf->map;
txbuf->map = map;
bus_dmamap_sync(txr->txtag, map, BUS_DMASYNC_PREWRITE);
@ -1820,11 +1854,15 @@ ixv_setup_interface(device_t dev, struct adapter *adapter)
ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4 | IFCAP_VLAN_HWCSUM;
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
ifp->if_capabilities |= IFCAP_JUMBO_MTU | IFCAP_LRO;
ifp->if_capabilities |= IFCAP_JUMBO_MTU;
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
| IFCAP_VLAN_HWTSO
| IFCAP_VLAN_MTU;
ifp->if_capenable = ifp->if_capabilities;
/* Don't enable LRO by default */
ifp->if_capabilities |= IFCAP_LRO;
/*
* Specify the media types supported by this adapter and register
* callbacks to update media and link information

18
sys/dev/mfi/mfi.c
View File

@ -788,7 +788,7 @@ mfi_aen_setup(struct mfi_softc *sc, uint32_t seq_start)
class_locale.members.reserved = 0;
class_locale.members.locale = mfi_event_locale;
class_locale.members.class = mfi_event_class;
class_locale.members.evt_class = mfi_event_class;
if (seq_start == 0) {
error = mfi_get_log_state(sc, &log_state);
@ -1082,8 +1082,8 @@ mfi_decode_evt(struct mfi_softc *sc, struct mfi_evt_detail *detail)
{
device_printf(sc->mfi_dev, "%d (%s/0x%04x/%s) - %s\n", detail->seq,
format_timestamp(detail->time), detail->class.members.locale,
format_class(detail->class.members.class), detail->description);
format_timestamp(detail->time), detail->evt_class.members.locale,
format_class(detail->evt_class.members.evt_class), detail->description);
}
static int
@ -1099,16 +1099,16 @@ mfi_aen_register(struct mfi_softc *sc, int seq, int locale)
if (sc->mfi_aen_cm != NULL) {
prior_aen.word =
((uint32_t *)&sc->mfi_aen_cm->cm_frame->dcmd.mbox)[1];
if (prior_aen.members.class <= current_aen.members.class &&
if (prior_aen.members.evt_class <= current_aen.members.evt_class &&
!((prior_aen.members.locale & current_aen.members.locale)
^current_aen.members.locale)) {
return (0);
} else {
prior_aen.members.locale |= current_aen.members.locale;
if (prior_aen.members.class
< current_aen.members.class)
current_aen.members.class =
prior_aen.members.class;
if (prior_aen.members.evt_class
< current_aen.members.evt_class)
current_aen.members.evt_class =
prior_aen.members.evt_class;
mfi_abort(sc, sc->mfi_aen_cm);
}
}
@ -1199,7 +1199,7 @@ mfi_parse_entries(struct mfi_softc *sc, int start_seq, int stop_seq)
class_locale.members.reserved = 0;
class_locale.members.locale = mfi_event_locale;
class_locale.members.class = mfi_event_class;
class_locale.members.evt_class = mfi_event_class;
size = sizeof(struct mfi_evt_list) + sizeof(struct mfi_evt_detail)
* (MAX_EVENTS - 1);

4
sys/dev/mfi/mfireg.h
View File

@ -719,7 +719,7 @@ union mfi_evt {
struct {
uint16_t locale;
uint8_t reserved;
int8_t class;
int8_t evt_class;
} members;
uint32_t word;
} __packed;
@ -755,7 +755,7 @@ struct mfi_evt_detail {
uint32_t seq;
uint32_t time;
uint32_t code;
union mfi_evt class;
union mfi_evt evt_class;
uint8_t arg_type;
uint8_t reserved1[15];

21
sys/dev/usb/net/if_axe.c
View File

@ -514,7 +514,7 @@ static void
axe_ax88178_init(struct axe_softc *sc)
{
struct usb_ether *ue;
int gpio0, phymode;
int gpio0, ledmode, phymode;
uint16_t eeprom, val;
ue = &sc->sc_ue;
@ -528,9 +528,11 @@ axe_ax88178_init(struct axe_softc *sc)
if (eeprom == 0xffff) {
phymode = AXE_PHY_MODE_MARVELL;
gpio0 = 1;
ledmode = 0;
} else {
phymode = eeprom & 0x7f;
gpio0 = (eeprom & 0x80) ? 0 : 1;
ledmode = eeprom >> 8;
}
if (bootverbose)
@ -548,9 +550,22 @@ axe_ax88178_init(struct axe_softc *sc)
AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
hz / 32);
} else
} else {
AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
AXE_GPIO1_EN, hz / 32);
AXE_GPIO1_EN, hz / 3);
if (ledmode == 1) {
AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
hz / 3);
} else {
AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
AXE_GPIO2_EN, hz / 4);
AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
}
}
break;
case AXE_PHY_MODE_CICADA:
case AXE_PHY_MODE_CICADA_V2:

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/* $FreeBSD$ */
/*-
* Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _UMCS7840_H_
#define _UMCS7840_H_
#define UMCS7840_MAX_PORTS 4
#define UMCS7840_READ_LENGTH 1 /* bytes */
#define UMCS7840_CTRL_TIMEOUT 500 /* ms */
/* Read/Wrtire registers vendor commands */
#define MCS7840_RDREQ 0x0d
#define MCS7840_WRREQ 0x0e
/* Read/Wrtie EEPROM values */
#define MCS7840_EEPROM_RW_WVALUE 0x0900
/*
* All these registers are documented only in full datasheet,
* which can be requested from MosChip tech support.
*/
#define MCS7840_DEV_REG_SP1 0x00 /* Options for for UART 1, R/W */
#define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
* R/W */
#define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
* register, R/W */
#define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
* register, R/W */
/* DCRx_1 Registers goes here (see below, they are documented) */
#define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits,
* undocumented, see notes
* below R/W */
#define MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */
#define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
* R/W */
#define MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */
#define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3,
* R/W */
#define MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */
#define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
* R/W */
#define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
#define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
#define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt
* endpoint control, R/W */
#define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 &
* 2, R/W */
#define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 &
* 4, R/W */
#define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */
/* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
#define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration,
* R/Only */
#define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap
* configuration for Port 1,
* R/W */
#define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap
* configuration for Port 2,
* R/W */
#define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap
* configuration for Port 3,
* R/W */
#define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap
* configuration for Port 4,
* R/W */
#define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 &
* 2, R/W */
#define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 &
* 4, R/W */
#define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
* 1, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
* 1, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
* 2, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port
* 2, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port
* 3, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port
* 3, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port
* 4, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port
* 4, contains number of
* availiable bytes, R/Only */
#define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out
* frames for Port 1, R/W */
#define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out
* frames for Port 1, R/W */
#define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out
* frames for Port 1, R/W */
#define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out
* frames for Port 1, R/W */
#define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out
* frames, R/W */
#define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshhold
* value for Bulk-Out for Port
* 1, R/W */
#define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshhold
* value for Bulk-Out and
* enable flag for Port 1, R/W */
#define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshhold
* value for Bulk-Out for Port
* 2, R/W */
#define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshhold
* value for Bulk-Out and
* enable flag for Port 2, R/W */
#define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshhold
* value for Bulk-Out for Port
* 3, R/W */
#define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshhold
* value for Bulk-Out and
* enable flag for Port 3, R/W */
#define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshhold
* value for Bulk-Out for Port
* 4, R/W */
#define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshhold
* value for Bulk-Out and
* enable flag for Port 4, R/W */
/* Bits for SPx registers */
#define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the
* Bulk-In FIFO, default = 0 */
#define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART,
* which were recevied with
* errors, default = 0 */
#define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */
#define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */
#define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK
* source */
#define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed
* = 115200 bps, default */
#define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed
* = 230400 bps */
#define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed
* = 403200 bps */
#define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed
* = 460800 bps */
#define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed
* = 806400 bps */
#define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed
* = 921600 bps */
#define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed
* = 1.5 Mbps */
#define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed
* = 3.0 Mbps */
#define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted
* to get clock value */
#define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */
/* Bits for CONTROLx registers */
#define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow
* control (when power
* down? It is unclear
* in documents),
* default = 0 */
#define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */
#define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are
* translated to MSR,
* default = 0 */
#define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports
* 2,3,4 */
#define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is
* finished, USB
* enumeration memory
* can be used as FIFOs */
#define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input,
* works for IrDA mode
* only, default = 0 */
#define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic,
* works only for
* RS-232/RS-485 mode,
* default = 0 */
#define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when
* TX is in progress,
* works for IrDA mode
* only, default = 0 */
#define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */
/*
* Bits for PINPONGx registers
* These registers control how often two input buffers
* for Bulk-In FIFOs are swapped. One of buffers is used
* for USB trnasfer, other for receiving data from UART.
* Exact meaning of 15 bit value in these registers is unknown
*/
#define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW
* register */
#define MCS7840_DEV_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW
* register */
/*
* THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support
* confirms, that it is register for GPIO_0 and GPIO_1 data input/output.
* Chips has 2 GPIO, but first one (lower bit) MUST be used by device
* authors as "number of port" indicator, grounded (0) for two-port
* devices and pulled-up to 1 for 4-port devices.
*/
#define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports
* configured */
#define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */
#define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */
/*
* Constants for PLL dividers
* Ouptut frequency of PLL is:
* Fout = (N/M) * Fin.
* Default PLL input frequency Fin is 12Mhz (on-chip).
*/
#define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M
* divider */
#define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */
#define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is
* forbidden */
#define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */
#define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */
#define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N
* divider */
#define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */
#define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is
* forbidden */
#define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */
#define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */
/* Bits for CLOCK_MUX register */
#define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock
* input */
#define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */
#define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended)
* PLL input */
#define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */
#define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */
#define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is
* 20MHz-100MHz (default), 1 =
* 100MHz-300MHz range */
#define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes
* fro Interrupt USB pipe with
* USB FIFOs statuses, default
* = 0 */
#define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */
#define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */
#define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */
#define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */
/* Bits for CLOCK_SELECTxx registers */
#define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in
* CLOCK_SELECT12 */
#define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in
* CLOCK_SELECT12 */
#define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in
* CLOCK_SELECT12 */
#define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in
* CLOCK_SELECT12 */
#define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in
* CLOCK_SELECT23 */
#define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in
* CLOCK_SELECT23 */
#define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in
* CLOCK_SELECT23 */
#define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in
* CLOCK_SELECT23 */
#define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived
* from 96Mhz, default for all
* ports */
#define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */
#define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */
#define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */
#define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N
* dividers) */
#define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input
* (device-dependend) */
#define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */
#define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */
/* Bits for MODE register */
#define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */
#define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High
* (default), 1: Reserved (?) */
#define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use
* hardocded values (default)
* (?) */
#define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed,
* default = 0 */
#define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is
* bypassed, default = 0 */
#define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA
* active, 1: 2 Serial Ports /
* IrDA active */
#define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled,
* default */
#define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated
* (could be turned on),
* default */
/* Bits for SPx ICG */
#define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as
* number of BAUD clocks of
* pause */
/*
* Bits for RX_SAMPLINGxx registers
* These registers control when bit value will be sampled within
* the baud period.
* 0 is very beginning of period, 15 is very end, 7 is the middle.
*/
#define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in
* RX_SAMPLING12 */
#define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in
* RX_SAMPLING12 */
#define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in
* RX_SAMPLING12 */
#define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in
* RX_SAMPLING12 */
#define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in
* RX_SAMPLING23 */
#define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in
* RX_SAMPLING23 */
#define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in
* RX_SAMPLING23 */
#define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in
* RX_SAMPLING23 */
#define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */
#define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX
* Sampling, center of period */
#define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */
/* Bits for ZERO_PERIODx */
#define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests
* befor sending zero-sized
* reply */
/* Bits for ZERO_ENABLE */
#define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending
* zero-sized replies for port
* 1, default */
#define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending
* zero-sized replies for port
* 2, default */
#define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending
* zero-sized replies for port
* 3, default */
#define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending
* zero-sized replies for port
* 4, default */
/* Bits for THR_VAL_HIGHx */
#define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */
#define MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */
#define MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */
#define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */
/* These are documented in "public" datasheet */
#define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port
* 1, R/W */
#define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port
* 1, R/W */
#define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port
* 1, R/W */
#define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port
* 2, R/W */
#define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port
* 2, R/W */
#define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port
* 2, R/W */
#define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port
* 3, R/W */
#define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port
* 3, R/W */
#define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port
* 3, R/W */
#define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port
* 4, R/W */
#define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port
* 4, R/W */
#define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port
* 4, R/W */
/* Bits of DCR0 registers, documented in datasheet */
#define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver
* when USB Suspend is
* engaged, default = 1 */
#define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */
#define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS
* ONLY FOR PORT 1 */
#define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input
* (0b00), WORKS ONLY
* FOR PORT 1 */
#define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input
* (0b10), WORKS ONLY
* FOR PORT 1 */
#define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH,
* default = 0 (low) */
#define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by
* state of TX buffer,
* default = 0
* (controlled by MCR) */
#define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */
#define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */
/* Bits of DCR1 registers, documented in datasheet */
#define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO
* current value, WORKS
* ONLY FOR PORT 1 */
#define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current
* 6mA, WORKS ONLY FOR
* PORT 1 */
#define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current
* 8mA, defauilt, WORKS
* ONLY FOR PORT 1 */
#define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current
* 10mA, WORKS ONLY FOR
* PORT 1 */
#define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current
* 12mA, WORKS ONLY FOR
* PORT 1 */
#define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART
* signals current value */
#define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current
* 6mA */
#define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current
* 8mA, defauilt */
#define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current
* 10mA */
#define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current
* 12mA */
#define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB
* Wakeup */
#define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power
* down when not needed,
* WORKS ONLY FOR PORT 1 */
#define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of
* interrupt data, with
* FIFO statistics,
* WORKS ONLY FOR PORT 1 */
#define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */
/*
* Bits of DCR2 registers, documented in datasheet
* Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and
* DCR1_WAKEUP_DISABLE = 0 (wakeup enabled).
*/
#define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change,
* default = 0 */
#define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change,
* default = 0 */
#define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change,
* default = 1 */
#define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change,
* default = 0 */
#define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change,
* default = 0 */
#define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME
* signal, DISCONNECT
* otherwise, default = 1 */
#define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */
#define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1:
* Pin 12 Active High, default
* = 0 */
/* Interrupt endpoint bytes & bits */
#define MCS7840_IEP_FIFO_STATUS_INDEX 5
/*
* Thesse can be calculated as "1 << portnumber" for Bulk-out and
* "1 << (portnumber+1)" for Bulk-in
*/
#define MCS7840_IEP_BO_PORT1_HASDATA 0x01
#define MCS7840_IEP_BI_PORT1_HASDATA 0x02
#define MCS7840_IEP_BO_PORT2_HASDATA 0x04
#define MCS7840_IEP_BI_PORT2_HASDATA 0x08
#define MCS7840_IEP_BO_PORT3_HASDATA 0x10
#define MCS7840_IEP_BI_PORT3_HASDATA 0x20
#define MCS7840_IEP_BO_PORT4_HASDATA 0x40
#define MCS7840_IEP_BI_PORT4_HASDATA 0x80
/* Documented UART registers (fully compatible with 16550 UART) */
#define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding
* Register W/Only */
#define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register
* R/Only */
#define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register -
* R/W */
#define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register -
* W/Only */
#define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter
* R/Only */
#define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */
#define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */
#define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */
#define MCS7840_UART_REG_MSR 0x06 /* Modem status register
* R/Only */
#define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */
#define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */
#define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */
/* IER bits */
#define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */
#define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */
#define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */
#define MCS7840_UART_IER_MODEM 0x08 /* Modem status change
* interrumpt mask */
#define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */
/* FCR bits */
#define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */
#define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */
#define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */
#define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR
* Interrupt Trigger level */
#define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */
#define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */
#define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */
#define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */
/* ISR bits */
#define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */
#define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt
* source */
#define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */
#define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */
#define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */
#define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */
#define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */
/* LCR bits */
#define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */
#define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */
#define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */
#define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */
#define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */
#define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */
#define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */
#define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on
* data length */
#define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */
#define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */
#define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */
#define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */
#define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */
#define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */
#define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */
#define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of
* xHR/IER */
/* LSR bits */
#define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */
#define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */
#define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */
#define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */
#define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK sigmal received */
#define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty,
* ready for transmit */
#define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */
/* MCR bits */
#define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active
* (low) */
#define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active
* (low) */
#define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from
* code, not documented) */
#define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test
* mode */
#define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control
* in 550 (FIFO) mode */
#define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control
* in 550 (FIFO) mode */
#define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in
* 550 (FIFO) mode */
/* MSR bits */
#define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last
* read */
#define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last
* read */
#define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to
* high since last read */
#define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last
* read */
#define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */
#define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */
#define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */
#define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */
/* SCRATCHPAD bits */
#define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */
#define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High
* = RX */
#define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High
* = TX */
#define MCS7840_CONFIG_INDEX 0
#define MCS7840_IFACE_INDEX 0
#endif

7
sys/dev/usb/usb_process.c
View File

@ -360,7 +360,12 @@ usb_proc_is_gone(struct usb_process *up)
if (up->up_gone)
return (1);
mtx_assert(up->up_mtx, MA_OWNED);
/*
* Allow calls when up_mtx is NULL, before the USB process
* structure is initialised.
*/
if (up->up_mtx != NULL)
mtx_assert(up->up_mtx, MA_OWNED);
return (0);
}

2
sys/dev/usb/usbdevs
View File

@ -2273,7 +2273,9 @@ product MOBILITY EASIDOCK 0x0304 EasiDock Ethernet
/* MosChip products */
product MOSCHIP MCS7703 0x7703 MCS7703 Serial Port Adapter
product MOSCHIP MCS7730 0x7730 MCS7730 Ethernet
product MOSCHIP MCS7820 0x7820 MCS7820 Serial Port Adapter
product MOSCHIP MCS7830 0x7830 MCS7830 Ethernet
product MOSCHIP MCS7840 0x7840 MCS7840 Serial Port Adapter
/* Motorola products */
product MOTOROLA MC141555 0x1555 MC141555 hub controller

15
sys/fs/nfsclient/nfs_clbio.c
View File

@ -302,7 +302,7 @@ ncl_putpages(struct vop_putpages_args *ap)
}
for (i = 0; i < npages; i++)
rtvals[i] = VM_PAGER_AGAIN;
rtvals[i] = VM_PAGER_ERROR;
/*
* When putting pages, do not extend file past EOF.
@ -345,16 +345,9 @@ ncl_putpages(struct vop_putpages_args *ap)
pmap_qremove(kva, npages);
relpbuf(bp, &ncl_pbuf_freecnt);
if (!error) {
int nwritten = round_page(count - uio.uio_resid) / PAGE_SIZE;
for (i = 0; i < nwritten; i++) {
rtvals[i] = VM_PAGER_OK;
vm_page_undirty(pages[i]);
}
if (must_commit) {
ncl_clearcommit(vp->v_mount);
}
}
vnode_pager_undirty_pages(pages, rtvals, count - uio.uio_resid);
if (must_commit)
ncl_clearcommit(vp->v_mount);
return rtvals[0];
}

11
sys/fs/nwfs/nwfs_io.c
View File

@ -544,7 +544,7 @@ nwfs_putpages(ap)
npages = btoc(count);
for (i = 0; i < npages; i++) {
rtvals[i] = VM_PAGER_AGAIN;
rtvals[i] = VM_PAGER_ERROR;
}
bp = getpbuf(&nwfs_pbuf_freecnt);
@ -569,13 +569,8 @@ nwfs_putpages(ap)
pmap_qremove(kva, npages);
relpbuf(bp, &nwfs_pbuf_freecnt);
if (!error) {
int nwritten = round_page(count - uio.uio_resid) / PAGE_SIZE;
for (i = 0; i < nwritten; i++) {
rtvals[i] = VM_PAGER_OK;
vm_page_undirty(pages[i]);
}
}
if (!error)
vnode_pager_undirty_pages(pages, rtvals, count - uio.uio_resid);
return rtvals[0];
#endif /* NWFS_RWCACHE */
}

11
sys/fs/smbfs/smbfs_io.c
View File

@ -609,7 +609,7 @@ smbfs_putpages(ap)
npages = btoc(count);
for (i = 0; i < npages; i++) {
rtvals[i] = VM_PAGER_AGAIN;
rtvals[i] = VM_PAGER_ERROR;
}
bp = getpbuf(&smbfs_pbuf_freecnt);
@ -639,13 +639,8 @@ smbfs_putpages(ap)
relpbuf(bp, &smbfs_pbuf_freecnt);
if (!error) {
int nwritten = round_page(count - uio.uio_resid) / PAGE_SIZE;
for (i = 0; i < nwritten; i++) {
rtvals[i] = VM_PAGER_OK;
vm_page_undirty(pages[i]);
}
}
if (!error)
vnode_pager_undirty_pages(pages, rtvals, count - uio.uio_resid);
return rtvals[0];
#endif /* SMBFS_RWGENERIC */
}

6
sys/geom/geom_dump.c
View File

@ -207,10 +207,8 @@ g_conf_provider(struct sbuf *sb, struct g_provider *pp)
sbuf_printf(sb, "\t <mediasize>%jd</mediasize>\n",
(intmax_t)pp->mediasize);
sbuf_printf(sb, "\t <sectorsize>%u</sectorsize>\n", pp->sectorsize);
if (pp->stripesize > 0) {
sbuf_printf(sb, "\t <stripesize>%u</stripesize>\n", pp->stripesize);
sbuf_printf(sb, "\t <stripeoffset>%u</stripeoffset>\n", pp->stripeoffset);
}
sbuf_printf(sb, "\t <stripesize>%u</stripesize>\n", pp->stripesize);
sbuf_printf(sb, "\t <stripeoffset>%u</stripeoffset>\n", pp->stripeoffset);
if (pp->geom->flags & G_GEOM_WITHER)
;
else if (pp->geom->dumpconf != NULL) {

4
sys/modules/ath/Makefile
View File

@ -134,6 +134,10 @@ SRCS+= onoe.c
SRCS+= amrr.c
.endif
# DFS
.PATH: ${.CURDIR}/../../dev/ath/ath_dfs/null
SRCS+= dfs_null.c
CFLAGS+= -I. -I${.CURDIR}/../../dev/ath -I${.CURDIR}/../../dev/ath/ath_hal
opt_ah.h:

2
sys/modules/usb/Makefile
View File

@ -30,7 +30,7 @@ SUBDIR += ehci musb ohci uhci xhci uss820dci ${_at91dci} ${_atmegadci}
SUBDIR += rum run uath upgt ural zyd ${_urtw}
SUBDIR += atp uhid ukbd ums udbp ufm uep
SUBDIR += ucom u3g uark ubsa ubser uchcom ucycom ufoma uftdi ugensa uipaq ulpt \
umct umodem umoscom uplcom uslcom uvisor uvscom
umct umcs7840 umodem umoscom uplcom uslcom uvisor uvscom
SUBDIR += uether aue axe cdce cue kue mos rue udav uhso ipheth
SUBDIR += usfs umass urio
SUBDIR += quirk template

36
sys/modules/usb/umcs7840/Makefile Normal file
View File

@ -0,0 +1,36 @@
#
# $FreeBSD$
#
# Copyright (c) 2011 Hans Petter Selasky. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
S= ${.CURDIR}/../../..
.PATH: $S/dev/usb/serial
KMOD= umcs7840
SRCS= opt_bus.h opt_usb.h device_if.h bus_if.h usb_if.h usbdevs.h \
umcs7840.c
.include <bsd.kmod.mk>

42
sys/net/if_ethersubr.c
View File

@ -561,7 +561,7 @@ ether_ipfw_chk(struct mbuf **m0, struct ifnet *dst, int shared)
* mbuf chain m with the ethernet header at the front.
*/
static void
ether_input(struct ifnet *ifp, struct mbuf *m)
ether_input_internal(struct ifnet *ifp, struct mbuf *m)
{
struct ether_header *eh;
u_short etype;
@ -754,6 +754,46 @@ ether_input(struct ifnet *ifp, struct mbuf *m)
CURVNET_RESTORE();
}
/*
* Ethernet input dispatch; by default, direct dispatch here regardless of
* global configuration.
*/
static void
ether_nh_input(struct mbuf *m)
{
ether_input_internal(m->m_pkthdr.rcvif, m);
}
static struct netisr_handler ether_nh = {
.nh_name = "ether",
.nh_handler = ether_nh_input,
.nh_proto = NETISR_ETHER,
.nh_policy = NETISR_POLICY_SOURCE,
.nh_dispatch = NETISR_DISPATCH_DIRECT,
};
static void
ether_init(__unused void *arg)
{
netisr_register(&ether_nh);
}
SYSINIT(ether, SI_SUB_INIT_IF, SI_ORDER_ANY, ether_init, NULL);
static void
ether_input(struct ifnet *ifp, struct mbuf *m)
{
/*
* We will rely on rcvif being set properly in the deferred context,
* so assert it is correct here.
*/
KASSERT(m->m_pkthdr.rcvif == ifp, ("%s: ifnet mismatch", __func__));
netisr_dispatch(NETISR_ETHER, m);
}
/*
* Upper layer processing for a received Ethernet packet.
*/

3
sys/netinet/ipfw/ip_fw2.c
View File

@ -2118,7 +2118,8 @@ do { \
case O_FORWARD_IP:
if (args->eh) /* not valid on layer2 pkts */
break;
if (!q || dyn_dir == MATCH_FORWARD) {
if (q == NULL || q->rule != f ||
dyn_dir == MATCH_FORWARD) {
struct sockaddr_in *sa;
sa = &(((ipfw_insn_sa *)cmd)->sa);
if (sa->sin_addr.s_addr == INADDR_ANY) {

2
sys/netinet/tcp_usrreq.c
View File

@ -1158,7 +1158,7 @@ tcp6_connect(struct tcpcb *tp, struct sockaddr *nam, struct thread *td)
*/
error = in6_pcbladdr(inp, nam, &addr6);
if (error)
return error;
goto out;
oinp = in6_pcblookup_hash_locked(inp->inp_pcbinfo,
&sin6->sin6_addr, sin6->sin6_port,
IN6_IS_ADDR_UNSPECIFIED(&inp->in6p_laddr)

8
sys/nfsclient/nfs_bio.c
View File

@ -300,7 +300,7 @@ nfs_putpages(struct vop_putpages_args *ap)
}
for (i = 0; i < npages; i++)
rtvals[i] = VM_PAGER_AGAIN;
rtvals[i] = VM_PAGER_ERROR;
/*
* When putting pages, do not extend file past EOF.
@ -344,11 +344,7 @@ nfs_putpages(struct vop_putpages_args *ap)
relpbuf(bp, &nfs_pbuf_freecnt);
if (!error) {
int nwritten = round_page(count - uio.uio_resid) / PAGE_SIZE;
for (i = 0; i < nwritten; i++) {
rtvals[i] = VM_PAGER_OK;
vm_page_undirty(pages[i]);
}
vnode_pager_undirty_pages(pages, rtvals, count - uio.uio_resid);
if (must_commit) {
nfs_clearcommit(vp->v_mount);
}

32
sys/teken/libteken/teken.3
View File

@ -185,22 +185,6 @@ function switches terminal emulation to
which is used by versions of
.Fx
prior to 9.0.
.Sh SECURITY CONSIDERATIONS
The
.Fn tf_respond
callback is used to respond to device status requests commands generated
by an application.
In the past, there have been various security issues, where a malicious
application sends a device status request before termination, causing
the generated response to be interpreted by applications such as
.Xr sh 1 .
.Pp
.Nm
only implements a small subset of responses which are unlikely to cause
any harm.
Still, it is advised to leave
.Fn tf_respond
unimplemented.
.Sh SEE ALSO
.Xr ncurses 3 ,
.Xr termcap 3 ,
@ -218,3 +202,19 @@ the
library appeared in userspace.
.Sh AUTHORS
.An Ed Schouten Aq ed@FreeBSD.org
.Sh SECURITY CONSIDERATIONS
The
.Fn tf_respond
callback is used to respond to device status requests commands generated
by an application.
In the past, there have been various security issues, where a malicious
application sends a device status request before termination, causing
the generated response to be interpreted by applications such as
.Xr sh 1 .
.Pp
.Nm
only implements a small subset of responses which are unlikely to cause
any harm.
Still, it is advised to leave
.Fn tf_respond
unimplemented.

15
sys/vm/vm_object.c
View File

@ -852,6 +852,21 @@ vm_object_page_clean(vm_object_t object, vm_ooffset_t start, vm_ooffset_t end,
flags, &clearobjflags);
if (object->generation != curgeneration)
goto rescan;
/*
* If the VOP_PUTPAGES() did a truncated write, so
* that even the first page of the run is not fully
* written, vm_pageout_flush() returns 0 as the run
* length. Since the condition that caused truncated
* write may be permanent, e.g. exhausted free space,
* accepting n == 0 would cause an infinite loop.
*
* Forwarding the iterator leaves the unwritten page
* behind, but there is not much we can do there if
* filesystem refuses to write it.
*/
if (n == 0)
n = 1;
np = vm_page_find_least(object, pi + n);
}
#if 0

19
sys/vm/vnode_pager.c
View File

@ -1089,7 +1089,7 @@ vnode_pager_generic_putpages(struct vnode *vp, vm_page_t *ma, int bytecount,
count = bytecount / PAGE_SIZE;
for (i = 0; i < count; i++)
rtvals[i] = VM_PAGER_AGAIN;
rtvals[i] = VM_PAGER_ERROR;
if ((int64_t)ma[0]->pindex < 0) {
printf("vnode_pager_putpages: attempt to write meta-data!!! -- 0x%lx(%lx)\n",
@ -1191,3 +1191,20 @@ vnode_pager_generic_putpages(struct vnode *vp, vm_page_t *ma, int bytecount,
}
return rtvals[0];
}
void
vnode_pager_undirty_pages(vm_page_t *ma, int *rtvals, int written)
{
int i, pos;
for (i = 0, pos = 0; pos < written; i++, pos += PAGE_SIZE) {
if (pos < trunc_page(written)) {
rtvals[i] = VM_PAGER_OK;
vm_page_undirty(ma[i]);
} else {
/* Partially written page. */
rtvals[i] = VM_PAGER_AGAIN;
vm_page_clear_dirty(ma[i], 0, written & PAGE_MASK);
}
}
}

3
sys/vm/vnode_pager.h
View File

@ -49,5 +49,8 @@ int vnode_pager_generic_getpages(struct vnode *vp, vm_page_t *m,
int vnode_pager_generic_putpages(struct vnode *vp, vm_page_t *m,
int count, boolean_t sync,
int *rtvals);
void vnode_pager_undirty_pages(vm_page_t *ma, int *rtvals, int written);
#endif /* _KERNEL */
#endif /* _VNODE_PAGER_ */

20
usr.bin/fstat/fuser.1
View File

@ -130,6 +130,16 @@ The
.Nm
utility is expected to conform to
.St -p1003.1-2004 .
.Sh HISTORY
The
.Nm
utility appeared in
.Fx 9.0 .
.Sh AUTHORS
The
.Nm
utility and this manual page was written by
.An Stanislav Sedov Aq stas@FreeBSD.org .
.Sh BUGS
Since
.Nm
@ -141,13 +151,3 @@ interface the report will be limited to filesystems the
.Nm
utility knows about (currently only cd9660, devfs, nfs, ntfs, nwfs, udf,
ufs and zfs).
.Sh HISTORY
The
.Nm
utility appeared in
.Fx 9.0 .
.Sh AUTHORS
The
.Nm
utility and this manual page was written by
.An Stanislav Sedov Aq stas@FreeBSD.org .

2
usr.bin/man/man.sh
View File

@ -895,7 +895,7 @@ NROFF='groff -S -P-c -Wall -mtty-char -man'
PIC=pic
REFER=refer
TBL=tbl
TROFF='groff -S -P-c -man'
TROFF='groff -S -man'
VGRIND=vgrind
COL=/usr/bin/col

2
usr.bin/rctl/rctl.8
View File

@ -82,7 +82,7 @@ Use unit suffixes: Byte, Kilobyte, Megabyte,
Gigabyte, Terabyte and Petabyte.
.It Fl n
Display user IDs numerically rather than converting them to a user name.
.Pp
.El
.Sh RULE SYNTAX
Syntax for a rule is subject:subject-id:resource:action=amount/per.
.Pp

2
usr.sbin/bsdinstall/scripts/auto
View File

@ -199,7 +199,7 @@ finalconfig() {
clear
echo This shell is operating in a chroot in the new system. \
When finished making configuration changes, type \"exit\".
chroot "$BSDINSTALL_CHROOT" /bin/sh
chroot "$BSDINSTALL_CHROOT" /bin/sh 2>&1
# Don't hose local rc.conf changes
cp $BSDINSTALL_CHROOT/etc/rc.conf $BSDINSTALL_TMPETC/rc.conf.manual
finalconfig

8
usr.sbin/mfiutil/mfi_evt.c
View File

@ -362,8 +362,8 @@ mfi_decode_evt(int fd, struct mfi_evt_detail *detail, int verbose)
{
printf("%5d (%s/%s/%s) - ", detail->seq, format_timestamp(detail->time),
format_locale(detail->class.members.locale),
format_class(detail->class.members.class));
format_locale(detail->evt_class.members.locale),
format_class(detail->evt_class.members.evt_class));
switch (detail->arg_type) {
case MR_EVT_ARGS_NONE:
break;
@ -557,7 +557,7 @@ show_events(int ac, char **av)
num_events = 15;
filter.members.reserved = 0;
filter.members.locale = MFI_EVT_LOCALE_ALL;
filter.members.class = MFI_EVT_CLASS_WARNING;
filter.members.evt_class = MFI_EVT_CLASS_WARNING;
start = info.boot_seq_num;
stop = info.newest_seq_num;
verbose = 0;
@ -567,7 +567,7 @@ show_events(int ac, char **av)
while ((ch = getopt(ac, av, "c:l:n:v")) != -1) {
switch (ch) {
case 'c':
if (parse_class(optarg, &filter.members.class) < 0) {
if (parse_class(optarg, &filter.members.evt_class) < 0) {
error = errno;
warn("Error parsing event class");
return (error);