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o) Unmask Central Interrupt Unit interrupts on APs, too.

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o) There's no good reason to make the low bits of the ebase the core
   number.  While per-CPU exception bases would be nice, for now we just
   need to make ebase the same on all cores.
This commit is contained in:
jmallett 2011-01-04 02:11:03 +00:00
parent 43700b5724
commit 3c430a1c11
1 changed files with 5 additions and 4 deletions
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9
sys/mips/cavium/octeon_mp.c
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@ -74,12 +74,12 @@ platform_ipi_intrnum(void)
void
platform_init_ap(int cpuid)
{
unsigned ipi_int_mask, clock_int_mask;
unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
/*
* Set the exception base.
*/
mips_wr_ebase(0x80000000 | cpuid);
mips_wr_ebase(0x80000000);
/*
* Clear any pending IPIs.
@ -92,11 +92,12 @@ platform_init_ap(int cpuid)
octeon_ciu_reset();
/*
* Unmask the clock and ipi interrupts.
* Unmask the clock, ipi and ciu interrupts.
*/
ciu_int_mask = hard_int_mask(0);
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
set_intr_mask(ipi_int_mask | clock_int_mask);
set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
mips_wbflush();
}