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Fix an unaligned I/O memory access in the event that a SCB times out.

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The FXP_SCR_FLOWCONTROL registers is at offset 0x19, but 2 bytes wide.
It cannot be read as a word without causing a panic on architectures
that enforce strict alignment.

MFC after: 3 days
This commit is contained in:
Marcel Moolenaar 2005-09-21 04:36:40 +00:00
parent 8aaa8fe733
commit 3cf09dd123
1 changed files with 9 additions and 3 deletions
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12
sys/dev/fxp/if_fxp.c
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@ -289,16 +289,22 @@ DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
static void
fxp_scb_wait(struct fxp_softc *sc)
{
union {
uint16_t w;
uint8_t b[2];
} flowctl;
int i = 10000;
while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
DELAY(2);
if (i == 0)
if (i == 0) {
flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL);
flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FLOWCONTROL + 1);
device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
}
}
static void