From 3d6bebd3a2a3ab5b4945d3a9a04b660d6982b6c4 Mon Sep 17 00:00:00 2001 From: Justin Hibbits Date: Sun, 9 Dec 2018 04:13:14 +0000 Subject: [PATCH] powerpc/SPE: Reload vector registers after efdabs/efdnabs/efdneg While here, also style(9)-adjust indents around this code. --- sys/powerpc/booke/spe.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/sys/powerpc/booke/spe.c b/sys/powerpc/booke/spe.c index 3d8134300bca..4f88f6f600cc 100644 --- a/sys/powerpc/booke/spe.c +++ b/sys/powerpc/booke/spe.c @@ -464,17 +464,17 @@ spe_handle_fpdata(struct trapframe *frame) switch (instr_sec_op) { case EVFSABS: curthread->td_pcb->pcb_vec.vr[rd][0] = - curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31); + curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31); frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31); break; case EVFSNABS: curthread->td_pcb->pcb_vec.vr[rd][0] = - curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31); + curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31); frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31); break; case EVFSNEG: curthread->td_pcb->pcb_vec.vr[rd][0] = - curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31); + curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31); frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31); break; default: @@ -542,15 +542,18 @@ spe_handle_fpdata(struct trapframe *frame) switch (instr_sec_op) { case EFDABS: curthread->td_pcb->pcb_vec.vr[rd][0] = - curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31); + curthread->td_pcb->pcb_vec.vr[ra][0] & ~(1U << 31); + enable_vec(curthread); break; case EFDNABS: curthread->td_pcb->pcb_vec.vr[rd][0] = - curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31); + curthread->td_pcb->pcb_vec.vr[ra][0] | (1U << 31); + enable_vec(curthread); break; case EFDNEG: curthread->td_pcb->pcb_vec.vr[rd][0] = - curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31); + curthread->td_pcb->pcb_vec.vr[ra][0] ^ (1U << 31); + enable_vec(curthread); break; case EFDCFS: spe_explode(&fpemu, &fpemu.fe_f3, SINGLE,