Move imx_sdhci driver over to a dev/sdhci in preparation for QorIQ support.
Freescale uses eSDHC in both i.MX (ARM) and QorIQ (PowerPC), with slight differences. This is part one in unifying the drivers. Reviewed by: imp
This commit is contained in:
Justin Hibbits
parent
06d706238b
commit
3d9df07abf
@ -32,7 +32,7 @@ arm/freescale/imx/imx51_ccm.c standard
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dev/ata/chipsets/ata-fsl.c optional imxata
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# SDHCI/MMC
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arm/freescale/imx/imx_sdhci.c optional sdhci
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dev/sdhci/fsl_sdhci.c optional sdhci
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# USB OH3 controller (1 OTG, 3 EHCI)
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arm/freescale/imx/imx_nop_usbphy.c optional ehci
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@ -32,7 +32,7 @@ arm/freescale/imx/imx6_ipu.c optional vt
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#
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# Optional devices.
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#
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arm/freescale/imx/imx_sdhci.c optional sdhci
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dev/sdhci/fsl_sdhci.c optional sdhci
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arm/freescale/imx/imx_wdog.c optional imxwdt
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@ -66,7 +66,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/sdhci/sdhci.h>
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#include "sdhci_if.h"
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struct imx_sdhci_softc {
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struct fsl_sdhci_softc {
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device_t dev;
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struct resource * mem_res;
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struct resource * irq_res;
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@ -88,8 +88,8 @@ struct imx_sdhci_softc {
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#define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
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#define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
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#define HWTYPE_ESDHC 1 /* imx5x and earlier. */
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#define HWTYPE_USDHC 2 /* imx6. */
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#define HWTYPE_ESDHC 1 /* fsl5x and earlier. */
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#define HWTYPE_USDHC 2 /* fsl6. */
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/*
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* Freescale-specific registers, or in some cases the layout of bits within the
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@ -172,28 +172,28 @@ static struct ofw_compat_data compat_data[] = {
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{NULL, HWTYPE_NONE},
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};
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static uint16_t imx_sdhc_get_clock(struct imx_sdhci_softc *sc);
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static void imx_sdhc_set_clock(struct imx_sdhci_softc *sc, uint16_t val);
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static void imx_sdhci_r1bfix_func(void *arg);
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static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc);
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static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val);
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static void fsl_sdhci_r1bfix_func(void *arg);
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static inline uint32_t
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RD4(struct imx_sdhci_softc *sc, bus_size_t off)
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RD4(struct fsl_sdhci_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off));
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}
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static inline void
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WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val)
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WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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static uint8_t
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imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32, wrk32;
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/*
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@ -246,9 +246,9 @@ imx_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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}
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static uint16_t
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imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32;
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if (sc->hwtype == HWTYPE_USDHC) {
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@ -297,16 +297,16 @@ imx_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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* hardware type, complex enough to have their own function.
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*/
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if (off == SDHCI_CLOCK_CONTROL) {
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return (imx_sdhc_get_clock(sc));
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return (fsl_sdhc_get_clock(sc));
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}
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return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
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}
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static uint32_t
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imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32, wrk32;
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val32 = RD4(sc, off);
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@ -348,7 +348,7 @@ imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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}
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/*
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* imx_sdhci_intr() can synthesize a DATA_END interrupt following a
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* fsl_sdhci_intr() can synthesize a DATA_END interrupt following a
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* command with an R1B response, mix it into the hardware status.
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*/
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if (off == SDHCI_INT_STATUS) {
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@ -359,18 +359,18 @@ imx_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
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}
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static void
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imx_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t *data, bus_size_t count)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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bus_read_multi_4(sc->mem_res, off, data, count);
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}
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static void
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imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
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fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32;
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/*
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@ -406,9 +406,9 @@ imx_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t
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}
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static void
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imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
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fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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uint32_t val32;
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/*
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@ -416,7 +416,7 @@ imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_
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* that can handle the ESDHC versus USDHC differences.
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*/
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if (off == SDHCI_CLOCK_CONTROL) {
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imx_sdhc_set_clock(sc, val);
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fsl_sdhc_set_clock(sc, val);
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return;
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}
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@ -432,7 +432,7 @@ imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_
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* there's a control bit for it (bit 3) in the vendor register.
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* When we're starting a command that needs a manual DAT0 line check at
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* interrupt time, we leave ourselves a note in r1bfix_type so that we
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* can do the extra work in imx_sdhci_intr().
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* can do the extra work in fsl_sdhci_intr().
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*/
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if (off == SDHCI_COMMAND_FLAGS) {
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if (val & SDHCI_CMD_DATA) {
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@ -485,9 +485,9 @@ imx_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_
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}
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static void
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imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
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fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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/* Clear synthesized interrupts, then pass the value to the hardware. */
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if (off == SDHCI_INT_STATUS) {
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@ -498,16 +498,16 @@ imx_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_
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}
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static void
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imx_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
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uint32_t *data, bus_size_t count)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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bus_write_multi_4(sc->mem_res, off, data, count);
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}
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static uint16_t
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imx_sdhc_get_clock(struct imx_sdhci_softc *sc)
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fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc)
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{
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uint16_t val;
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@ -551,7 +551,7 @@ imx_sdhc_get_clock(struct imx_sdhci_softc *sc)
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}
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static void
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imx_sdhc_set_clock(struct imx_sdhci_softc *sc, uint16_t val)
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fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
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{
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uint32_t divisor, freq, prescale, val32;
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@ -629,7 +629,7 @@ imx_sdhc_set_clock(struct imx_sdhci_softc *sc, uint16_t val)
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}
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static boolean_t
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imx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc)
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fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc)
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{
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uint32_t inhibit;
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@ -646,7 +646,7 @@ imx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc)
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if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
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callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
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imx_sdhci_r1bfix_func, sc, 0);
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fsl_sdhci_r1bfix_func, sc, 0);
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return (false);
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}
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@ -670,22 +670,22 @@ imx_sdhci_r1bfix_is_wait_done(struct imx_sdhci_softc *sc)
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}
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static void
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imx_sdhci_r1bfix_func(void * arg)
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fsl_sdhci_r1bfix_func(void * arg)
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{
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struct imx_sdhci_softc *sc = arg;
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struct fsl_sdhci_softc *sc = arg;
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boolean_t r1bwait_done;
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mtx_lock(&sc->slot.mtx);
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r1bwait_done = imx_sdhci_r1bfix_is_wait_done(sc);
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r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc);
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mtx_unlock(&sc->slot.mtx);
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if (r1bwait_done)
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sdhci_generic_intr(&sc->slot);
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}
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static void
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imx_sdhci_intr(void *arg)
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fsl_sdhci_intr(void *arg)
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{
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struct imx_sdhci_softc *sc = arg;
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struct fsl_sdhci_softc *sc = arg;
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uint32_t intmask;
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mtx_lock(&sc->slot.mtx);
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@ -721,7 +721,7 @@ imx_sdhci_intr(void *arg)
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}
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if (intmask) {
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sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
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if (!imx_sdhci_r1bfix_is_wait_done(sc)) {
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if (!fsl_sdhci_r1bfix_is_wait_done(sc)) {
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WR4(sc, SDHC_INT_STATUS, intmask);
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bus_barrier(sc->mem_res, SDHC_INT_STATUS, 4,
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BUS_SPACE_BARRIER_WRITE);
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@ -733,23 +733,23 @@ imx_sdhci_intr(void *arg)
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}
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static int
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imx_sdhci_get_ro(device_t bus, device_t child)
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fsl_sdhci_get_ro(device_t bus, device_t child)
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{
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return (false);
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}
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static int
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imx_sdhci_detach(device_t dev)
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fsl_sdhci_detach(device_t dev)
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{
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return (EBUSY);
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}
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static int
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imx_sdhci_attach(device_t dev)
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fsl_sdhci_attach(device_t dev)
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{
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struct imx_sdhci_softc *sc = device_get_softc(dev);
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struct fsl_sdhci_softc *sc = device_get_softc(dev);
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int rid, err;
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phandle_t node;
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@ -757,7 +757,7 @@ imx_sdhci_attach(device_t dev)
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sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (sc->hwtype == HWTYPE_NONE)
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panic("Impossible: not compatible in imx_sdhci_attach()");
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panic("Impossible: not compatible in fsl_sdhci_attach()");
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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@ -778,7 +778,7 @@ imx_sdhci_attach(device_t dev)
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}
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, imx_sdhci_intr, sc, &sc->intr_cookie)) {
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NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) {
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device_printf(dev, "cannot setup interrupt handler\n");
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err = ENXIO;
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goto fail;
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@ -853,7 +853,7 @@ imx_sdhci_attach(device_t dev)
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}
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static int
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imx_sdhci_probe(device_t dev)
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fsl_sdhci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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@ -872,11 +872,11 @@ imx_sdhci_probe(device_t dev)
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return (ENXIO);
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}
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static device_method_t imx_sdhci_methods[] = {
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static device_method_t fsl_sdhci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, imx_sdhci_probe),
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DEVMETHOD(device_attach, imx_sdhci_attach),
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DEVMETHOD(device_detach, imx_sdhci_detach),
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DEVMETHOD(device_probe, fsl_sdhci_probe),
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DEVMETHOD(device_attach, fsl_sdhci_attach),
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DEVMETHOD(device_detach, fsl_sdhci_detach),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
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@ -886,32 +886,32 @@ static device_method_t imx_sdhci_methods[] = {
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/* MMC bridge interface */
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DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
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DEVMETHOD(mmcbr_request, sdhci_generic_request),
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DEVMETHOD(mmcbr_get_ro, imx_sdhci_get_ro),
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DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro),
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DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
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DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
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/* SDHCI registers accessors */
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DEVMETHOD(sdhci_read_1, imx_sdhci_read_1),
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DEVMETHOD(sdhci_read_2, imx_sdhci_read_2),
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DEVMETHOD(sdhci_read_4, imx_sdhci_read_4),
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DEVMETHOD(sdhci_read_multi_4, imx_sdhci_read_multi_4),
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DEVMETHOD(sdhci_write_1, imx_sdhci_write_1),
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DEVMETHOD(sdhci_write_2, imx_sdhci_write_2),
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DEVMETHOD(sdhci_write_4, imx_sdhci_write_4),
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DEVMETHOD(sdhci_write_multi_4, imx_sdhci_write_multi_4),
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DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1),
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DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2),
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DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4),
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DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4),
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DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1),
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DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2),
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DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4),
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DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4),
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{ 0, 0 }
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};
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static devclass_t imx_sdhci_devclass;
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static devclass_t fsl_sdhci_devclass;
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static driver_t imx_sdhci_driver = {
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"sdhci_imx",
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imx_sdhci_methods,
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sizeof(struct imx_sdhci_softc),
|
||||
static driver_t fsl_sdhci_driver = {
|
||||
"sdhci_fsl",
|
||||
fsl_sdhci_methods,
|
||||
sizeof(struct fsl_sdhci_softc),
|
||||
};
|
||||
|
||||
DRIVER_MODULE(sdhci_imx, simplebus, imx_sdhci_driver, imx_sdhci_devclass, 0, 0);
|
||||
MODULE_DEPEND(sdhci_imx, sdhci, 1, 1, 1);
|
||||
DRIVER_MODULE(mmc, sdhci_imx, mmc_driver, mmc_devclass, NULL, NULL);
|
||||
MODULE_DEPEND(sdhci_imx, mmc, 1, 1, 1);
|
||||
DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass, 0, 0);
|
||||
MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1);
|
||||
DRIVER_MODULE(mmc, sdhci_fsl, mmc_driver, mmc_devclass, NULL, NULL);
|
||||
MODULE_DEPEND(sdhci_fsl, mmc, 1, 1, 1);
|
||||
Loading…
Reference in New Issue
Block a user