d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge ^/head r340869 through r340917.

Browse Source
This commit is contained in:
dim 2018-11-25 11:15:01 +00:00
parent 3aa6bcc5fe
commit 3eb053d6a0
41 changed files with 1146 additions and 839 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/csu/common/crtend.c
View File

@ -41,6 +41,9 @@ static crt_func __CTOR_END__[] __section(".ctors") __used = {
static crt_func __DTOR_END__[] __section(".dtors") __used = {
(crt_func)0
};
static crt_func __JCR_LIST__[] __section(".jcr") __used = {
(crt_func)0
};
static void
__do_global_ctors_aux(void)

8
stand/i386/pxeldr/pxeboot.8
View File

@ -58,7 +58,7 @@ The
.Nm
binary is loaded just like any other boot file,
by specifying it in the DHCP server's configuration file.
Below is a sample configuration for the ISC DHCP v2 server:
Below is a sample configuration for the ISC DHCP v3 server:
.Bd -literal -offset indent
option domain-name "example.com";
option routers 10.0.0.1;
@ -67,6 +67,7 @@ option broadcast-address 10.0.0.255;
option domain-name-servers 10.0.0.1;
server-name "DHCPserver";
server-identifier 10.0.0.1;
next-server 10.0.0.1;
default-lease-time 120;
max-lease-time 120;
@ -80,10 +81,11 @@ subnet 10.0.0.0 netmask 255.255.255.0 {
}
.Ed
.Va next-server
is the IP address of the next server in the bootstrap process, i.e.
your TFTP server or NFS server.
.Nm
recognizes
.Va next-server
and
.Va option root-path
directives as the server and path to NFS mount for file requests,
respectively, or the server to make TFTP requests to.

2
sys/compat/linux/linux_event.c
View File

@ -504,7 +504,7 @@ linux_epoll_ctl(struct thread *td, struct linux_epoll_ctl_args *args)
* and the EV_ADD flag is not set.
*/
kev[0].flags &= ~EV_ADD;
error = kqfd_register(args->epfd, &kev[0], td, 1);
error = kqfd_register(args->epfd, &kev[0], td, M_WAITOK);
if (error != ENOENT) {
error = EEXIST;
goto leave0;

3
sys/contrib/ipfilter/netinet/ip_fil_freebsd.c
View File

@ -288,8 +288,7 @@ ipfdetach(softc)
* Filter ioctl interface.
*/
int
ipfioctl(dev, cmd, data, mode
, p)
ipfioctl(dev, cmd, data, mode, p)
struct thread *p;
# define p_cred td_ucred
# define p_uid td_ucred->cr_ruid

83
sys/dev/atkbdc/atkbdc.c
View File

@ -296,6 +296,7 @@ atkbdc_setup(atkbdc_softc_t *sc, bus_space_tag_t tag, bus_space_handle_t h0,
sc->lock = FALSE;
sc->kbd.head = sc->kbd.tail = 0;
sc->aux.head = sc->aux.tail = 0;
sc->aux_mux_enabled = FALSE;
#if KBDIO_DEBUG >= 2
sc->kbd.call_count = 0;
sc->kbd.qcount = sc->kbd.max_qcount = 0;
@ -639,7 +640,12 @@ write_kbd_command(KBDC p, int c)
int
write_aux_command(KBDC p, int c)
{
if (!write_controller_command(p, KBDC_WRITE_TO_AUX))
int f;
f = aux_mux_is_enabled(p) ?
KBDC_WRITE_TO_AUX_MUX + kbdcp(p)->aux_mux_port : KBDC_WRITE_TO_AUX;
if (!write_controller_command(p, f))
return FALSE;
return write_controller_data(p, c);
}
@ -1201,3 +1207,78 @@ set_controller_command_byte(KBDC p, int mask, int command)
return TRUE;
}
/*
* Rudimentary support for active PS/2 AUX port multiplexing.
* Only write commands can be routed to a selected AUX port.
* Source port of data processed by read commands is totally ignored.
*/
static int
set_aux_mux_state(KBDC p, int enabled)
{
int command, version;
if (write_controller_command(p, KBDC_FORCE_AUX_OUTPUT) == 0 ||
write_controller_data(p, 0xF0) == 0 ||
read_controller_data(p) != 0xF0)
return (-1);
if (write_controller_command(p, KBDC_FORCE_AUX_OUTPUT) == 0 ||
write_controller_data(p, 0x56) == 0 ||
read_controller_data(p) != 0x56)
return (-1);
command = enabled ? 0xa4 : 0xa5;
if (write_controller_command(p, KBDC_FORCE_AUX_OUTPUT) == 0 ||
write_controller_data(p, command) == 0 ||
(version = read_controller_data(p)) == command)
return (-1);
return (version);
}
int
set_active_aux_mux_port(KBDC p, int port)
{
if (!aux_mux_is_enabled(p))
return (FALSE);
if (port < 0 || port >= KBDC_AUX_MUX_NUM_PORTS)
return (FALSE);
kbdcp(p)->aux_mux_port = port;
return (TRUE);
}
/* Checks for active multiplexing support and enables it */
int
enable_aux_mux(KBDC p)
{
int version;
version = set_aux_mux_state(p, TRUE);
if (version >= 0) {
kbdcp(p)->aux_mux_enabled = TRUE;
set_active_aux_mux_port(p, 0);
}
return (version);
}
int
disable_aux_mux(KBDC p)
{
kbdcp(p)->aux_mux_enabled = FALSE;
return (set_aux_mux_state(p, FALSE));
}
int
aux_mux_is_enabled(KBDC p)
{
return (kbdcp(p)->aux_mux_enabled);
}

11
sys/dev/atkbdc/atkbdcreg.h
View File

@ -51,6 +51,8 @@
/* controller commands (sent to KBD_COMMAND_PORT) */
#define KBDC_SET_COMMAND_BYTE 0x0060
#define KBDC_GET_COMMAND_BYTE 0x0020
#define KBDC_WRITE_TO_AUX_MUX 0x0090
#define KBDC_FORCE_AUX_OUTPUT 0x00d3
#define KBDC_WRITE_TO_AUX 0x00d4
#define KBDC_DISABLE_AUX_PORT 0x00a7
#define KBDC_ENABLE_AUX_PORT 0x00a8
@ -209,6 +211,8 @@ typedef struct atkbdc_softc {
#define KBDC_QUIRK_IGNORE_PROBE_RESULT (1 << 1)
#define KBDC_QUIRK_RESET_AFTER_PROBE (1 << 2)
#define KBDC_QUIRK_SETLEDS_ON_INIT (1 << 3)
int aux_mux_enabled; /* active PS/2 multiplexing is enabled */
int aux_mux_port; /* current aux mux port */
} atkbdc_softc_t;
enum kbdc_device_ivar {
@ -223,6 +227,8 @@ typedef caddr_t KBDC;
#define KBDC_RID_KBD 0
#define KBDC_RID_AUX 1
#define KBDC_AUX_MUX_NUM_PORTS 4
/* function prototypes */
atkbdc_softc_t *atkbdc_get_softc(int unit);
@ -268,6 +274,11 @@ void kbdc_set_device_mask(KBDC kbdc, int mask);
int get_controller_command_byte(KBDC kbdc);
int set_controller_command_byte(KBDC kbdc, int command, int flag);
int set_active_aux_mux_port(KBDC p, int port);
int enable_aux_mux(KBDC p);
int disable_aux_mux(KBDC p);
int aux_mux_is_enabled(KBDC p);
#endif /* _KERNEL */
#endif /* !_DEV_ATKBDC_ATKBDCREG_H_ */

245
sys/dev/atkbdc/psm.c
View File

@ -136,7 +136,6 @@ struct psmcpnp_softc {
enum {
PSMCPNP_GENERIC,
PSMCPNP_FORCEPAD,
PSMCPNP_HPSYN81,
} type; /* Based on PnP ID */
};
@ -151,6 +150,9 @@ struct psmcpnp_softc {
#define PSM_LEVEL_MIN PSM_LEVEL_BASE
#define PSM_LEVEL_MAX PSM_LEVEL_NATIVE
/* Active PS/2 multiplexing */
#define PSM_NOMUX (-1)
/* Logitech PS2++ protocol */
#define MOUSE_PS2PLUS_CHECKBITS(b) \
((((b[2] & 0x03) << 2) | 0x02) == (b[1] & 0x0f))
@ -175,15 +177,6 @@ typedef struct packetbuf {
#define PSM_PACKETQUEUE 128
#endif
/*
* Typical bezel limits. Taken from 'Synaptics
* PS/2 TouchPad Interfacing Guide' p.3.2.3.
*/
#define SYNAPTICS_DEFAULT_MAX_X 5472
#define SYNAPTICS_DEFAULT_MAX_Y 4448
#define SYNAPTICS_DEFAULT_MIN_X 1472
#define SYNAPTICS_DEFAULT_MIN_Y 1408
typedef struct synapticsinfo {
struct sysctl_ctx_list sysctl_ctx;
struct sysctl_oid *sysctl_tree;
@ -448,6 +441,11 @@ struct psm_softc { /* Driver status information */
int cmdcount;
struct sigio *async; /* Processes waiting for SIGIO */
int extended_buttons;
int muxport; /* MUX port with attached Synaptics */
u_char muxsave[3]; /* 3->6 byte proto conversion buffer */
int muxtpbuttons; /* Touchpad button state */
int muxmsbuttons; /* Mouse (trackpoint) button state */
struct timeval muxmidtimeout; /* middle button supression timeout */
#ifdef EVDEV_SUPPORT
struct evdev_dev *evdev_a; /* Absolute reporting device */
struct evdev_dev *evdev_r; /* Relative reporting device */
@ -613,6 +611,7 @@ static void proc_mmanplus(struct psm_softc *, packetbuf_t *,
mousestatus_t *, int *, int *, int *);
static int proc_synaptics(struct psm_softc *, packetbuf_t *,
mousestatus_t *, int *, int *, int *);
static int proc_synaptics_mux(struct psm_softc *, packetbuf_t *);
static void proc_versapad(struct psm_softc *, packetbuf_t *,
mousestatus_t *, int *, int *, int *);
static int proc_elantech(struct psm_softc *, packetbuf_t *,
@ -642,6 +641,7 @@ static probefunc_t enable_4dmouse;
static probefunc_t enable_4dplus;
static probefunc_t enable_mmanplus;
static probefunc_t enable_synaptics;
static probefunc_t enable_synaptics_mux;
static probefunc_t enable_trackpoint;
static probefunc_t enable_versapad;
static probefunc_t enable_elantech;
@ -662,6 +662,8 @@ static struct {
* WARNING: the order of probe is very important. Don't mess it
* unless you know what you are doing.
*/
{ MOUSE_MODEL_SYNAPTICS, /* Synaptics Touchpad on Active Mux */
0x00, MOUSE_PS2_PACKETSIZE, enable_synaptics_mux },
{ MOUSE_MODEL_NET, /* Genius NetMouse */
0x08, MOUSE_PS2INTELLI_PACKETSIZE, enable_gmouse },
{ MOUSE_MODEL_NETSCROLL, /* Genius NetScroll */
@ -1092,6 +1094,7 @@ static int
doopen(struct psm_softc *sc, int command_byte)
{
int stat[3];
int mux_enabled = FALSE;
/*
* FIXME: Synaptics TouchPad seems to go back to Relative Mode with
@ -1106,16 +1109,27 @@ doopen(struct psm_softc *sc, int command_byte)
* doesn't show any evidence of such a command.
*/
if (sc->hw.model == MOUSE_MODEL_SYNAPTICS) {
if (sc->muxport != PSM_NOMUX) {
mux_enabled = enable_aux_mux(sc->kbdc) >= 0;
if (mux_enabled)
set_active_aux_mux_port(sc->kbdc, sc->muxport);
else
log(LOG_ERR, "psm%d: failed to enable "
"active multiplexing mode.\n",
sc->unit);
}
mouse_ext_command(sc->kbdc, 1);
get_mouse_status(sc->kbdc, stat, 0, 3);
if ((SYNAPTICS_VERSION_GE(sc->synhw, 7, 5) ||
stat[1] == 0x46 || stat[1] == 0x47) &&
stat[1] == 0x47) &&
stat[2] == 0x40) {
synaptics_set_mode(sc, synaptics_preferred_mode(sc));
VLOG(5, (LOG_DEBUG, "psm%d: Synaptis Absolute Mode "
"hopefully restored\n",
sc->unit));
}
if (mux_enabled)
disable_aux_mux(sc->kbdc);
}
/*
@ -1364,6 +1378,7 @@ psmprobe(device_t dev)
#endif
#endif /* PSM_HOOKRESUME | PSM_HOOKAPM */
sc->flags = 0;
sc->muxport = PSM_NOMUX;
if (bootverbose)
++verbose;
@ -1833,7 +1848,7 @@ psm_register_synaptics(device_t dev)
evdev_support_key(evdev_a, BTN_0 + i);
error = evdev_register_mtx(evdev_a, &Giant);
if (!error && sc->synhw.capPassthrough) {
if (!error && (sc->synhw.capPassthrough || sc->muxport != PSM_NOMUX)) {
guest_model = sc->tpinfo.sysctl_tree != NULL ?
MOUSE_MODEL_TRACKPOINT : MOUSE_MODEL_GENERIC;
error = psm_register(dev, guest_model);
@ -2941,6 +2956,9 @@ psmintr(void *arg)
int c;
packetbuf_t *pb;
if (aux_mux_is_enabled(sc->kbdc))
VLOG(2, (LOG_DEBUG, "psmintr: active multiplexing mode is not "
"supported!\n"));
/* read until there is nothing to read */
while((c = read_aux_data_no_wait(sc->kbdc)) != -1) {
@ -3292,7 +3310,7 @@ proc_synaptics(struct psm_softc *sc, packetbuf_t *pb, mousestatus_t *ms,
* Handle packets from the guest device. See:
* Synaptics PS/2 TouchPad Interfacing Guide, Section 5.1
*/
if (sc->synhw.capPassthrough) {
if (sc->synhw.capPassthrough || sc->muxport != PSM_NOMUX) {
*x = ((pb->ipacket[1] & 0x10) ?
pb->ipacket[4] - 256 : pb->ipacket[4]);
*y = ((pb->ipacket[1] & 0x20) ?
@ -3591,6 +3609,83 @@ SYNAPTICS_END:
return (0);
}
static int
proc_synaptics_mux(struct psm_softc *sc, packetbuf_t *pb)
{
int butt;
/*
* Convert 3-byte interleaved mixture of Synaptics and generic mouse
* packets into plain 6-byte Synaptics packet protocol.
* While in hidden multiplexing mode KBC does some editing of the
* packet stream. It remembers the button bits from the last packet
* received from each device, and replaces the button bits of every
* packet with the logical OR of all devices’ most recent button bits.
* This button crosstalk should be filtered out as Synaptics and
* generic mouse encode middle button presses in a different way.
*/
switch (pb->ipacket[0] & 0xc0) {
case 0x80: /* First 3 bytes of Synaptics packet */
bcopy(pb->ipacket, sc->muxsave, 3);
/* Compute middle mouse button supression timeout. */
sc->muxmidtimeout.tv_sec = 0;
sc->muxmidtimeout.tv_usec = 50000; /* ~2-3 ints */
timevaladd(&sc->muxmidtimeout, &sc->lastsoftintr);
return (1);
case 0xc0: /* Second 3 bytes of Synaptics packet */
/* Join two 3-bytes absolute packets */
bcopy(pb->ipacket, pb->ipacket + 3, 3);
bcopy(sc->muxsave, pb->ipacket, 3);
/* Prefer trackpoint buttons over touchpad's */
pb->ipacket[0] &= ~(0x08 | sc->muxmsbuttons);
pb->ipacket[3] &= ~(0x08 | sc->muxmsbuttons);
butt = (pb->ipacket[3] & 0x03) << 2 | (pb->ipacket[0] & 0x03);
/* Add hysteresis to remove spurious middle button events */
if (butt != sc->muxtpbuttons && sc->fpcount < 1) {
pb->ipacket[0] &= 0xfc;
pb->ipacket[0] |= sc->muxtpbuttons & 0x03;
pb->ipacket[3] &= 0xfc;
pb->ipacket[3] |= sc->muxtpbuttons >> 2 & 0x03;
++sc->fpcount;
} else {
sc->fpcount = 0;
sc->muxtpbuttons = butt;
}
/* Filter out impossible w induced by middle trackpoint btn */
if (sc->synhw.capExtended && !sc->synhw.capPassthrough &&
(pb->ipacket[0] & 0x34) == 0x04 &&
(pb->ipacket[3] & 0x04) == 0x04) {
pb->ipacket[0] &= 0xfb;
pb->ipacket[3] &= 0xfb;
}
sc->muxsave[0] &= 0x30;
break;
default: /* Generic mouse (Trackpoint) packet */
/* Filter out middle button events induced by some w values */
if (sc->muxmsbuttons & 0x03 || pb->ipacket[0] & 0x03 ||
(timevalcmp(&sc->lastsoftintr, &sc->muxmidtimeout, <=) &&
(sc->muxsave[0] & 0x30 || sc->muxsave[2] > 8)))
pb->ipacket[0] &= 0xfb;
sc->muxmsbuttons = pb->ipacket[0] & 0x07;
/* Convert to Synaptics pass-through protocol */
pb->ipacket[4] = pb->ipacket[1];
pb->ipacket[5] = pb->ipacket[2];
pb->ipacket[1] = pb->ipacket[0];
pb->ipacket[2] = 0;
pb->ipacket[0] = 0x84 | (sc->muxtpbuttons & 0x03);
pb->ipacket[3] = 0xc4 | (sc->muxtpbuttons >> 2 & 0x03);
}
VLOG(4, (LOG_DEBUG, "synaptics: %02x %02x %02x %02x %02x %02x\n",
pb->ipacket[0], pb->ipacket[1], pb->ipacket[2],
pb->ipacket[3], pb->ipacket[4], pb->ipacket[5]));
pb->inputbytes = MOUSE_SYNAPTICS_PACKETSIZE;
return (0);
}
static int
psmpalmdetect(struct psm_softc *sc, finger_t *f, int nfingers)
{
@ -4929,6 +5024,10 @@ psmsoftintr(void *arg)
break;
case MOUSE_MODEL_SYNAPTICS:
if (pb->inputbytes == MOUSE_PS2_PACKETSIZE)
if (proc_synaptics_mux(sc, pb))
goto next;
if (proc_synaptics(sc, pb, &ms, &x, &y, &z) != 0) {
VLOG(3, (LOG_DEBUG, "synaptics: "
"packet rejected\n"));
@ -6039,6 +6138,60 @@ synaptics_set_mode(struct psm_softc *sc, int mode_byte) {
}
}
/*
* AUX MUX detection code should be placed at very beginning of probe sequence
* at least before 4-byte protocol mouse probes e.g. MS IntelliMouse probe as
* latter can trigger switching the MUX to incompatible state.
*/
static int
enable_synaptics_mux(struct psm_softc *sc, enum probearg arg)
{
KBDC kbdc = sc->kbdc;
int port, version;
int probe = FALSE;
int active_ports_count = 0;
int active_ports_mask = 0;
version = enable_aux_mux(kbdc);
if (version == -1)
return (FALSE);
for (port = 0; port < KBDC_AUX_MUX_NUM_PORTS; port++) {
VLOG(3, (LOG_DEBUG, "aux_mux: ping port %d\n", port));
set_active_aux_mux_port(kbdc, port);
if (enable_aux_dev(kbdc) && disable_aux_dev(kbdc)) {
active_ports_count++;
active_ports_mask |= 1 << port;
}
}
if (verbose >= 2)
printf("Active Multiplexing PS/2 controller v%d.%d with %d "
"active port(s)\n", version >> 4 & 0x0f, version & 0x0f,
active_ports_count);
/* psm has a special support for GenMouse + SynTouchpad combination */
if (active_ports_count >= 2) {
for (port = 0; port < KBDC_AUX_MUX_NUM_PORTS; port++) {
if ((active_ports_mask & 1 << port) == 0)
continue;
VLOG(3, (LOG_DEBUG, "aux_mux: probe port %d\n", port));
set_active_aux_mux_port(kbdc, port);
probe = enable_synaptics(sc, arg);
if (probe) {
if (arg == PROBE)
sc->muxport = port;
break;
}
}
}
/* IRQ handler does not support active multiplexing mode */
disable_aux_mux(kbdc);
return (probe);
}
static int
enable_synaptics(struct psm_softc *sc, enum probearg arg)
{
@ -6047,7 +6200,7 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
KBDC kbdc = sc->kbdc;
synapticshw_t synhw;
int status[3];
int buttons, middle_byte;
int buttons;
VLOG(3, (LOG_DEBUG, "synaptics: BEGIN init\n"));
@ -6064,8 +6217,7 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
return (FALSE);
if (get_mouse_status(kbdc, status, 0, 3) != 3)
return (FALSE);
middle_byte = status[1];
if (middle_byte != 0x46 && middle_byte != 0x47)
if (status[1] != 0x47)
return (FALSE);
bzero(&synhw, sizeof(synhw));
@ -6076,15 +6228,7 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
printf("Synaptics Touchpad v%d.%d\n", synhw.infoMajor,
synhw.infoMinor);
/*
* Most synaptics touchpads return 0x47 in middle byte in responce to
* identify command as stated in p.4.4 of "Synaptics PS/2 TouchPad
* Interfacing Guide" and we only support v4.0 or better. But some
* devices return 0x46 here and have a different numbering scheme.
* In the case of 0x46, we allow versions as low as v2.0
*/
if ((middle_byte == 0x47 && synhw.infoMajor < 4) ||
(middle_byte == 0x46 && synhw.infoMajor < 2)) {
if (synhw.infoMajor < 4) {
printf(" Unsupported (pre-v4) Touchpad detected\n");
return (FALSE);
}
@ -6125,7 +6269,7 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
return (FALSE);
if (get_mouse_status(kbdc, status, 0, 3) != 3)
return (FALSE);
if (!SYNAPTICS_VERSION_GE(synhw, 7, 5) && status[1] != middle_byte) {
if (!SYNAPTICS_VERSION_GE(synhw, 7, 5) && status[1] != 0x47) {
printf(" Failed to read extended capability bits\n");
return (FALSE);
}
@ -6134,29 +6278,10 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
sc->unit);
psmcpnp_sc = (psmcpnp != NULL) ? device_get_softc(psmcpnp) : NULL;
/*
* Set conservative defaults for 0x46 middle byte touchpads
* as ExtendedQueries return bogus data.
*/
if (middle_byte == 0x46) {
synhw.capExtended = 1;
synhw.capPalmDetect = 1;
synhw.capPassthrough = 1;
synhw.capMultiFinger = 1;
synhw.maximumXCoord = SYNAPTICS_DEFAULT_MAX_X;
synhw.maximumYCoord = SYNAPTICS_DEFAULT_MAX_Y;
synhw.minimumXCoord = SYNAPTICS_DEFAULT_MIN_X;
synhw.minimumYCoord = SYNAPTICS_DEFAULT_MIN_Y;
/* Enable multitouch mode for HW v8.1 devices */
if (psmcpnp_sc != NULL &&
psmcpnp_sc->type == PSMCPNP_HPSYN81)
synhw.capReportsV = 1;
} else
synhw.capExtended = (status[0] & 0x80) != 0;
/* Set the different capabilities when they exist. */
buttons = 0;
if (synhw.capExtended && middle_byte == 0x47) {
synhw.capExtended = (status[0] & 0x80) != 0;
if (synhw.capExtended) {
synhw.nExtendedQueries = (status[0] & 0x70) >> 4;
synhw.capMiddle = (status[0] & 0x04) != 0;
synhw.capPassthrough = (status[2] & 0x80) != 0;
@ -6278,8 +6403,12 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
synhw.maximumYCoord = (status[2] << 5) |
((status[1] & 0xf0) >> 3);
} else {
synhw.maximumXCoord = SYNAPTICS_DEFAULT_MAX_X;
synhw.maximumYCoord = SYNAPTICS_DEFAULT_MAX_Y;
/*
* Typical bezel limits. Taken from 'Synaptics
* PS/2 * TouchPad Interfacing Guide' p.3.2.3.
*/
synhw.maximumXCoord = 5472;
synhw.maximumYCoord = 4448;
}
if (synhw.capReportsMin) {
@ -6295,8 +6424,12 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
synhw.minimumYCoord = (status[2] << 5) |
((status[1] & 0xf0) >> 3);
} else {
synhw.minimumXCoord = SYNAPTICS_DEFAULT_MIN_X;
synhw.minimumYCoord = SYNAPTICS_DEFAULT_MIN_Y;
/*
* Typical bezel limits. Taken from 'Synaptics
* PS/2 * TouchPad Interfacing Guide' p.3.2.3.
*/
synhw.minimumXCoord = 1472;
synhw.minimumYCoord = 1408;
}
/*
@ -6382,7 +6515,7 @@ enable_synaptics(struct psm_softc *sc, enum probearg arg)
return (FALSE);
if (get_mouse_status(kbdc, status, 0, 3) != 3)
return (FALSE);
if (!SYNAPTICS_VERSION_GE(synhw, 7, 5) && status[1] != middle_byte) {
if (!SYNAPTICS_VERSION_GE(synhw, 7, 5) && status[1] != 0x47) {
printf(" Failed to read mode byte\n");
return (FALSE);
}
@ -7205,12 +7338,6 @@ static struct isa_pnp_id forcepad_ids[] = {
{ 0 }
};
/* List of HW v8.1 synaptics touchpads erroneously detected as HW v2.0 */
static struct isa_pnp_id hpsyn81_ids[] = {
{ 0x9e012e4f, "HP PS/2 trackpad port" }, /* SYN019E, EB 9470 */
{ 0 }
};
static int
create_a_copy(device_t atkbdc, device_t me)
{
@ -7244,8 +7371,6 @@ psmcpnp_probe(device_t dev)
if (ISA_PNP_PROBE(device_get_parent(dev), dev, forcepad_ids) == 0)
sc->type = PSMCPNP_FORCEPAD;
else if(ISA_PNP_PROBE(device_get_parent(dev), dev, hpsyn81_ids) == 0)
sc->type = PSMCPNP_HPSYN81;
else if (ISA_PNP_PROBE(device_get_parent(dev), dev, psmcpnp_ids) == 0)
sc->type = PSMCPNP_GENERIC;
else

20
sys/dev/sfxge/common/ef10_ev.c
View File

@ -466,7 +466,7 @@ ef10_ev_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
@ -480,7 +480,8 @@ ef10_ev_qcreate(
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
if (!ISP2(ndescs) ||
(ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
rc = EINVAL;
goto fail1;
}
@ -529,7 +530,8 @@ ef10_ev_qcreate(
* it will choose the best settings for low latency, otherwise
* it will choose the best settings for throughput.
*/
rc = efx_mcdi_init_evq_v2(enp, index, esmp, n, irq, us, flags);
rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
flags);
if (rc != 0)
goto fail4;
} else {
@ -545,7 +547,7 @@ ef10_ev_qcreate(
* to choose it.)
*/
boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, us, flags,
rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
low_latency);
if (rc != 0)
goto fail5;
@ -576,7 +578,7 @@ ef10_ev_qdestroy(
EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
enp->en_family == EFX_FAMILY_MEDFORD);
(void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
(void) efx_mcdi_fini_evq(enp, eep->ee_index);
}
__checkReturn efx_rc_t
@ -1347,9 +1349,11 @@ ef10_ev_rxlabel_init(
__in efx_rxq_type_t type)
{
efx_evq_rxq_state_t *eersp;
boolean_t packed_stream = (type >= EFX_RXQ_TYPE_PACKED_STREAM_1M) &&
(type <= EFX_RXQ_TYPE_PACKED_STREAM_64K);
#if EFSYS_OPT_RX_PACKED_STREAM
boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
#endif
_NOTE(ARGUNUSED(type))
EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
eersp = &eep->ee_rxq_state[label];
@ -1387,8 +1391,6 @@ ef10_ev_rxlabel_init(
EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
EFX_RX_PACKED_STREAM_MAX_CREDITS);
}
#else
EFSYS_ASSERT(!packed_stream);
#endif
}

10
sys/dev/sfxge/common/ef10_filter.c
View File

@ -998,7 +998,7 @@ ef10_filter_supported_filters(
size_t list_length;
uint32_t i;
efx_rc_t rc;
uint32_t all_filter_flags =
efx_filter_match_flags_t all_filter_flags =
(EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_LOC_HOST |
EFX_FILTER_MATCH_REM_MAC | EFX_FILTER_MATCH_REM_PORT |
EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_PORT |
@ -1246,8 +1246,8 @@ typedef struct ef10_filter_encap_entry_s {
uint32_t inner_frame_match;
} ef10_filter_encap_entry_t;
#define EF10_ENCAP_FILTER_ENTRY(ipv, encap_type, inner_frame_match) \
{ EFX_ETHER_TYPE_##ipv, EFX_TUNNEL_PROTOCOL_##encap_type, \
#define EF10_ENCAP_FILTER_ENTRY(ipv, encap_type, inner_frame_match) \
{ EFX_ETHER_TYPE_##ipv, EFX_TUNNEL_PROTOCOL_##encap_type, \
EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_##inner_frame_match }
static ef10_filter_encap_entry_t ef10_filter_encap_list[] = {
@ -1308,8 +1308,8 @@ ef10_filter_insert_encap_filters(
*/
if ((mulcst == B_FALSE) &&
(encap_filter->inner_frame_match ==
EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST))
continue;
EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST))
continue;
efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO,
filter_flags,

70
sys/dev/sfxge/common/ef10_impl.h
View File

@ -52,8 +52,9 @@ extern "C" {
*/
#define EF10_NVRAM_CHUNK 0x80
/* Alignment requirement for value written to RX WPTR:
* the WPTR must be aligned to an 8 descriptor boundary
/*
* Alignment requirement for value written to RX WPTR: the WPTR must be aligned
* to an 8 descriptor boundary.
*/
#define EF10_RX_WPTR_ALIGN 8
@ -82,7 +83,7 @@ ef10_ev_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
@ -507,8 +508,7 @@ ef10_nvram_buffer_find_item_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
);
__out uint32_t *startp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_find_end(
@ -516,8 +516,7 @@ ef10_nvram_buffer_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
);
__out uint32_t *endp);
extern __checkReturn __success(return != B_FALSE) boolean_t
ef10_nvram_buffer_find_item(
@ -526,8 +525,7 @@ ef10_nvram_buffer_find_item(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_get_item(
@ -539,8 +537,7 @@ ef10_nvram_buffer_get_item(
__out_bcount_part(item_max_size, *lengthp)
caddr_t itemp,
__in size_t item_max_size,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_insert_item(
@ -550,8 +547,7 @@ ef10_nvram_buffer_insert_item(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_delete_item(
@ -560,15 +556,13 @@ ef10_nvram_buffer_delete_item(
__in size_t buffer_size,
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end
);
__in uint32_t end);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_finish(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
#endif /* EFSYS_OPT_NVRAM */
@ -670,7 +664,7 @@ ef10_tx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint16_t flags,
__in efx_evq_t *eep,
@ -681,13 +675,13 @@ extern void
ef10_tx_qdestroy(
__in efx_txq_t *etp);
extern __checkReturn efx_rc_t
extern __checkReturn efx_rc_t
ef10_tx_qpost(
__in efx_txq_t *etp,
__in_ecount(n) efx_buffer_t *eb,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp);
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_buffer_t *ebp,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp);
extern void
ef10_tx_qpush(
@ -797,7 +791,7 @@ ef10_tx_qstats_update(
typedef uint32_t efx_piobuf_handle_t;
#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
extern __checkReturn efx_rc_t
ef10_nic_pio_alloc(
@ -956,14 +950,14 @@ ef10_rx_prefix_pktlen(
__in uint8_t *buffer,
__out uint16_t *lengthp);
extern void
extern void
ef10_rx_qpost(
__in efx_rxq_t *erp,
__in_ecount(n) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int n,
__in unsigned int completed,
__in unsigned int added);
__in efx_rxq_t *erp,
__in_ecount(ndescs) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int ndescs,
__in unsigned int completed,
__in unsigned int added);
extern void
ef10_rx_qpush(
@ -985,9 +979,11 @@ ef10_rx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
__in uint32_t type_data,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__in efx_rxq_t *erp);
@ -1036,7 +1032,7 @@ typedef struct ef10_filter_entry_s {
* IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
* multicast inner frames.
*/
#define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
#define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
typedef struct ef10_filter_table_s {
ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
@ -1203,9 +1199,9 @@ ef10_external_port_mapping(
/* Minimum space for packet in packed stream mode */
#define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
EFX_MAC_PDU_MIN + \
EFX_RX_PACKED_STREAM_ALIGNMENT, \
EFX_RX_PACKED_STREAM_ALIGNMENT)
EFX_MAC_PDU_MIN + \
EFX_RX_PACKED_STREAM_ALIGNMENT, \
EFX_RX_PACKED_STREAM_ALIGNMENT)
/* Maximum number of credits */
#define EFX_RX_PACKED_STREAM_MAX_CREDITS 127

3
sys/dev/sfxge/common/ef10_nvram.c
View File

@ -675,6 +675,7 @@ ef10_nvram_buffer_validate(
int pos;
efx_rc_t rc;
_NOTE(ARGUNUSED(enp, partn))
EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK);
if ((partn_data == NULL) || (partn_size == 0)) {
@ -1285,6 +1286,8 @@ ef10_nvram_buf_read_tlv(
caddr_t value;
efx_rc_t rc;
_NOTE(ARGUNUSED(enp))
if ((seg_data == NULL) || (max_seg_size == 0)) {
rc = EINVAL;
goto fail1;

2
sys/dev/sfxge/common/ef10_phy.c
View File

@ -283,7 +283,9 @@ ef10_phy_reconfigure(
uint8_t payload[MAX(MC_CMD_SET_LINK_IN_LEN,
MC_CMD_SET_LINK_OUT_LEN)];
uint32_t cap_mask;
#if EFSYS_OPT_PHY_LED_CONTROL
unsigned int led_mode;
#endif
unsigned int speed;
boolean_t supported;
efx_rc_t rc;

118
sys/dev/sfxge/common/ef10_rx.c
View File

@ -41,19 +41,20 @@ __FBSDID("$FreeBSD$");
static __checkReturn efx_rc_t
efx_mcdi_init_rxq(
__in efx_nic_t *enp,
__in uint32_t size,
__in uint32_t ndescs,
__in uint32_t target_evq,
__in uint32_t label,
__in uint32_t instance,
__in efsys_mem_t *esmp,
__in boolean_t disable_scatter,
__in boolean_t want_inner_classes,
__in uint32_t ps_bufsize)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_mcdi_req_t req;
uint8_t payload[MAX(MC_CMD_INIT_RXQ_EXT_IN_LEN,
MC_CMD_INIT_RXQ_EXT_OUT_LEN)];
int npages = EFX_RXQ_NBUFS(size);
int npages = EFX_RXQ_NBUFS(ndescs);
int i;
efx_qword_t *dma_addr;
uint64_t addr;
@ -61,16 +62,15 @@ efx_mcdi_init_rxq(
uint32_t dma_mode;
boolean_t want_outer_classes;
/* If this changes, then the payload size might need to change. */
EFSYS_ASSERT3U(MC_CMD_INIT_RXQ_OUT_LEN, ==, 0);
EFSYS_ASSERT3U(size, <=, EFX_RXQ_MAXNDESCS);
EFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS);
if (ps_bufsize > 0)
dma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;
else
dma_mode = MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET;
if (encp->enc_tunnel_encapsulations_supported != 0) {
if (encp->enc_tunnel_encapsulations_supported != 0 &&
!want_inner_classes) {
/*
* WANT_OUTER_CLASSES can only be specified on hardware which
* supports tunnel encapsulation offloads, even though it is
@ -96,7 +96,7 @@ efx_mcdi_init_rxq(
req.emr_out_buf = payload;
req.emr_out_length = MC_CMD_INIT_RXQ_EXT_OUT_LEN;
MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, size);
MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);
MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, target_evq);
MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);
MCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);
@ -222,7 +222,13 @@ efx_mcdi_rss_context_alloc(
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
EVB_PORT_ID_ASSIGNED);
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
/* NUM_QUEUES is only used to validate indirection table offsets */
/*
* For exclusive contexts, NUM_QUEUES is only used to validate
* indirection table offsets.
* For shared contexts, the provided context will spread traffic over
* NUM_QUEUES many queues.
*/
MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
efx_mcdi_execute(enp, &req);
@ -740,20 +746,22 @@ ef10_rx_prefix_hash(
#define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
#endif
void
void
ef10_rx_qpost(
__in efx_rxq_t *erp,
__in_ecount(n) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int n,
__in unsigned int completed,
__in unsigned int added)
__in efx_rxq_t *erp,
__in_ecount(ndescs) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int ndescs,
__in unsigned int completed,
__in unsigned int added)
{
efx_qword_t qword;
unsigned int i;
unsigned int offset;
unsigned int id;
_NOTE(ARGUNUSED(completed))
#if EFSYS_OPT_RX_PACKED_STREAM
/*
* Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
@ -764,11 +772,11 @@ ef10_rx_qpost(
#endif
/* The client driver must not overfill the queue */
EFSYS_ASSERT3U(added - completed + n, <=,
EFSYS_ASSERT3U(added - completed + ndescs, <=,
EFX_RXQ_LIMIT(erp->er_mask + 1));
id = added & (erp->er_mask);
for (i = 0; i < n; i++) {
for (i = 0; i < ndescs; i++) {
EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
unsigned int, id, efsys_dma_addr_t, addrp[i],
size_t, size);
@ -945,18 +953,21 @@ ef10_rx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
__in uint32_t type_data,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__in efx_rxq_t *erp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_rc_t rc;
boolean_t disable_scatter;
boolean_t want_inner_classes;
unsigned int ps_buf_size;
_NOTE(ARGUNUSED(id, erp))
_NOTE(ARGUNUSED(id, erp, type_data))
EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
@ -965,7 +976,8 @@ ef10_rx_qcreate(
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
if (!ISP2(ndescs) ||
(ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
rc = EINVAL;
goto fail1;
}
@ -976,29 +988,35 @@ ef10_rx_qcreate(
switch (type) {
case EFX_RXQ_TYPE_DEFAULT:
case EFX_RXQ_TYPE_SCATTER:
ps_buf_size = 0;
break;
#if EFSYS_OPT_RX_PACKED_STREAM
case EFX_RXQ_TYPE_PACKED_STREAM_1M:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
break;
case EFX_RXQ_TYPE_PACKED_STREAM_512K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
break;
case EFX_RXQ_TYPE_PACKED_STREAM_256K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
break;
case EFX_RXQ_TYPE_PACKED_STREAM_128K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
break;
case EFX_RXQ_TYPE_PACKED_STREAM_64K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
case EFX_RXQ_TYPE_PACKED_STREAM:
switch (type_data) {
case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
break;
case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
break;
case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
break;
case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
break;
case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
break;
default:
rc = ENOTSUP;
goto fail3;
}
break;
#endif /* EFSYS_OPT_RX_PACKED_STREAM */
default:
rc = ENOTSUP;
goto fail3;
goto fail4;
}
#if EFSYS_OPT_RX_PACKED_STREAM
@ -1006,13 +1024,13 @@ ef10_rx_qcreate(
/* Check if datapath firmware supports packed stream mode */
if (encp->enc_rx_packed_stream_supported == B_FALSE) {
rc = ENOTSUP;
goto fail4;
goto fail5;
}
/* Check if packed stream allows configurable buffer sizes */
if ((type != EFX_RXQ_TYPE_PACKED_STREAM_1M) &&
if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
(encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
rc = ENOTSUP;
goto fail5;
goto fail6;
}
}
#else /* EFSYS_OPT_RX_PACKED_STREAM */
@ -1020,14 +1038,20 @@ ef10_rx_qcreate(
#endif /* EFSYS_OPT_RX_PACKED_STREAM */
/* Scatter can only be disabled if the firmware supports doing so */
if (type == EFX_RXQ_TYPE_SCATTER)
if (flags & EFX_RXQ_FLAG_SCATTER)
disable_scatter = B_FALSE;
else
disable_scatter = encp->enc_rx_disable_scatter_supported;
if ((rc = efx_mcdi_init_rxq(enp, n, eep->ee_index, label, index,
esmp, disable_scatter, ps_buf_size)) != 0)
goto fail6;
if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
want_inner_classes = B_TRUE;
else
want_inner_classes = B_FALSE;
if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep->ee_index, label, index,
esmp, disable_scatter, want_inner_classes,
ps_buf_size)) != 0)
goto fail7;
erp->er_eep = eep;
erp->er_label = label;
@ -1038,16 +1062,20 @@ ef10_rx_qcreate(
return (0);
fail7:
EFSYS_PROBE(fail7);
#if EFSYS_OPT_RX_PACKED_STREAM
fail6:
EFSYS_PROBE(fail6);
#if EFSYS_OPT_RX_PACKED_STREAM
fail5:
EFSYS_PROBE(fail5);
#endif /* EFSYS_OPT_RX_PACKED_STREAM */
fail4:
EFSYS_PROBE(fail4);
#endif /* EFSYS_OPT_RX_PACKED_STREAM */
#if EFSYS_OPT_RX_PACKED_STREAM
fail3:
EFSYS_PROBE(fail3);
#endif /* EFSYS_OPT_RX_PACKED_STREAM */
fail2:
EFSYS_PROBE(fail2);
fail1:

54
sys/dev/sfxge/common/ef10_tx.c
View File

@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
static __checkReturn efx_rc_t
efx_mcdi_init_txq(
__in efx_nic_t *enp,
__in uint32_t size,
__in uint32_t ndescs,
__in uint32_t target_evq,
__in uint32_t label,
__in uint32_t instance,
@ -69,7 +69,7 @@ efx_mcdi_init_txq(
EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
npages = EFX_TXQ_NBUFS(size);
npages = EFX_TXQ_NBUFS(ndescs);
if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
rc = EINVAL;
goto fail1;
@ -82,7 +82,7 @@ efx_mcdi_init_txq(
req.emr_out_buf = payload;
req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, ndescs);
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
@ -194,7 +194,7 @@ ef10_tx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint16_t flags,
__in efx_evq_t *eep,
@ -215,8 +215,8 @@ ef10_tx_qcreate(
goto fail1;
}
if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
esmp)) != 0)
if ((rc = efx_mcdi_init_txq(enp, ndescs, eep->ee_index, label, index,
flags, esmp)) != 0)
goto fail2;
/*
@ -436,24 +436,24 @@ fail1:
return (rc);
}
__checkReturn efx_rc_t
__checkReturn efx_rc_t
ef10_tx_qpost(
__in efx_txq_t *etp,
__in_ecount(n) efx_buffer_t *eb,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp)
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_buffer_t *eb,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp)
{
unsigned int added = *addedp;
unsigned int i;
efx_rc_t rc;
if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
rc = ENOSPC;
goto fail1;
}
for (i = 0; i < n; i++) {
for (i = 0; i < ndescs; i++) {
efx_buffer_t *ebp = &eb[i];
efsys_dma_addr_t addr = ebp->eb_addr;
size_t size = ebp->eb_size;
@ -559,24 +559,24 @@ ef10_tx_qpush(
}
}
__checkReturn efx_rc_t
__checkReturn efx_rc_t
ef10_tx_qdesc_post(
__in efx_txq_t *etp,
__in_ecount(n) efx_desc_t *ed,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp)
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_desc_t *ed,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp)
{
unsigned int added = *addedp;
unsigned int i;
efx_rc_t rc;
if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
rc = ENOSPC;
goto fail1;
}
for (i = 0; i < n; i++) {
for (i = 0; i < ndescs; i++) {
efx_desc_t *edp = &ed[i];
unsigned int id;
size_t offset;
@ -588,7 +588,7 @@ ef10_tx_qdesc_post(
}
EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
unsigned int, added, unsigned int, n);
unsigned int, added, unsigned int, ndescs);
EFX_TX_QSTAT_INCR(etp, TX_POST);
@ -609,6 +609,8 @@ ef10_tx_qdesc_dma_create(
__in boolean_t eop,
__out efx_desc_t *edp)
{
_NOTE(ARGUNUSED(etp))
/* No limitations on boundary crossing */
EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
@ -632,6 +634,8 @@ ef10_tx_qdesc_tso_create(
__in uint8_t tcp_flags,
__out efx_desc_t *edp)
{
_NOTE(ARGUNUSED(etp))
EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
uint16_t, ipv4_id, uint32_t, tcp_seq,
uint8_t, tcp_flags);
@ -654,6 +658,8 @@ ef10_tx_qdesc_tso2_create(
__out_ecount(count) efx_desc_t *edp,
__in int count)
{
_NOTE(ARGUNUSED(etp, count))
EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
uint16_t, ipv4_id, uint32_t, tcp_seq,
uint16_t, tcp_mss);
@ -683,6 +689,8 @@ ef10_tx_qdesc_vlantci_create(
__in uint16_t tci,
__out efx_desc_t *edp)
{
_NOTE(ARGUNUSED(etp))
EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
uint16_t, tci);

221
sys/dev/sfxge/common/efx.h
View File

@ -44,13 +44,13 @@ extern "C" {
#endif
#define EFX_STATIC_ASSERT(_cond) \
((void)sizeof(char[(_cond) ? 1 : -1]))
((void)sizeof (char[(_cond) ? 1 : -1]))
#define EFX_ARRAY_SIZE(_array) \
(sizeof(_array) / sizeof((_array)[0]))
(sizeof (_array) / sizeof ((_array)[0]))
#define EFX_FIELD_OFFSET(_type, _field) \
((size_t) &(((_type *)0)->_field))
((size_t)&(((_type *)0)->_field))
/* The macro expands divider twice */
#define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
@ -562,7 +562,7 @@ efx_mac_stats_get_mask(
#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
(1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
(1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
#define EFX_MAC_STATS_SIZE 0x400
@ -631,7 +631,7 @@ efx_mon_init(
#define EFX_MON_STATS_PAGE_SIZE 0x100
#define EFX_MON_MASK_ELEMENT_SIZE 32
/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
/* START MKCONFIG GENERATED MonitorHeaderStatsBlock aa0233c80156308e */
typedef enum efx_mon_stat_e {
EFX_MON_STAT_2_5V,
EFX_MON_STAT_VCCP1,
@ -710,6 +710,8 @@ typedef enum efx_mon_stat_e {
EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
EFX_MON_STAT_BOARD_FRONT_TEMP,
EFX_MON_STAT_BOARD_BACK_TEMP,
EFX_MON_STAT_I1V8,
EFX_MON_STAT_I2V5,
EFX_MON_NSTATS
} efx_mon_stat_t;
@ -910,7 +912,8 @@ typedef enum efx_phy_media_type_e {
EFX_PHY_MEDIA_NTYPES
} efx_phy_media_type_t;
/* Get the type of medium currently used. If the board has ports for
/*
* Get the type of medium currently used. If the board has ports for
* modules, a module is present, and we recognise the media type of
* the module, then this will be the media type of the module.
* Otherwise it will be the media type of the port.
@ -1011,7 +1014,7 @@ typedef enum efx_bist_type_e {
EFX_BIST_TYPE_PHY_CABLE_SHORT,
EFX_BIST_TYPE_PHY_CABLE_LONG,
EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
EFX_BIST_TYPE_REG, /* Test the register memories */
EFX_BIST_TYPE_NTYPES,
} efx_bist_type_t;
@ -1042,8 +1045,10 @@ typedef enum efx_bist_value_e {
EFX_BIST_PHY_CABLE_STATUS_C,
EFX_BIST_PHY_CABLE_STATUS_D,
EFX_BIST_FAULT_CODE,
/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
* response. */
/*
* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
* response.
*/
EFX_BIST_MEM_TEST,
EFX_BIST_MEM_ADDR,
EFX_BIST_MEM_BUS,
@ -1505,13 +1510,13 @@ efx_bootcfg_copy_sector(
extern efx_rc_t
efx_bootcfg_read(
__in efx_nic_t *enp,
__out_bcount(size) caddr_t data,
__out_bcount(size) uint8_t *data,
__in size_t size);
extern efx_rc_t
efx_bootcfg_write(
__in efx_nic_t *enp,
__in_bcount(size) caddr_t data,
__in_bcount(size) uint8_t *data,
__in size_t size);
#endif /* EFSYS_OPT_BOOTCFG */
@ -1638,7 +1643,7 @@ efx_ev_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
@ -1795,8 +1800,7 @@ typedef __checkReturn boolean_t
typedef __checkReturn boolean_t
(*efx_mac_stats_ev_t)(
__in_opt void *arg,
__in uint32_t generation
);
__in uint32_t generation);
#endif /* EFSYS_OPT_MAC_STATS */
@ -2002,15 +2006,26 @@ efx_pseudo_hdr_pkt_length_get(
typedef enum efx_rxq_type_e {
EFX_RXQ_TYPE_DEFAULT,
EFX_RXQ_TYPE_SCATTER,
EFX_RXQ_TYPE_PACKED_STREAM_1M,
EFX_RXQ_TYPE_PACKED_STREAM_512K,
EFX_RXQ_TYPE_PACKED_STREAM_256K,
EFX_RXQ_TYPE_PACKED_STREAM_128K,
EFX_RXQ_TYPE_PACKED_STREAM_64K,
EFX_RXQ_TYPE_PACKED_STREAM,
EFX_RXQ_NTYPES
} efx_rxq_type_t;
/*
* Dummy flag to be used instead of 0 to make it clear that the argument
* is receive queue flags.
*/
#define EFX_RXQ_FLAG_NONE 0x0
#define EFX_RXQ_FLAG_SCATTER 0x1
/*
* If tunnels are supported and Rx event can provide information about
* either outer or inner packet classes (e.g. SFN8xxx adapters with
* full-feature firmware variant running), outer classes are requested by
* default. However, if the driver supports tunnels, the flag allows to
* request inner classes which are required to be able to interpret inner
* Rx checksum offload results.
*/
#define EFX_RXQ_FLAG_INNER_CLASSES 0x2
extern __checkReturn efx_rc_t
efx_rx_qcreate(
__in efx_nic_t *enp,
@ -2018,11 +2033,33 @@ efx_rx_qcreate(
__in unsigned int label,
__in efx_rxq_type_t type,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__deref_out efx_rxq_t **erpp);
#if EFSYS_OPT_RX_PACKED_STREAM
#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
extern __checkReturn efx_rc_t
efx_rx_qcreate_packed_stream(
__in efx_nic_t *enp,
__in unsigned int index,
__in unsigned int label,
__in uint32_t ps_buf_size,
__in efsys_mem_t *esmp,
__in size_t ndescs,
__in efx_evq_t *eep,
__deref_out efx_rxq_t **erpp);
#endif
typedef struct efx_buffer_s {
efsys_dma_addr_t eb_addr;
size_t eb_size;
@ -2033,14 +2070,14 @@ typedef struct efx_desc_s {
efx_qword_t ed_eq;
} efx_desc_t;
extern void
extern void
efx_rx_qpost(
__in efx_rxq_t *erp,
__in_ecount(n) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int n,
__in unsigned int completed,
__in unsigned int added);
__in efx_rxq_t *erp,
__in_ecount(ndescs) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int ndescs,
__in unsigned int completed,
__in unsigned int added);
extern void
efx_rx_qpush(
@ -2107,7 +2144,6 @@ efx_tx_fini(
#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
@ -2130,13 +2166,13 @@ efx_tx_qcreate(
__deref_out efx_txq_t **etpp,
__out unsigned int *addedp);
extern __checkReturn efx_rc_t
extern __checkReturn efx_rc_t
efx_tx_qpost(
__in efx_txq_t *etp,
__in_ecount(n) efx_buffer_t *eb,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp);
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_buffer_t *eb,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp);
extern __checkReturn efx_rc_t
efx_tx_qpace(
@ -2273,35 +2309,43 @@ efx_tx_qdestroy(
/* Filter is for TX */
#define EFX_FILTER_FLAG_TX 0x10
typedef unsigned int efx_filter_flags_t;
typedef uint8_t efx_filter_flags_t;
/*
* Flags which specify the fields to match on. The values are the same as in the
* MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
*/
typedef enum efx_filter_match_flags_e {
EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
* address */
EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
* address */
EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
* protocol */
/* For encapsulated packets, match all multicast inner frames */
EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST = 0x01000000,
/* For encapsulated packets, match all unicast inner frames */
EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST = 0x02000000,
/* Match otherwise-unmatched multicast and broadcast packets */
EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000,
/* Match otherwise-unmatched unicast packets */
EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000,
} efx_filter_match_flags_t;
/* Match by remote IP host address */
#define EFX_FILTER_MATCH_REM_HOST 0x00000001
/* Match by local IP host address */
#define EFX_FILTER_MATCH_LOC_HOST 0x00000002
/* Match by remote MAC address */
#define EFX_FILTER_MATCH_REM_MAC 0x00000004
/* Match by remote TCP/UDP port */
#define EFX_FILTER_MATCH_REM_PORT 0x00000008
/* Match by remote TCP/UDP port */
#define EFX_FILTER_MATCH_LOC_MAC 0x00000010
/* Match by local TCP/UDP port */
#define EFX_FILTER_MATCH_LOC_PORT 0x00000020
/* Match by Ether-type */
#define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
/* Match by inner VLAN ID */
#define EFX_FILTER_MATCH_INNER_VID 0x00000080
/* Match by outer VLAN ID */
#define EFX_FILTER_MATCH_OUTER_VID 0x00000100
/* Match by IP transport protocol */
#define EFX_FILTER_MATCH_IP_PROTO 0x00000200
/* For encapsulated packets, match all multicast inner frames */
#define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
/* For encapsulated packets, match all unicast inner frames */
#define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
/* Match otherwise-unmatched multicast and broadcast packets */
#define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
/* Match otherwise-unmatched unicast packets */
#define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
typedef uint32_t efx_filter_match_flags_t;
typedef enum efx_filter_priority_s {
EFX_FILTER_PRI_HINT = 0, /* Performance hint */
@ -2322,22 +2366,22 @@ typedef enum efx_filter_priority_s {
*/
typedef struct efx_filter_spec_s {
uint32_t efs_match_flags;
uint32_t efs_priority:2;
uint32_t efs_flags:6;
uint32_t efs_dmaq_id:12;
uint32_t efs_rss_context;
uint16_t efs_outer_vid;
uint16_t efs_inner_vid;
uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
uint16_t efs_ether_type;
uint8_t efs_ip_proto;
efx_tunnel_protocol_t efs_encap_type;
uint16_t efs_loc_port;
uint16_t efs_rem_port;
efx_oword_t efs_rem_host;
efx_oword_t efs_loc_host;
efx_filter_match_flags_t efs_match_flags;
uint8_t efs_priority;
efx_filter_flags_t efs_flags;
uint16_t efs_dmaq_id;
uint32_t efs_rss_context;
uint16_t efs_outer_vid;
uint16_t efs_inner_vid;
uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
uint16_t efs_ether_type;
uint8_t efs_ip_proto;
efx_tunnel_protocol_t efs_encap_type;
uint16_t efs_loc_port;
uint16_t efs_rem_port;
efx_oword_t efs_rem_host;
efx_oword_t efs_loc_host;
} efx_filter_spec_t;
@ -2513,8 +2557,7 @@ efx_lic_find_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
);
__out uint32_t *startp);
extern __checkReturn efx_rc_t
efx_lic_find_end(
@ -2523,8 +2566,7 @@ efx_lic_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
);
__out uint32_t *endp);
extern __checkReturn __success(return != B_FALSE) boolean_t
efx_lic_find_key(
@ -2534,15 +2576,13 @@ efx_lic_find_key(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
extern __checkReturn __success(return != B_FALSE) boolean_t
efx_lic_validate_key(
__in efx_nic_t *enp,
__in_bcount(length) caddr_t keyp,
__in uint32_t length
);
__in uint32_t length);
extern __checkReturn efx_rc_t
efx_lic_read_key(
@ -2555,8 +2595,7 @@ efx_lic_read_key(
__out_bcount_part(key_max_size, *lengthp)
caddr_t keyp,
__in size_t key_max_size,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
extern __checkReturn efx_rc_t
efx_lic_write_key(
@ -2567,8 +2606,7 @@ efx_lic_write_key(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn efx_rc_t
efx_lic_delete_key(
@ -2579,24 +2617,21 @@ efx_lic_delete_key(
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end,
__out uint32_t *deltap
);
__out uint32_t *deltap);
extern __checkReturn efx_rc_t
efx_lic_create_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
extern __checkReturn efx_rc_t
efx_lic_finish_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
#endif /* EFSYS_OPT_LICENSING */

8
sys/dev/sfxge/common/efx_bootcfg.c
View File

@ -295,7 +295,7 @@ fail1:
efx_rc_t
efx_bootcfg_read(
__in efx_nic_t *enp,
__out_bcount(size) caddr_t data,
__out_bcount(size) uint8_t *data,
__in size_t size)
{
uint8_t *payload = NULL;
@ -358,10 +358,10 @@ efx_bootcfg_read(
goto fail7;
/* Verify that the area is correctly formatted and checksummed */
rc = efx_bootcfg_verify(enp, (caddr_t)payload, sector_length,
rc = efx_bootcfg_verify(enp, payload, sector_length,
&used_bytes);
if (rc != 0 || used_bytes == 0) {
payload[0] = (uint8_t)~DHCP_END;
payload[0] = (uint8_t)(~DHCP_END & 0xff);
payload[1] = DHCP_END;
used_bytes = 2;
}
@ -435,7 +435,7 @@ fail1:
efx_rc_t
efx_bootcfg_write(
__in efx_nic_t *enp,
__in_bcount(size) caddr_t data,
__in_bcount(size) uint8_t *data,
__in size_t size)
{
uint8_t *partn_data;

8
sys/dev/sfxge/common/efx_check.h
View File

@ -226,8 +226,8 @@
/* Support for PHY LED control */
#if EFSYS_OPT_PHY_LED_CONTROL
# if !EFSYS_OPT_SIENA
# error "PHY_LED_CONTROL requires SIENA"
# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
# error "PHY_LED_CONTROL requires SIENA or HUNTINGTON or MEDFORD"
# endif
#endif /* EFSYS_OPT_PHY_LED_CONTROL */
@ -261,8 +261,8 @@
/* Support PHY statistics */
#if EFSYS_OPT_PHY_STATS
# if !EFSYS_OPT_SIENA
# error "PHY_STATS requires SIENA"
# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
# error "PHY_STATS requires SIENA or HUNTINGTON or MEDFORD"
# endif
#endif /* EFSYS_OPT_PHY_STATS */

21
sys/dev/sfxge/common/efx_ev.c
View File

@ -70,7 +70,7 @@ siena_ev_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
@ -221,21 +221,21 @@ efx_ev_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
__deref_out efx_evq_t **eepp)
{
const efx_ev_ops_t *eevop = enp->en_eevop;
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_evq_t *eep;
efx_rc_t rc;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
enp->en_nic_cfg.enc_evq_limit);
switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
@ -261,7 +261,7 @@ efx_ev_qcreate(
eep->ee_magic = EFX_EVQ_MAGIC;
eep->ee_enp = enp;
eep->ee_index = index;
eep->ee_mask = n - 1;
eep->ee_mask = ndescs - 1;
eep->ee_flags = flags;
eep->ee_esmp = esmp;
@ -276,7 +276,7 @@ efx_ev_qcreate(
enp->en_ev_qcount++;
*eepp = eep;
if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
eep)) != 0)
goto fail4;
@ -1286,7 +1286,7 @@ siena_ev_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
@ -1303,7 +1303,8 @@ siena_ev_qcreate(
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
if (!ISP2(ndescs) ||
(ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
rc = EINVAL;
goto fail1;
}
@ -1320,7 +1321,7 @@ siena_ev_qcreate(
#endif
for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
size++)
if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
if ((1 << size) == (int)(ndescs / EFX_EVQ_MINNEVS))
break;
if (id + (1 << size) >= encp->enc_buftbl_limit) {
rc = EINVAL;
@ -1421,6 +1422,8 @@ efx_ev_qstat_name(
__in efx_nic_t *enp,
__in unsigned int id)
{
_NOTE(ARGUNUSED(enp))
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(id, <, EV_NQSTATS);

44
sys/dev/sfxge/common/efx_impl.h
View File

@ -185,8 +185,9 @@ typedef struct efx_rx_ops_s {
efx_rc_t (*erxo_qflush)(efx_rxq_t *);
void (*erxo_qenable)(efx_rxq_t *);
efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
unsigned int, efx_rxq_type_t,
unsigned int, efx_rxq_type_t, uint32_t,
efsys_mem_t *, size_t, uint32_t,
unsigned int,
efx_evq_t *, efx_rxq_t *);
void (*erxo_qdestroy)(efx_rxq_t *);
} efx_rx_ops_t;
@ -300,7 +301,6 @@ typedef struct efx_port_s {
uint32_t ep_default_adv_cap_mask;
uint32_t ep_phy_cap_mask;
boolean_t ep_mac_drain;
boolean_t ep_mac_stats_pending;
#if EFSYS_OPT_BIST
efx_bist_type_t ep_current_bist;
#endif
@ -362,12 +362,7 @@ typedef struct efx_nic_ops_s {
#ifndef EFX_RXQ_LIMIT_TARGET
#define EFX_RXQ_LIMIT_TARGET 512
#endif
#ifndef EFX_TXQ_DC_SIZE
#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
#endif
#ifndef EFX_RXQ_DC_SIZE
#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
#endif
#if EFSYS_OPT_FILTER
@ -1040,8 +1035,7 @@ struct efx_txq_s {
do { \
EFX_CHECK_REG((_enp), (_reg)); \
EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
const char *, \
#_reg, \
const char *, #_reg, \
uint32_t, (_index), \
uint32_t, _reg ## _OFST, \
uint32_t, (_eop)->eo_u32[3], \
@ -1075,10 +1069,6 @@ struct efx_txq_s {
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
extern __checkReturn efx_rc_t
efx_nic_biu_test(
__in efx_nic_t *enp);
extern __checkReturn efx_rc_t
efx_mac_select(
__in efx_nic_t *enp);
@ -1147,32 +1137,6 @@ efx_vpd_hunk_set(
#endif /* EFSYS_OPT_VPD */
#if EFSYS_OPT_DIAG
extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
typedef struct efx_register_set_s {
unsigned int address;
unsigned int step;
unsigned int rows;
efx_oword_t mask;
} efx_register_set_t;
extern __checkReturn efx_rc_t
efx_nic_test_registers(
__in efx_nic_t *enp,
__in efx_register_set_t *rsp,
__in size_t count);
extern __checkReturn efx_rc_t
efx_nic_test_tables(
__in efx_nic_t *enp,
__in efx_register_set_t *rsp,
__in efx_pattern_type_t pattern,
__in size_t count);
#endif /* EFSYS_OPT_DIAG */
#if EFSYS_OPT_MCDI
extern __checkReturn efx_rc_t

198
sys/dev/sfxge/common/efx_lic.c
View File

@ -46,8 +46,7 @@ efx_lic_v1v2_find_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
);
__out uint32_t *startp);
__checkReturn efx_rc_t
efx_lic_v1v2_find_end(
@ -56,8 +55,7 @@ efx_lic_v1v2_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
);
__out uint32_t *endp);
__checkReturn __success(return != B_FALSE) boolean_t
efx_lic_v1v2_find_key(
@ -67,15 +65,13 @@ efx_lic_v1v2_find_key(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn __success(return != B_FALSE) boolean_t
efx_lic_v1v2_validate_key(
__in efx_nic_t *enp,
__in_bcount(length) caddr_t keyp,
__in uint32_t length
);
__in uint32_t length);
__checkReturn efx_rc_t
efx_lic_v1v2_read_key(
@ -88,8 +84,7 @@ efx_lic_v1v2_read_key(
__out_bcount_part(key_max_size, *lengthp)
caddr_t keyp,
__in size_t key_max_size,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn efx_rc_t
efx_lic_v1v2_write_key(
@ -100,8 +95,7 @@ efx_lic_v1v2_write_key(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn efx_rc_t
efx_lic_v1v2_delete_key(
@ -112,24 +106,21 @@ efx_lic_v1v2_delete_key(
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end,
__out uint32_t *deltap
);
__out uint32_t *deltap);
__checkReturn efx_rc_t
efx_lic_v1v2_create_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
__checkReturn efx_rc_t
efx_lic_v1v2_finish_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
#endif /* EFSYS_OPT_HUNTINGTON | EFSYS_OPT_SIENA */
@ -230,8 +221,7 @@ efx_lic_v3_find_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
);
__out uint32_t *startp);
__checkReturn efx_rc_t
efx_lic_v3_find_end(
@ -240,8 +230,7 @@ efx_lic_v3_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
);
__out uint32_t *endp);
__checkReturn __success(return != B_FALSE) boolean_t
efx_lic_v3_find_key(
@ -251,15 +240,13 @@ efx_lic_v3_find_key(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn __success(return != B_FALSE) boolean_t
efx_lic_v3_validate_key(
__in efx_nic_t *enp,
__in_bcount(length) caddr_t keyp,
__in uint32_t length
);
__in uint32_t length);
__checkReturn efx_rc_t
efx_lic_v3_read_key(
@ -272,8 +259,7 @@ efx_lic_v3_read_key(
__out_bcount_part(key_max_size, *lengthp)
caddr_t keyp,
__in size_t key_max_size,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn efx_rc_t
efx_lic_v3_write_key(
@ -284,8 +270,7 @@ efx_lic_v3_write_key(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
);
__out uint32_t *lengthp);
__checkReturn efx_rc_t
efx_lic_v3_delete_key(
@ -296,31 +281,28 @@ efx_lic_v3_delete_key(
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end,
__out uint32_t *deltap
);
__out uint32_t *deltap);
__checkReturn efx_rc_t
efx_lic_v3_create_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
__checkReturn efx_rc_t
efx_lic_v3_finish_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
);
__in size_t buffer_size);
static const efx_lic_ops_t __efx_lic_v3_ops = {
efx_mcdi_licensing_v3_update_licenses, /* elo_update_licenses */
efx_mcdi_licensing_v3_report_license, /* elo_get_key_stats */
efx_mcdi_licensing_v3_app_state, /* elo_app_state */
efx_mcdi_licensing_v3_get_id, /* elo_get_id */
efx_lic_v3_find_start, /* elo_find_start*/
efx_lic_v3_find_start, /* elo_find_start */
efx_lic_v3_find_end, /* elo_find_end */
efx_lic_v3_find_key, /* elo_find_key */
efx_lic_v3_validate_key, /* elo_validate_key */
@ -455,8 +437,8 @@ fail1:
* Length (L): 16bit - value length in bytes
* Value (V): L bytes - payload
*/
#define EFX_LICENSE_V1V2_PAYLOAD_LENGTH_MAX (256)
#define EFX_LICENSE_V1V2_HEADER_LENGTH (2 * sizeof(uint16_t))
#define EFX_LICENSE_V1V2_PAYLOAD_LENGTH_MAX (256)
#define EFX_LICENSE_V1V2_HEADER_LENGTH (2 * sizeof (uint16_t))
__checkReturn efx_rc_t
efx_lic_v1v2_find_start(
@ -464,8 +446,7 @@ efx_lic_v1v2_find_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
)
__out uint32_t *startp)
{
_NOTE(ARGUNUSED(enp, bufferp, buffer_size))
@ -480,8 +461,7 @@ efx_lic_v1v2_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
)
__out uint32_t *endp)
{
_NOTE(ARGUNUSED(enp, bufferp, buffer_size))
@ -497,8 +477,7 @@ efx_lic_v1v2_find_key(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
boolean_t found;
uint16_t tlv_type;
@ -522,7 +501,7 @@ efx_lic_v1v2_find_key(
return (found);
fail1:
EFSYS_PROBE(fail1);
EFSYS_PROBE1(fail1, boolean_t, B_FALSE);
return (B_FALSE);
}
@ -531,8 +510,7 @@ fail1:
efx_lic_v1v2_validate_key(
__in efx_nic_t *enp,
__in_bcount(length) caddr_t keyp,
__in uint32_t length
)
__in uint32_t length)
{
uint16_t tlv_type;
uint16_t tlv_length;
@ -565,7 +543,7 @@ fail3:
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE(fail1);
EFSYS_PROBE1(fail1, boolean_t, B_FALSE);
return (B_FALSE);
}
@ -582,12 +560,11 @@ efx_lic_v1v2_read_key(
__out_bcount_part(key_max_size, *lengthp)
caddr_t keyp,
__in size_t key_max_size,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
efx_rc_t rc;
_NOTE(ARGUNUSED(enp))
_NOTE(ARGUNUSED(enp, buffer_size))
EFSYS_ASSERT(length <= (EFX_LICENSE_V1V2_PAYLOAD_LENGTH_MAX +
EFX_LICENSE_V1V2_HEADER_LENGTH));
@ -616,8 +593,7 @@ efx_lic_v1v2_write_key(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
efx_rc_t rc;
@ -653,13 +629,12 @@ efx_lic_v1v2_delete_key(
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end,
__out uint32_t *deltap
)
__out uint32_t *deltap)
{
uint32_t move_start = offset + length;
uint32_t move_length = end - move_start;
_NOTE(ARGUNUSED(enp))
_NOTE(ARGUNUSED(enp, buffer_size))
EFSYS_ASSERT(end <= buffer_size);
/* Shift everything after the key down */
@ -675,10 +650,9 @@ efx_lic_v1v2_create_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
)
__in size_t buffer_size)
{
_NOTE(ARGUNUSED(enp))
_NOTE(ARGUNUSED(enp, buffer_size))
EFSYS_ASSERT(EFX_LICENSE_V1V2_HEADER_LENGTH <= buffer_size);
/* Write terminator */
@ -692,8 +666,7 @@ efx_lic_v1v2_finish_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
)
__in size_t buffer_size)
{
_NOTE(ARGUNUSED(enp, bufferp, buffer_size))
@ -1005,7 +978,8 @@ efx_mcdi_licensing_v3_app_state(
goto fail1;
}
if (req.emr_out_length_used < MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN) {
if (req.emr_out_length_used <
MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN) {
rc = EMSGSIZE;
goto fail2;
}
@ -1055,7 +1029,8 @@ efx_mcdi_licensing_v3_get_id(
req.emr_in_buf = bufferp;
req.emr_in_length = MC_CMD_LICENSING_GET_ID_V3_IN_LEN;
req.emr_out_buf = bufferp;
req.emr_out_length = MIN(buffer_size, MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX);
req.emr_out_length =
MIN(buffer_size, MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX);
(void) memset(bufferp, 0, req.emr_out_length);
}
@ -1072,12 +1047,14 @@ efx_mcdi_licensing_v3_get_id(
}
*typep = MCDI_OUT_DWORD(req, LICENSING_GET_ID_V3_OUT_LICENSE_TYPE);
*lengthp = MCDI_OUT_DWORD(req, LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH);
*lengthp =
MCDI_OUT_DWORD(req, LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH);
if (bufferp == NULL) {
/* modify length requirements to indicate to caller the extra buffering
** needed to read the complete output.
*/
/*
* Modify length requirements to indicate to caller the extra
* buffering needed to read the complete output.
*/
*lengthp += MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN;
} else {
/* Shift ID down to start of buffer */
@ -1099,8 +1076,8 @@ fail1:
}
/* V3 format uses Huntington TLV format partition. See SF-108797-SW */
#define EFX_LICENSE_V3_KEY_LENGTH_MIN (64)
#define EFX_LICENSE_V3_KEY_LENGTH_MAX (160)
#define EFX_LICENSE_V3_KEY_LENGTH_MIN (64)
#define EFX_LICENSE_V3_KEY_LENGTH_MAX (160)
__checkReturn efx_rc_t
efx_lic_v3_find_start(
@ -1108,12 +1085,12 @@ efx_lic_v3_find_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
)
__out uint32_t *startp)
{
_NOTE(ARGUNUSED(enp))
return ef10_nvram_buffer_find_item_start(bufferp, buffer_size, startp);
return (ef10_nvram_buffer_find_item_start(bufferp, buffer_size,
startp));
}
__checkReturn efx_rc_t
@ -1123,12 +1100,11 @@ efx_lic_v3_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
)
__out uint32_t *endp)
{
_NOTE(ARGUNUSED(enp))
return ef10_nvram_buffer_find_end(bufferp, buffer_size, offset, endp);
return (ef10_nvram_buffer_find_end(bufferp, buffer_size, offset, endp));
}
__checkReturn __success(return != B_FALSE) boolean_t
@ -1139,8 +1115,7 @@ efx_lic_v3_find_key(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
_NOTE(ARGUNUSED(enp))
@ -1152,8 +1127,7 @@ efx_lic_v3_find_key(
efx_lic_v3_validate_key(
__in efx_nic_t *enp,
__in_bcount(length) caddr_t keyp,
__in uint32_t length
)
__in uint32_t length)
{
/* Check key is a valid V3 key */
uint8_t key_type;
@ -1187,7 +1161,7 @@ fail3:
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE(fail1);
EFSYS_PROBE1(fail1, boolean_t, B_FALSE);
return (B_FALSE);
}
@ -1203,8 +1177,7 @@ efx_lic_v3_read_key(
__out_bcount_part(key_max_size, *lengthp)
caddr_t keyp,
__in size_t key_max_size,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
_NOTE(ARGUNUSED(enp))
@ -1221,8 +1194,7 @@ efx_lic_v3_write_key(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
_NOTE(ARGUNUSED(enp))
EFSYS_ASSERT(length <= EFX_LICENSE_V3_KEY_LENGTH_MAX);
@ -1240,8 +1212,7 @@ efx_lic_v3_delete_key(
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end,
__out uint32_t *deltap
)
__out uint32_t *deltap)
{
efx_rc_t rc;
@ -1267,8 +1238,7 @@ efx_lic_v3_create_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
)
__in size_t buffer_size)
{
efx_rc_t rc;
@ -1293,8 +1263,7 @@ efx_lic_v3_finish_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
)
__in size_t buffer_size)
{
efx_rc_t rc;
@ -1386,7 +1355,7 @@ efx_lic_check_support(
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_LIC);
return enp->en_licensing_supported;
return (enp->en_licensing_supported);
}
void
@ -1477,8 +1446,7 @@ efx_lic_get_id(
__in size_t buffer_size,
__out uint32_t *typep,
__out size_t *lengthp,
__out_opt uint8_t *bufferp
)
__out_opt uint8_t *bufferp)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1501,7 +1469,10 @@ fail1:
return (rc);
}
/* Buffer management API - abstracts varying TLV format used for License partition */
/*
* Buffer management API - abstracts varying TLV format used for License
* partition.
*/
__checkReturn efx_rc_t
efx_lic_find_start(
@ -1509,8 +1480,7 @@ efx_lic_find_start(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
__out uint32_t *startp
)
__out uint32_t *startp)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1536,8 +1506,7 @@ efx_lic_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *endp
)
__out uint32_t *endp)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1545,7 +1514,8 @@ efx_lic_find_end(
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_LIC);
if ((rc = elop->elo_find_end(enp, bufferp, buffer_size, offset, endp)) != 0)
rc = elop->elo_find_end(enp, bufferp, buffer_size, offset, endp);
if (rc != 0)
goto fail1;
return (0);
@ -1564,8 +1534,7 @@ efx_lic_find_key(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
const efx_lic_ops_t *elop = enp->en_elop;
@ -1581,15 +1550,15 @@ efx_lic_find_key(
}
/* Validate that the buffer contains a single key in a recognised format.
** An empty or terminator buffer is not accepted as a valid key.
*/
/*
* Validate that the buffer contains a single key in a recognised format.
* An empty or terminator buffer is not accepted as a valid key.
*/
__checkReturn __success(return != B_FALSE) boolean_t
efx_lic_validate_key(
__in efx_nic_t *enp,
__in_bcount(length) caddr_t keyp,
__in uint32_t length
)
__in uint32_t length)
{
const efx_lic_ops_t *elop = enp->en_elop;
boolean_t rc;
@ -1619,8 +1588,7 @@ efx_lic_read_key(
__out_bcount_part(key_max_size, *lengthp)
caddr_t keyp,
__in size_t key_max_size,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1649,8 +1617,7 @@ efx_lic_write_key(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
__out uint32_t *lengthp
)
__out uint32_t *lengthp)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1679,8 +1646,7 @@ efx_lic_delete_key(
__in uint32_t offset,
__in uint32_t length,
__in uint32_t end,
__out uint32_t *deltap
)
__out uint32_t *deltap)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1705,8 +1671,7 @@ efx_lic_create_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
)
__in size_t buffer_size)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;
@ -1731,8 +1696,7 @@ efx_lic_finish_partition(
__in efx_nic_t *enp,
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size
)
__in size_t buffer_size)
{
const efx_lic_ops_t *elop = enp->en_elop;
efx_rc_t rc;

9
sys/dev/sfxge/common/efx_mac.c
View File

@ -756,16 +756,9 @@ efx_mac_stats_upload(
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
EFSYS_ASSERT(emop != NULL);
/*
* Don't assert !ep_mac_stats_pending, because the client might
* have failed to finalise statistics when previously stopping
* the port.
*/
if ((rc = emop->emo_stats_upload(enp, esmp)) != 0)
goto fail1;
epp->ep_mac_stats_pending = B_TRUE;
return (0);
fail1:
@ -825,8 +818,6 @@ efx_mac_stats_update(
EFSYS_ASSERT(emop != NULL);
rc = emop->emo_stats_update(enp, esmp, essp, generationp);
if (rc == 0)
epp->ep_mac_stats_pending = B_FALSE;
return (rc);
}

2
sys/dev/sfxge/common/efx_mcdi.c
View File

@ -814,6 +814,8 @@ efx_mcdi_get_proxy_handle(
{
efx_rc_t rc;
_NOTE(ARGUNUSED(enp))
/*
* Return proxy handle from MCDI request that returned with error
* MC_MCD_ERR_PROXY_PENDING. This handle is used to wait for a matching

2
sys/dev/sfxge/common/efx_mcdi.h
View File

@ -55,7 +55,7 @@ struct efx_mcdi_req_s {
unsigned int emr_cmd;
uint8_t *emr_in_buf;
size_t emr_in_length;
/* Outputs: retcode, buffer, length, and length used*/
/* Outputs: retcode, buffer, length, and length used */
efx_rc_t emr_rc;
uint8_t *emr_out_buf;
size_t emr_out_length;

4
sys/dev/sfxge/common/efx_mon.c
View File

@ -128,7 +128,7 @@ fail1:
#if EFSYS_OPT_NAMES
/* START MKCONFIG GENERATED MonitorStatNamesBlock 5daa2a5725ba734b */
/* START MKCONFIG GENERATED MonitorStatNamesBlock d92af1538001301f */
static const char * const __mon_stat_name[] = {
"value_2_5v",
"value_vccp1",
@ -207,6 +207,8 @@ static const char * const __mon_stat_name[] = {
"controller_tdiode_temp",
"board_front_temp",
"board_back_temp",
"i1v8",
"i2v5",
};
/* END MKCONFIG GENERATED MonitorStatNamesBlock */

214
sys/dev/sfxge/common/efx_nic.c
View File

@ -107,78 +107,6 @@ efx_family(
return (ENOTSUP);
}
#define EFX_BIU_MAGIC0 0x01234567
#define EFX_BIU_MAGIC1 0xfedcba98
__checkReturn efx_rc_t
efx_nic_biu_test(
__in efx_nic_t *enp)
{
efx_oword_t oword;
efx_rc_t rc;
/*
* Write magic values to scratch registers 0 and 1, then
* verify that the values were written correctly. Interleave
* the accesses to ensure that the BIU is not just reading
* back the cached value that was last written.
*/
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
rc = EIO;
goto fail1;
}
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
rc = EIO;
goto fail2;
}
/*
* Perform the same test, with the values swapped. This
* ensures that subsequent tests don't start with the correct
* values already written into the scratch registers.
*/
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
rc = EIO;
goto fail3;
}
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
rc = EIO;
goto fail4;
}
return (0);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_PROBE(fail3);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
#if EFSYS_OPT_SIENA
static const efx_nic_ops_t __efx_nic_siena_ops = {
@ -642,9 +570,9 @@ efx_nic_get_fw_version(
goto fail2;
rc = efx_mcdi_get_capabilities(enp, NULL,
&enfip->enfi_rx_dpcpu_fw_id,
&enfip->enfi_tx_dpcpu_fw_id,
NULL, NULL);
&enfip->enfi_rx_dpcpu_fw_id,
&enfip->enfi_tx_dpcpu_fw_id,
NULL, NULL);
if (rc == 0) {
enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
} else if (rc == ENOTSUP) {
@ -655,7 +583,8 @@ efx_nic_get_fw_version(
goto fail3;
}
memcpy(enfip->enfi_mc_fw_version, mc_fw_version, sizeof(mc_fw_version));
memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
sizeof (mc_fw_version));
return (0);
@ -687,139 +616,6 @@ efx_nic_register_test(
return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
__checkReturn efx_rc_t
efx_nic_test_registers(
__in efx_nic_t *enp,
__in efx_register_set_t *rsp,
__in size_t count)
{
unsigned int bit;
efx_oword_t original;
efx_oword_t reg;
efx_oword_t buf;
efx_rc_t rc;
while (count > 0) {
/* This function is only suitable for registers */
EFSYS_ASSERT(rsp->rows == 1);
/* bit sweep on and off */
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
B_TRUE);
for (bit = 0; bit < 128; bit++) {
/* Is this bit in the mask? */
if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
continue;
/* Test this bit can be set in isolation */
reg = original;
EFX_AND_OWORD(reg, rsp->mask);
EFX_SET_OWORD_BIT(reg, bit);
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &reg,
B_TRUE);
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
B_TRUE);
EFX_AND_OWORD(buf, rsp->mask);
if (memcmp(&reg, &buf, sizeof (reg))) {
rc = EIO;
goto fail1;
}
/* Test this bit can be cleared in isolation */
EFX_OR_OWORD(reg, rsp->mask);
EFX_CLEAR_OWORD_BIT(reg, bit);
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &reg,
B_TRUE);
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
B_TRUE);
EFX_AND_OWORD(buf, rsp->mask);
if (memcmp(&reg, &buf, sizeof (reg))) {
rc = EIO;
goto fail2;
}
}
/* Restore the old value */
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
B_TRUE);
--count;
++rsp;
}
return (0);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
/* Restore the old value */
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
return (rc);
}
__checkReturn efx_rc_t
efx_nic_test_tables(
__in efx_nic_t *enp,
__in efx_register_set_t *rsp,
__in efx_pattern_type_t pattern,
__in size_t count)
{
efx_sram_pattern_fn_t func;
unsigned int index;
unsigned int address;
efx_oword_t reg;
efx_oword_t buf;
efx_rc_t rc;
EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
func = __efx_sram_pattern_fns[pattern];
while (count > 0) {
/* Write */
address = rsp->address;
for (index = 0; index < rsp->rows; ++index) {
func(2 * index + 0, B_FALSE, &reg.eo_qword[0]);
func(2 * index + 1, B_FALSE, &reg.eo_qword[1]);
EFX_AND_OWORD(reg, rsp->mask);
EFSYS_BAR_WRITEO(enp->en_esbp, address, &reg, B_TRUE);
address += rsp->step;
}
/* Read */
address = rsp->address;
for (index = 0; index < rsp->rows; ++index) {
func(2 * index + 0, B_FALSE, &reg.eo_qword[0]);
func(2 * index + 1, B_FALSE, &reg.eo_qword[1]);
EFX_AND_OWORD(reg, rsp->mask);
EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
if (memcmp(&reg, &buf, sizeof (reg))) {
rc = EIO;
goto fail1;
}
address += rsp->step;
}
++rsp;
--count;
}
return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);

1
sys/dev/sfxge/common/efx_port.c
View File

@ -114,7 +114,6 @@ efx_port_poll(
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
EFSYS_ASSERT(emop != NULL);
EFSYS_ASSERT(!epp->ep_mac_stats_pending);
if (link_modep == NULL)
link_modep = &ignore_link_mode;

139
sys/dev/sfxge/common/efx_rx.c
View File

@ -91,14 +91,14 @@ siena_rx_prefix_pktlen(
__in uint8_t *buffer,
__out uint16_t *lengthp);
static void
static void
siena_rx_qpost(
__in efx_rxq_t *erp,
__in_ecount(n) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int n,
__in unsigned int completed,
__in unsigned int added);
__in efx_rxq_t *erp,
__in_ecount(ndescs) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int ndescs,
__in unsigned int completed,
__in unsigned int added);
static void
siena_rx_qpush(
@ -136,9 +136,11 @@ siena_rx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
__in uint32_t type_data,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__in efx_rxq_t *erp);
@ -517,21 +519,21 @@ fail1:
}
#endif /* EFSYS_OPT_RX_SCALE */
void
void
efx_rx_qpost(
__in efx_rxq_t *erp,
__in_ecount(n) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int n,
__in unsigned int completed,
__in unsigned int added)
__in efx_rxq_t *erp,
__in_ecount(ndescs) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int ndescs,
__in unsigned int completed,
__in unsigned int added)
{
efx_nic_t *enp = erp->er_enp;
const efx_rx_ops_t *erxop = enp->en_erxop;
EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
erxop->erxo_qpost(erp, addrp, size, n, completed, added);
erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
}
#if EFSYS_OPT_RX_PACKED_STREAM
@ -615,15 +617,17 @@ efx_rx_qenable(
erxop->erxo_qenable(erp);
}
__checkReturn efx_rc_t
efx_rx_qcreate(
static __checkReturn efx_rc_t
efx_rx_qcreate_internal(
__in efx_nic_t *enp,
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
__in uint32_t type_data,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__deref_out efx_rxq_t **erpp)
{
@ -645,11 +649,11 @@ efx_rx_qcreate(
erp->er_magic = EFX_RXQ_MAGIC;
erp->er_enp = enp;
erp->er_index = index;
erp->er_mask = n - 1;
erp->er_mask = ndescs - 1;
erp->er_esmp = esmp;
if ((rc = erxop->erxo_qcreate(enp, index, label, type, esmp, n, id,
eep, erp)) != 0)
if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
ndescs, id, flags, eep, erp)) != 0)
goto fail2;
enp->en_rx_qcount++;
@ -667,6 +671,43 @@ fail1:
return (rc);
}
__checkReturn efx_rc_t
efx_rx_qcreate(
__in efx_nic_t *enp,
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
__in efsys_mem_t *esmp,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__deref_out efx_rxq_t **erpp)
{
return efx_rx_qcreate_internal(enp, index, label, type, 0, esmp, ndescs,
id, flags, eep, erpp);
}
#if EFSYS_OPT_RX_PACKED_STREAM
__checkReturn efx_rc_t
efx_rx_qcreate_packed_stream(
__in efx_nic_t *enp,
__in unsigned int index,
__in unsigned int label,
__in uint32_t ps_buf_size,
__in efsys_mem_t *esmp,
__in size_t ndescs,
__in efx_evq_t *eep,
__deref_out efx_rxq_t **erpp)
{
return efx_rx_qcreate_internal(enp, index, label,
EFX_RXQ_TYPE_PACKED_STREAM, ps_buf_size, esmp, ndescs,
0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
}
#endif
void
efx_rx_qdestroy(
__in efx_rxq_t *erp)
@ -1168,14 +1209,14 @@ siena_rx_prefix_pktlen(
}
static void
static void
siena_rx_qpost(
__in efx_rxq_t *erp,
__in_ecount(n) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int n,
__in unsigned int completed,
__in unsigned int added)
__in efx_rxq_t *erp,
__in_ecount(ndescs) efsys_dma_addr_t *addrp,
__in size_t size,
__in unsigned int ndescs,
__in unsigned int completed,
__in unsigned int added)
{
efx_qword_t qword;
unsigned int i;
@ -1183,11 +1224,11 @@ siena_rx_qpost(
unsigned int id;
/* The client driver must not overfill the queue */
EFSYS_ASSERT3U(added - completed + n, <=,
EFSYS_ASSERT3U(added - completed + ndescs, <=,
EFX_RXQ_LIMIT(erp->er_mask + 1));
id = added & (erp->er_mask);
for (i = 0; i < n; i++) {
for (i = 0; i < ndescs; i++) {
EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
unsigned int, id, efsys_dma_addr_t, addrp[i],
size_t, size);
@ -1308,19 +1349,22 @@ siena_rx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
__in uint32_t type_data,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in unsigned int flags,
__in efx_evq_t *eep,
__in efx_rxq_t *erp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_oword_t oword;
uint32_t size;
boolean_t jumbo;
boolean_t jumbo = B_FALSE;
efx_rc_t rc;
_NOTE(ARGUNUSED(esmp))
_NOTE(ARGUNUSED(type_data))
EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
(1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
@ -1330,7 +1374,8 @@ siena_rx_qcreate(
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
if (!ISP2(n) || (n < EFX_RXQ_MINNDESCS) || (n > EFX_RXQ_MAXNDESCS)) {
if (!ISP2(ndescs) ||
(ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
rc = EINVAL;
goto fail1;
}
@ -1340,7 +1385,7 @@ siena_rx_qcreate(
}
for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
size++)
if ((1 << size) == (int)(n / EFX_RXQ_MINNDESCS))
if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
break;
if (id + (1 << size) >= encp->enc_buftbl_limit) {
rc = EINVAL;
@ -1349,24 +1394,22 @@ siena_rx_qcreate(
switch (type) {
case EFX_RXQ_TYPE_DEFAULT:
jumbo = B_FALSE;
break;
#if EFSYS_OPT_RX_SCATTER
case EFX_RXQ_TYPE_SCATTER:
if (enp->en_family < EFX_FAMILY_SIENA) {
rc = EINVAL;
goto fail4;
}
jumbo = B_TRUE;
break;
#endif /* EFSYS_OPT_RX_SCATTER */
default:
rc = EINVAL;
goto fail4;
}
if (flags & EFX_RXQ_FLAG_SCATTER) {
#if EFSYS_OPT_RX_SCATTER
jumbo = B_TRUE;
#else
rc = EINVAL;
goto fail5;
#endif /* EFSYS_OPT_RX_SCATTER */
}
/* Set up the new descriptor queue */
EFX_POPULATE_OWORD_7(oword,
FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
@ -1382,6 +1425,10 @@ siena_rx_qcreate(
return (0);
#if !EFSYS_OPT_RX_SCATTER
fail5:
EFSYS_PROBE(fail5);
#endif
fail4:
EFSYS_PROBE(fail4);
fail3:

106
sys/dev/sfxge/common/efx_tx.c
View File

@ -62,7 +62,7 @@ siena_tx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint16_t flags,
__in efx_evq_t *eep,
@ -73,13 +73,13 @@ static void
siena_tx_qdestroy(
__in efx_txq_t *etp);
static __checkReturn efx_rc_t
static __checkReturn efx_rc_t
siena_tx_qpost(
__in efx_txq_t *etp,
__in_ecount(n) efx_buffer_t *eb,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp);
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_buffer_t *eb,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp);
static void
siena_tx_qpush(
@ -100,13 +100,13 @@ static void
siena_tx_qenable(
__in efx_txq_t *etp);
__checkReturn efx_rc_t
__checkReturn efx_rc_t
siena_tx_qdesc_post(
__in efx_txq_t *etp,
__in_ecount(n) efx_desc_t *ed,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp);
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_desc_t *ed,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp);
void
siena_tx_qdesc_dma_create(
@ -295,7 +295,7 @@ efx_tx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint16_t flags,
__in efx_evq_t *eep,
@ -303,14 +303,14 @@ efx_tx_qcreate(
__out unsigned int *addedp)
{
const efx_tx_ops_t *etxop = enp->en_etxop;
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
efx_txq_t *etp;
efx_rc_t rc;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit);
EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <,
enp->en_nic_cfg.enc_txq_limit);
/* Allocate an TXQ object */
EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp);
@ -323,14 +323,14 @@ efx_tx_qcreate(
etp->et_magic = EFX_TXQ_MAGIC;
etp->et_enp = enp;
etp->et_index = index;
etp->et_mask = n - 1;
etp->et_mask = ndescs - 1;
etp->et_esmp = esmp;
/* Initial descriptor index may be modified by etxo_qcreate */
*addedp = 0;
if ((rc = etxop->etxo_qcreate(enp, index, label, esmp,
n, id, flags, eep, etp, addedp)) != 0)
ndescs, id, flags, eep, etp, addedp)) != 0)
goto fail2;
enp->en_tx_qcount++;
@ -364,13 +364,13 @@ efx_tx_qdestroy(
EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);
}
__checkReturn efx_rc_t
__checkReturn efx_rc_t
efx_tx_qpost(
__in efx_txq_t *etp,
__in_ecount(n) efx_buffer_t *eb,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp)
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_buffer_t *eb,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp)
{
efx_nic_t *enp = etp->et_enp;
const efx_tx_ops_t *etxop = enp->en_etxop;
@ -378,8 +378,7 @@ efx_tx_qpost(
EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
if ((rc = etxop->etxo_qpost(etp, eb,
n, completed, addedp)) != 0)
if ((rc = etxop->etxo_qpost(etp, eb, ndescs, completed, addedp)) != 0)
goto fail1;
return (0);
@ -555,13 +554,13 @@ fail1:
return (rc);
}
__checkReturn efx_rc_t
__checkReturn efx_rc_t
efx_tx_qdesc_post(
__in efx_txq_t *etp,
__in_ecount(n) efx_desc_t *ed,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp)
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_desc_t *ed,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp)
{
efx_nic_t *enp = etp->et_enp;
const efx_tx_ops_t *etxop = enp->en_etxop;
@ -570,7 +569,7 @@ efx_tx_qdesc_post(
EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
if ((rc = etxop->etxo_qdesc_post(etp, ed,
n, completed, addedp)) != 0)
ndescs, completed, addedp)) != 0)
goto fail1;
return (0);
@ -729,22 +728,22 @@ siena_tx_init(
_NOTE(CONSTANTCONDITION) \
} while (B_FALSE)
static __checkReturn efx_rc_t
static __checkReturn efx_rc_t
siena_tx_qpost(
__in efx_txq_t *etp,
__in_ecount(n) efx_buffer_t *eb,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp)
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_buffer_t *eb,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp)
{
unsigned int added = *addedp;
unsigned int i;
int rc = ENOSPC;
if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1))
if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1))
goto fail1;
for (i = 0; i < n; i++) {
for (i = 0; i < ndescs; i++) {
efx_buffer_t *ebp = &eb[i];
efsys_dma_addr_t start = ebp->eb_addr;
size_t size = ebp->eb_size;
@ -895,7 +894,7 @@ siena_tx_qcreate(
__in unsigned int index,
__in unsigned int label,
__in efsys_mem_t *esmp,
__in size_t n,
__in size_t ndescs,
__in uint32_t id,
__in uint16_t flags,
__in efx_evq_t *eep,
@ -917,7 +916,8 @@ siena_tx_qcreate(
EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs));
EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
if (!ISP2(n) || (n < EFX_TXQ_MINNDESCS) || (n > EFX_EVQ_MAXNEVS)) {
if (!ISP2(ndescs) ||
(ndescs < EFX_TXQ_MINNDESCS) || (ndescs > EFX_EVQ_MAXNEVS)) {
rc = EINVAL;
goto fail1;
}
@ -928,7 +928,7 @@ siena_tx_qcreate(
for (size = 0;
(1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS);
size++)
if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS))
if ((1 << size) == (int)(ndescs / EFX_TXQ_MINNDESCS))
break;
if (id + (1 << size) >= encp->enc_buftbl_limit) {
rc = EINVAL;
@ -975,24 +975,24 @@ fail1:
return (rc);
}
__checkReturn efx_rc_t
__checkReturn efx_rc_t
siena_tx_qdesc_post(
__in efx_txq_t *etp,
__in_ecount(n) efx_desc_t *ed,
__in unsigned int n,
__in unsigned int completed,
__inout unsigned int *addedp)
__in efx_txq_t *etp,
__in_ecount(ndescs) efx_desc_t *ed,
__in unsigned int ndescs,
__in unsigned int completed,
__inout unsigned int *addedp)
{
unsigned int added = *addedp;
unsigned int i;
efx_rc_t rc;
if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
rc = ENOSPC;
goto fail1;
}
for (i = 0; i < n; i++) {
for (i = 0; i < ndescs; i++) {
efx_desc_t *edp = &ed[i];
unsigned int id;
size_t offset;
@ -1004,7 +1004,7 @@ siena_tx_qdesc_post(
}
EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
unsigned int, added, unsigned int, n);
unsigned int, added, unsigned int, ndescs);
EFX_TX_QSTAT_INCR(etp, TX_POST);

3
sys/dev/sfxge/common/efx_types.h
View File

@ -120,7 +120,8 @@ extern "C" {
#define EFX_DWORD_3_LBN 96
#define EFX_DWORD_3_WIDTH 32
/* There are intentionally no EFX_QWORD_0 or EFX_QWORD_1 field definitions
/*
* There are intentionally no EFX_QWORD_0 or EFX_QWORD_1 field definitions
* here as the implementaion of EFX_QWORD_FIELD and EFX_OWORD_FIELD do not
* support field widths larger than 32 bits.
*/

2
sys/dev/sfxge/common/efx_vpd.c
View File

@ -933,7 +933,7 @@ efx_vpd_hunk_set(
}
/* Modify tag length (large resource type) */
taglen += (dest - source);
taglen += (uint16_t)(dest - source);
EFX_POPULATE_WORD_1(word, EFX_WORD_0, taglen);
data[offset - 2] = EFX_WORD_FIELD(word, EFX_BYTE_0);
data[offset - 1] = EFX_WORD_FIELD(word, EFX_BYTE_1);

26
sys/dev/sfxge/common/mcdi_mon.c
View File

@ -160,6 +160,8 @@ static const struct mcdi_sensor_map_s {
STAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */
STAT(Px, BOARD_FRONT_TEMP), /* 0x4f BOARD_FRONT_TEMP */
STAT(Px, BOARD_BACK_TEMP), /* 0x50 BOARD_BACK_TEMP */
STAT(Px, I1V8), /* 0x51 IN_I1V8 */
STAT(Px, I2V5), /* 0x52 IN_I2V5 */
};
#define MCDI_STATIC_SENSOR_ASSERT(_field) \
@ -265,7 +267,6 @@ mcdi_mon_ev(
__out efx_mon_stat_value_t *valuep)
{
efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
uint16_t port_mask;
uint16_t sensor;
uint16_t state;
@ -281,11 +282,13 @@ mcdi_mon_ev(
value = (uint16_t)MCDI_EV_FIELD(eqp, SENSOREVT_VALUE);
/* Hardware must support this MCDI sensor */
EFSYS_ASSERT3U(sensor, <, (8 * encp->enc_mcdi_sensor_mask_size));
EFSYS_ASSERT3U(sensor, <,
(8 * enp->en_nic_cfg.enc_mcdi_sensor_mask_size));
EFSYS_ASSERT((sensor % MCDI_MON_PAGE_SIZE) != MC_CMD_SENSOR_PAGE0_NEXT);
EFSYS_ASSERT(encp->enc_mcdi_sensor_maskp != NULL);
EFSYS_ASSERT((encp->enc_mcdi_sensor_maskp[sensor / MCDI_MON_PAGE_SIZE] &
(1U << (sensor % MCDI_MON_PAGE_SIZE))) != 0);
EFSYS_ASSERT(enp->en_nic_cfg.enc_mcdi_sensor_maskp != NULL);
EFSYS_ASSERT(
(enp->en_nic_cfg.enc_mcdi_sensor_maskp[sensor/MCDI_MON_PAGE_SIZE] &
(1U << (sensor % MCDI_MON_PAGE_SIZE))) != 0);
/* But we don't have to understand it */
if (sensor >= EFX_ARRAY_SIZE(mcdi_sensor_map)) {
@ -396,6 +399,11 @@ efx_mcdi_sensor_info(
EFSYS_ASSERT(sensor_maskp != NULL);
if (npages < 1) {
rc = EINVAL;
goto fail1;
}
for (page = 0; page < npages; page++) {
uint32_t mask;
@ -412,7 +420,7 @@ efx_mcdi_sensor_info(
if (req.emr_rc != 0) {
rc = req.emr_rc;
goto fail1;
goto fail2;
}
mask = MCDI_OUT_DWORD(req, SENSOR_INFO_OUT_MASK);
@ -420,18 +428,20 @@ efx_mcdi_sensor_info(
if ((page != (npages - 1)) &&
((mask & (1U << MC_CMD_SENSOR_PAGE0_NEXT)) == 0)) {
rc = EINVAL;
goto fail2;
goto fail3;
}
sensor_maskp[page] = mask;
}
if (sensor_maskp[npages - 1] & (1U << MC_CMD_SENSOR_PAGE0_NEXT)) {
rc = EINVAL;
goto fail3;
goto fail4;
}
return (0);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_PROBE(fail3);
fail2:

8
sys/dev/sfxge/common/medford_impl.h
View File

@ -37,14 +37,6 @@
extern "C" {
#endif
/* Alignment requirement for value written to RX WPTR:
* the WPTR must be aligned to an 8 descriptor boundary
*
* FIXME: Is this the same on Medford as Huntington?
*/
#define MEDFORD_RX_WPTR_ALIGN 8
#ifndef ER_EZ_TX_PIOBUF_SIZE
#define ER_EZ_TX_PIOBUF_SIZE 4096

3
sys/dev/sfxge/common/medford_nic.c
View File

@ -181,7 +181,8 @@ medford_board_cfg(
if (EFX_PCI_FUNCTION_IS_PF(encp)) {
rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
#if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
/* Disable static config checking for Medford NICs, ONLY
/*
* Disable static config checking for Medford NICs, ONLY
* for manufacturing test and setup at the factory, to
* allow the static config to be installed.
*/

18
sys/dev/sfxge/common/siena_impl.h
View File

@ -44,8 +44,17 @@
extern "C" {
#endif
#ifndef EFX_TXQ_DC_SIZE
#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
#endif
#ifndef EFX_RXQ_DC_SIZE
#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
#endif
#define EFX_TXQ_DC_NDESCS(_dcsize) (8 << (_dcsize))
#define SIENA_NVRAM_CHUNK 0x80
extern __checkReturn efx_rc_t
siena_nic_probe(
__in efx_nic_t *enp);
@ -60,6 +69,15 @@ siena_nic_init(
#if EFSYS_OPT_DIAG
extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
typedef struct siena_register_set_s {
unsigned int address;
unsigned int step;
unsigned int rows;
efx_oword_t mask;
} siena_register_set_t;
extern __checkReturn efx_rc_t
siena_nic_register_test(
__in efx_nic_t *enp);

223
sys/dev/sfxge/common/siena_nic.c
View File

@ -195,7 +195,9 @@ static __checkReturn efx_rc_t
siena_phy_cfg(
__in efx_nic_t *enp)
{
#if EFSYS_OPT_PHY_STATS
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
#endif /* EFSYS_OPT_PHY_STATS */
efx_rc_t rc;
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
@ -216,6 +218,77 @@ fail1:
return (rc);
}
#define SIENA_BIU_MAGIC0 0x01234567
#define SIENA_BIU_MAGIC1 0xfedcba98
static __checkReturn efx_rc_t
siena_nic_biu_test(
__in efx_nic_t *enp)
{
efx_oword_t oword;
efx_rc_t rc;
/*
* Write magic values to scratch registers 0 and 1, then
* verify that the values were written correctly. Interleave
* the accesses to ensure that the BIU is not just reading
* back the cached value that was last written.
*/
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
rc = EIO;
goto fail1;
}
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
rc = EIO;
goto fail2;
}
/*
* Perform the same test, with the values swapped. This
* ensures that subsequent tests don't start with the correct
* values already written into the scratch registers.
*/
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
rc = EIO;
goto fail3;
}
EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
rc = EIO;
goto fail4;
}
return (0);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_PROBE(fail3);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
__checkReturn efx_rc_t
siena_nic_probe(
__in efx_nic_t *enp)
@ -230,7 +303,7 @@ siena_nic_probe(
EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
/* Test BIU */
if ((rc = efx_nic_biu_test(enp)) != 0)
if ((rc = siena_nic_biu_test(enp)) != 0)
goto fail1;
/* Clear the region register */
@ -460,7 +533,7 @@ siena_nic_unprobe(
#if EFSYS_OPT_DIAG
static efx_register_set_t __siena_registers[] = {
static siena_register_set_t __siena_registers[] = {
{ FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
{ FR_CZ_USR_EV_CFG_OFST, 0, 1 },
{ FR_AZ_RX_CFG_REG_OFST, 0, 1 },
@ -492,7 +565,7 @@ static const uint32_t __siena_register_masks[] = {
0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
};
static efx_register_set_t __siena_tables[] = {
static siena_register_set_t __siena_tables[] = {
{ FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
FR_AZ_RX_FILTER_TBL0_ROWS },
{ FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
@ -518,11 +591,145 @@ static const uint32_t __siena_table_masks[] = {
0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
};
__checkReturn efx_rc_t
siena_nic_test_registers(
__in efx_nic_t *enp,
__in siena_register_set_t *rsp,
__in size_t count)
{
unsigned int bit;
efx_oword_t original;
efx_oword_t reg;
efx_oword_t buf;
efx_rc_t rc;
while (count > 0) {
/* This function is only suitable for registers */
EFSYS_ASSERT(rsp->rows == 1);
/* bit sweep on and off */
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
B_TRUE);
for (bit = 0; bit < 128; bit++) {
/* Is this bit in the mask? */
if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
continue;
/* Test this bit can be set in isolation */
reg = original;
EFX_AND_OWORD(reg, rsp->mask);
EFX_SET_OWORD_BIT(reg, bit);
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &reg,
B_TRUE);
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
B_TRUE);
EFX_AND_OWORD(buf, rsp->mask);
if (memcmp(&reg, &buf, sizeof (reg))) {
rc = EIO;
goto fail1;
}
/* Test this bit can be cleared in isolation */
EFX_OR_OWORD(reg, rsp->mask);
EFX_CLEAR_OWORD_BIT(reg, bit);
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &reg,
B_TRUE);
EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
B_TRUE);
EFX_AND_OWORD(buf, rsp->mask);
if (memcmp(&reg, &buf, sizeof (reg))) {
rc = EIO;
goto fail2;
}
}
/* Restore the old value */
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
B_TRUE);
--count;
++rsp;
}
return (0);
fail2:
EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
/* Restore the old value */
EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
return (rc);
}
__checkReturn efx_rc_t
siena_nic_test_tables(
__in efx_nic_t *enp,
__in siena_register_set_t *rsp,
__in efx_pattern_type_t pattern,
__in size_t count)
{
efx_sram_pattern_fn_t func;
unsigned int index;
unsigned int address;
efx_oword_t reg;
efx_oword_t buf;
efx_rc_t rc;
EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
func = __efx_sram_pattern_fns[pattern];
while (count > 0) {
/* Write */
address = rsp->address;
for (index = 0; index < rsp->rows; ++index) {
func(2 * index + 0, B_FALSE, &reg.eo_qword[0]);
func(2 * index + 1, B_FALSE, &reg.eo_qword[1]);
EFX_AND_OWORD(reg, rsp->mask);
EFSYS_BAR_WRITEO(enp->en_esbp, address, &reg, B_TRUE);
address += rsp->step;
}
/* Read */
address = rsp->address;
for (index = 0; index < rsp->rows; ++index) {
func(2 * index + 0, B_FALSE, &reg.eo_qword[0]);
func(2 * index + 1, B_FALSE, &reg.eo_qword[1]);
EFX_AND_OWORD(reg, rsp->mask);
EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
if (memcmp(&reg, &buf, sizeof (reg))) {
rc = EIO;
goto fail1;
}
address += rsp->step;
}
++rsp;
--count;
}
return (0);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
return (rc);
}
__checkReturn efx_rc_t
siena_nic_register_test(
__in efx_nic_t *enp)
{
efx_register_set_t *rsp;
siena_register_set_t *rsp;
const uint32_t *dwordp;
unsigned int nitems;
unsigned int count;
@ -556,21 +763,21 @@ siena_nic_register_test(
rsp->mask.eo_u32[3] = *dwordp++;
}
if ((rc = efx_nic_test_registers(enp, __siena_registers,
if ((rc = siena_nic_test_registers(enp, __siena_registers,
EFX_ARRAY_SIZE(__siena_registers))) != 0)
goto fail1;
if ((rc = efx_nic_test_tables(enp, __siena_tables,
if ((rc = siena_nic_test_tables(enp, __siena_tables,
EFX_PATTERN_BYTE_ALTERNATE,
EFX_ARRAY_SIZE(__siena_tables))) != 0)
goto fail2;
if ((rc = efx_nic_test_tables(enp, __siena_tables,
if ((rc = siena_nic_test_tables(enp, __siena_tables,
EFX_PATTERN_BYTE_CHANGING,
EFX_ARRAY_SIZE(__siena_tables))) != 0)
goto fail3;
if ((rc = efx_nic_test_tables(enp, __siena_tables,
if ((rc = siena_nic_test_tables(enp, __siena_tables,
EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
goto fail4;

2
sys/dev/sfxge/common/siena_phy.c
View File

@ -278,7 +278,9 @@ siena_phy_reconfigure(
MAX(MC_CMD_SET_LINK_IN_LEN,
MC_CMD_SET_LINK_OUT_LEN))];
uint32_t cap_mask;
#if EFSYS_OPT_PHY_LED_CONTROL
unsigned int led_mode;
#endif
unsigned int speed;
efx_rc_t rc;

4
sys/dev/sfxge/sfxge_rx.c
View File

@ -1037,8 +1037,8 @@ sfxge_rx_qstart(struct sfxge_softc *sc, unsigned int index)
/* Create the common code receive queue. */
if ((rc = efx_rx_qcreate(sc->enp, index, 0, EFX_RXQ_TYPE_DEFAULT,
esmp, sc->rxq_entries, rxq->buf_base_id, evq->common,
&rxq->common)) != 0)
esmp, sc->rxq_entries, rxq->buf_base_id, EFX_RXQ_FLAG_NONE,
evq->common, &rxq->common)) != 0)
goto fail;
SFXGE_EVQ_LOCK(evq);

76
sys/kern/kern_event.c
View File

@ -102,13 +102,13 @@ TASKQUEUE_DEFINE_THREAD(kqueue_ctx);
static int kevent_copyout(void *arg, struct kevent *kevp, int count);
static int kevent_copyin(void *arg, struct kevent *kevp, int count);
static int kqueue_register(struct kqueue *kq, struct kevent *kev,
struct thread *td, int waitok);
struct thread *td, int mflag);
static int kqueue_acquire(struct file *fp, struct kqueue **kqp);
static void kqueue_release(struct kqueue *kq, int locked);
static void kqueue_destroy(struct kqueue *kq);
static void kqueue_drain(struct kqueue *kq, struct thread *td);
static int kqueue_expand(struct kqueue *kq, struct filterops *fops,
uintptr_t ident, int waitok);
uintptr_t ident, int mflag);
static void kqueue_task(void *arg, int pending);
static int kqueue_scan(struct kqueue *kq, int maxevents,
struct kevent_copyops *k_ops,
@ -150,7 +150,7 @@ static void knote_drop_detached(struct knote *kn, struct thread *td);
static void knote_enqueue(struct knote *kn);
static void knote_dequeue(struct knote *kn);
static void knote_init(void);
static struct knote *knote_alloc(int waitok);
static struct knote *knote_alloc(int mflag);
static void knote_free(struct knote *kn);
static void filt_kqdetach(struct knote *kn);
@ -535,8 +535,9 @@ knote_fork(struct knlist *list, int pid)
if (list == NULL)
return;
list->kl_lock(list->kl_lockarg);
memset(&kev, 0, sizeof(kev));
list->kl_lock(list->kl_lockarg);
SLIST_FOREACH(kn, &list->kl_list, kn_selnext) {
kq = kn->kn_kq;
KQ_LOCK(kq);
@ -581,7 +582,7 @@ knote_fork(struct knlist *list, int pid)
kev.fflags = kn->kn_sfflags;
kev.data = kn->kn_id; /* parent */
kev.udata = kn->kn_kevent.udata;/* preserve udata */
error = kqueue_register(kq, &kev, NULL, 0);
error = kqueue_register(kq, &kev, NULL, M_NOWAIT);
if (error)
kn->kn_fflags |= NOTE_TRACKERR;
@ -595,15 +596,15 @@ knote_fork(struct knlist *list, int pid)
kev.fflags = kn->kn_sfflags;
kev.data = kn->kn_id; /* parent */
kev.udata = kn->kn_kevent.udata;/* preserve udata */
error = kqueue_register(kq, &kev, NULL, 0);
error = kqueue_register(kq, &kev, NULL, M_NOWAIT);
if (error)
kn->kn_fflags |= NOTE_TRACKERR;
if (kn->kn_fop->f_event(kn, NOTE_FORK))
KNOTE_ACTIVATE(kn, 0);
list->kl_lock(list->kl_lockarg);
KQ_LOCK(kq);
kn_leave_flux(kn);
KQ_UNLOCK_FLUX(kq);
list->kl_lock(list->kl_lockarg);
}
list->kl_unlock(list->kl_lockarg);
}
@ -1228,7 +1229,7 @@ kqueue_kevent(struct kqueue *kq, struct thread *td, int nchanges, int nevents,
if (!kevp->filter)
continue;
kevp->flags &= ~EV_SYSFLAGS;
error = kqueue_register(kq, kevp, td, 1);
error = kqueue_register(kq, kevp, td, M_WAITOK);
if (error || (kevp->flags & EV_RECEIPT)) {
if (nevents == 0)
return (error);
@ -1369,12 +1370,11 @@ kqueue_fo_release(int filt)
}
/*
* A ref to kq (obtained via kqueue_acquire) must be held. waitok will
* influence if memory allocation should wait. Make sure it is 0 if you
* hold any mutexes.
* A ref to kq (obtained via kqueue_acquire) must be held.
*/
static int
kqueue_register(struct kqueue *kq, struct kevent *kev, struct thread *td, int waitok)
kqueue_register(struct kqueue *kq, struct kevent *kev, struct thread *td,
int mflag)
{
struct filterops *fops;
struct file *fp;
@ -1404,7 +1404,7 @@ kqueue_register(struct kqueue *kq, struct kevent *kev, struct thread *td, int wa
* allocation failures are handled in the loop, only
* if the spare knote appears to be actually required.
*/
tkn = knote_alloc(waitok);
tkn = knote_alloc(mflag);
} else {
tkn = NULL;
}
@ -1420,11 +1420,11 @@ findkn:
goto done;
if ((kev->flags & EV_ADD) == EV_ADD && kqueue_expand(kq, fops,
kev->ident, 0) != 0) {
kev->ident, M_NOWAIT) != 0) {
/* try again */
fdrop(fp, td);
fp = NULL;
error = kqueue_expand(kq, fops, kev->ident, waitok);
error = kqueue_expand(kq, fops, kev->ident, mflag);
if (error)
goto done;
goto findkn;
@ -1460,8 +1460,11 @@ findkn:
break;
}
} else {
if ((kev->flags & EV_ADD) == EV_ADD)
kqueue_expand(kq, fops, kev->ident, waitok);
if ((kev->flags & EV_ADD) == EV_ADD) {
error = kqueue_expand(kq, fops, kev->ident, mflag);
if (error != 0)
goto done;
}
KQ_LOCK(kq);
@ -1689,16 +1692,15 @@ kqueue_schedtask(struct kqueue *kq)
*/
static int
kqueue_expand(struct kqueue *kq, struct filterops *fops, uintptr_t ident,
int waitok)
int mflag)
{
struct klist *list, *tmp_knhash, *to_free;
u_long tmp_knhashmask;
int size;
int fd;
int mflag = waitok ? M_WAITOK : M_NOWAIT;
int error, fd, size;
KQ_NOTOWNED(kq);
error = 0;
to_free = NULL;
if (fops->f_isfd) {
fd = ident;
@ -1710,9 +1712,11 @@ kqueue_expand(struct kqueue *kq, struct filterops *fops, uintptr_t ident,
if (list == NULL)
return ENOMEM;
KQ_LOCK(kq);
if (kq->kq_knlistsize > fd) {
if ((kq->kq_state & KQ_CLOSING) != 0) {
to_free = list;
error = EBADF;
} else if (kq->kq_knlistsize > fd) {
to_free = list;
list = NULL;
} else {
if (kq->kq_knlist != NULL) {
bcopy(kq->kq_knlist, list,
@ -1731,12 +1735,15 @@ kqueue_expand(struct kqueue *kq, struct filterops *fops, uintptr_t ident,
} else {
if (kq->kq_knhashmask == 0) {
tmp_knhash = hashinit_flags(KN_HASHSIZE, M_KQUEUE,
&tmp_knhashmask,
waitok ? HASH_WAITOK : HASH_NOWAIT);
&tmp_knhashmask, (mflag & M_WAITOK) != 0 ?
HASH_WAITOK : HASH_NOWAIT);
if (tmp_knhash == NULL)
return ENOMEM;
return (ENOMEM);
KQ_LOCK(kq);
if (kq->kq_knhashmask == 0) {
if ((kq->kq_state & KQ_CLOSING) != 0) {
to_free = tmp_knhash;
error = EBADF;
} else if (kq->kq_knhashmask == 0) {
kq->kq_knhash = tmp_knhash;
kq->kq_knhashmask = tmp_knhashmask;
} else {
@ -1748,7 +1755,7 @@ kqueue_expand(struct kqueue *kq, struct filterops *fops, uintptr_t ident,
free(to_free, M_KQUEUE);
KQ_NOTOWNED(kq);
return 0;
return (error);
}
static void
@ -1818,7 +1825,7 @@ kqueue_scan(struct kqueue *kq, int maxevents, struct kevent_copyops *k_ops,
asbt = -1;
} else
asbt = 0;
marker = knote_alloc(1);
marker = knote_alloc(M_WAITOK);
marker->kn_status = KN_MARKER;
KQ_LOCK(kq);
@ -2597,6 +2604,8 @@ knote_attach(struct knote *kn, struct kqueue *kq)
KASSERT(kn_in_flux(kn), ("knote %p not marked influx", kn));
KQ_OWNED(kq);
if ((kq->kq_state & KQ_CLOSING) != 0)
return (EBADF);
if (kn->kn_fop->f_isfd) {
if (kn->kn_id >= kq->kq_knlistsize)
return (ENOMEM);
@ -2692,11 +2701,10 @@ knote_init(void)
SYSINIT(knote, SI_SUB_PSEUDO, SI_ORDER_ANY, knote_init, NULL);
static struct knote *
knote_alloc(int waitok)
knote_alloc(int mflag)
{
return (uma_zalloc(knote_zone, (waitok ? M_WAITOK : M_NOWAIT) |
M_ZERO));
return (uma_zalloc(knote_zone, mflag | M_ZERO));
}
static void
@ -2710,7 +2718,7 @@ knote_free(struct knote *kn)
* Register the kev w/ the kq specified by fd.
*/
int
kqfd_register(int fd, struct kevent *kev, struct thread *td, int waitok)
kqfd_register(int fd, struct kevent *kev, struct thread *td, int mflag)
{
struct kqueue *kq;
struct file *fp;
@ -2723,7 +2731,7 @@ kqfd_register(int fd, struct kevent *kev, struct thread *td, int waitok)
if ((error = kqueue_acquire(fp, &kq)) != 0)
goto noacquire;
error = kqueue_register(kq, kev, td, waitok);
error = kqueue_register(kq, kev, td, mflag);
kqueue_release(kq, 0);
noacquire:

2
sys/kern/subr_blist.c
View File

@ -764,6 +764,8 @@ blst_meta_alloc(blmeta_t *scan, daddr_t cursor, daddr_t count, u_daddr_t radix)
/* Discard any candidates that appear before cursor. */
digit = (cursor / radix) & BLIST_META_MASK;
mask &= (u_daddr_t)-1 << digit;
if (mask == 0)
return (SWAPBLK_NONE);
/*
* If the first try is for a block that includes the cursor, pre-undo

7
sys/kern/vfs_aio.c
View File

@ -1589,12 +1589,13 @@ aio_aqueue(struct thread *td, struct aiocb *ujob, struct aioliojob *lj,
goto aqueue_fail;
}
kqfd = job->uaiocb.aio_sigevent.sigev_notify_kqueue;
memset(&kev, 0, sizeof(kev));
kev.ident = (uintptr_t)job->ujob;
kev.filter = EVFILT_AIO;
kev.flags = EV_ADD | EV_ENABLE | EV_FLAG1 | evflags;
kev.data = (intptr_t)job;
kev.udata = job->uaiocb.aio_sigevent.sigev_value.sival_ptr;
error = kqfd_register(kqfd, &kev, td, 1);
error = kqfd_register(kqfd, &kev, td, M_WAITOK);
if (error)
goto aqueue_fail;
@ -2155,6 +2156,7 @@ kern_lio_listio(struct thread *td, int mode, struct aiocb * const *uacb_list,
bcopy(sig, &lj->lioj_signal, sizeof(lj->lioj_signal));
if (lj->lioj_signal.sigev_notify == SIGEV_KEVENT) {
/* Assume only new style KEVENT */
memset(&kev, 0, sizeof(kev));
kev.filter = EVFILT_LIO;
kev.flags = EV_ADD | EV_ENABLE | EV_FLAG1;
kev.ident = (uintptr_t)uacb_list; /* something unique */
@ -2162,7 +2164,8 @@ kern_lio_listio(struct thread *td, int mode, struct aiocb * const *uacb_list,
/* pass user defined sigval data */
kev.udata = lj->lioj_signal.sigev_value.sival_ptr;
error = kqfd_register(
lj->lioj_signal.sigev_notify_kqueue, &kev, td, 1);
lj->lioj_signal.sigev_notify_kqueue, &kev, td,
M_WAITOK);
if (error) {
uma_zfree(aiolio_zone, lj);
return (error);

2
sys/sys/event.h
View File

@ -348,7 +348,7 @@ void knlist_cleardel(struct knlist *knl, struct thread *td,
knlist_cleardel((knl), (td), (islocked), 1)
void knote_fdclose(struct thread *p, int fd);
int kqfd_register(int fd, struct kevent *kev, struct thread *p,
int waitok);
int mflag);
int kqueue_add_filteropts(int filt, struct filterops *filtops);
int kqueue_del_filteropts(int filt);