Modify handling of writes to the vlapic ID, LDR and DFR registers.
The handlers are now called after the register value is updated in the virtual APIC page. This will make it easier to handle APIC-write VM-exits with APIC register virtualization turned on. Additionally, we need to ensure that the value of these registers is always correctly reflected in the virtual APIC page, because there is no VM exit when the guest reads these registers with APIC register virtualization.
This commit is contained in:
Neel Natu
parent
4ca1cd1d63
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3f0ddc7c5c
@ -125,72 +125,71 @@ vlapic_get_id(struct vlapic *vlapic)
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return (vlapic->vcpuid << 24);
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}
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static __inline uint32_t
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vlapic_get_ldr(struct vlapic *vlapic)
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static uint32_t
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x2apic_ldr(struct vlapic *vlapic)
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{
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struct LAPIC *lapic;
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int apicid;
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uint32_t ldr;
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lapic = vlapic->apic_page;
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if (x2apic(vlapic)) {
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apicid = vlapic_get_id(vlapic);
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ldr = 1 << (apicid & 0xf);
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ldr |= (apicid & 0xffff0) << 12;
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return (ldr);
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} else
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return (lapic->ldr);
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apicid = vlapic_get_id(vlapic);
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ldr = 1 << (apicid & 0xf);
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ldr |= (apicid & 0xffff0) << 12;
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return (ldr);
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}
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static __inline uint32_t
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vlapic_get_dfr(struct vlapic *vlapic)
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void
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vlapic_dfr_write_handler(struct vlapic *vlapic)
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{
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struct LAPIC *lapic;
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lapic = vlapic->apic_page;
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if (x2apic(vlapic))
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return (0);
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else
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return (lapic->dfr);
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}
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static void
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vlapic_set_dfr(struct vlapic *vlapic, uint32_t data)
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{
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uint32_t dfr;
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struct LAPIC *lapic;
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if (x2apic(vlapic)) {
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VM_CTR1(vlapic->vm, "write to DFR in x2apic mode: %#x", data);
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VM_CTR1(vlapic->vm, "ignoring write to DFR in x2apic mode: %#x",
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lapic->dfr);
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lapic->dfr = 0;
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return;
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}
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lapic = vlapic->apic_page;
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dfr = (lapic->dfr & APIC_DFR_RESERVED) | (data & APIC_DFR_MODEL_MASK);
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if ((dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT)
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lapic->dfr &= APIC_DFR_MODEL_MASK;
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lapic->dfr |= APIC_DFR_RESERVED;
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if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT)
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VLAPIC_CTR0(vlapic, "vlapic DFR in Flat Model");
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else if ((dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_CLUSTER)
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else if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_CLUSTER)
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VLAPIC_CTR0(vlapic, "vlapic DFR in Cluster Model");
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else
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VLAPIC_CTR1(vlapic, "vlapic DFR in Unknown Model %#x", dfr);
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lapic->dfr = dfr;
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VLAPIC_CTR1(vlapic, "DFR in Unknown Model %#x", lapic->dfr);
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}
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static void
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vlapic_set_ldr(struct vlapic *vlapic, uint32_t data)
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void
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vlapic_ldr_write_handler(struct vlapic *vlapic)
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{
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struct LAPIC *lapic;
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lapic = vlapic->apic_page;
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/* LDR is read-only in x2apic mode */
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if (x2apic(vlapic)) {
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VLAPIC_CTR1(vlapic, "write to LDR in x2apic mode: %#x", data);
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return;
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VLAPIC_CTR1(vlapic, "ignoring write to LDR in x2apic mode: %#x",
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lapic->ldr);
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lapic->ldr = x2apic_ldr(vlapic);
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} else {
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lapic->ldr &= ~APIC_LDR_RESERVED;
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VLAPIC_CTR1(vlapic, "vlapic LDR set to %#x", lapic->ldr);
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}
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}
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void
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vlapic_id_write_handler(struct vlapic *vlapic)
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{
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struct LAPIC *lapic;
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/*
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* We don't allow the ID register to be modified so reset it back to
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* its default value.
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*/
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lapic = vlapic->apic_page;
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lapic->ldr = data & ~APIC_LDR_RESERVED;
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VLAPIC_CTR1(vlapic, "vlapic LDR set to %#x", lapic->ldr);
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lapic->id = vlapic_get_id(vlapic);
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}
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static int
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@ -314,6 +313,7 @@ vlapic_reset(struct vlapic *vlapic)
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lapic = vlapic->apic_page;
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bzero(lapic, sizeof(struct LAPIC));
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lapic->id = vlapic_get_id(vlapic);
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lapic->version = VLAPIC_VERSION;
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lapic->version |= (VLAPIC_MAXLVT_ENTRIES << MAXLVTSHIFT);
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lapic->dfr = 0xffffffff;
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@ -843,8 +843,8 @@ vlapic_calcdest(struct vm *vm, cpuset_t *dmask, uint32_t dest, bool phys,
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CPU_CLR(vcpuid, &amask);
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vlapic = vm_lapic(vm, vcpuid);
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dfr = vlapic_get_dfr(vlapic);
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ldr = vlapic_get_ldr(vlapic);
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dfr = vlapic->apic_page->dfr;
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ldr = vlapic->apic_page->ldr;
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if ((dfr & APIC_DFR_MODEL_MASK) ==
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APIC_DFR_MODEL_FLAT) {
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@ -1099,7 +1099,7 @@ vlapic_read(struct vlapic *vlapic, uint64_t offset, uint64_t *data, bool *retu)
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switch(offset)
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{
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case APIC_OFFSET_ID:
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*data = vlapic_get_id(vlapic);
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*data = lapic->id;
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break;
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case APIC_OFFSET_VER:
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*data = lapic->version;
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@ -1117,10 +1117,10 @@ vlapic_read(struct vlapic *vlapic, uint64_t offset, uint64_t *data, bool *retu)
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*data = lapic->eoi;
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break;
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case APIC_OFFSET_LDR:
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*data = vlapic_get_ldr(vlapic);
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*data = lapic->ldr;
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break;
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case APIC_OFFSET_DFR:
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*data = vlapic_get_dfr(vlapic);
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*data = lapic->dfr;
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break;
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case APIC_OFFSET_SVR:
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*data = lapic->svr;
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@ -1178,6 +1178,9 @@ vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data, bool *retu)
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struct LAPIC *lapic = vlapic->apic_page;
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int retval;
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KASSERT((offset & 0xf) == 0 && offset < PAGE_SIZE,
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("vlapic_write: invalid offset %#lx", offset));
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VLAPIC_CTR2(vlapic, "vlapic write offset %#x, data %#lx", offset, data);
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if (offset > sizeof(*lapic)) {
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@ -1185,10 +1188,11 @@ vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data, bool *retu)
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}
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retval = 0;
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offset &= ~3;
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switch(offset)
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{
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case APIC_OFFSET_ID:
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lapic->id = data;
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vlapic_id_write_handler(vlapic);
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break;
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case APIC_OFFSET_TPR:
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lapic->tpr = data & 0xff;
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@ -1198,10 +1202,12 @@ vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data, bool *retu)
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vlapic_process_eoi(vlapic);
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break;
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case APIC_OFFSET_LDR:
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vlapic_set_ldr(vlapic, data);
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lapic->ldr = data;
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vlapic_ldr_write_handler(vlapic);
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break;
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case APIC_OFFSET_DFR:
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vlapic_set_dfr(vlapic, data);
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lapic->dfr = data;
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vlapic_dfr_write_handler(vlapic);
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break;
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case APIC_OFFSET_SVR:
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lapic_set_svr(vlapic, data);
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@ -1292,19 +1298,38 @@ vlapic_get_apicbase(struct vlapic *vlapic)
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}
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void
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vlapic_set_apicbase(struct vlapic *vlapic, uint64_t val)
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vlapic_set_apicbase(struct vlapic *vlapic, uint64_t new)
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{
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int err;
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struct LAPIC *lapic;
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enum x2apic_state state;
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uint64_t old;
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int err;
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err = vm_get_x2apic_state(vlapic->vm, vlapic->vcpuid, &state);
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if (err)
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panic("vlapic_set_apicbase: err %d fetching x2apic state", err);
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if (state == X2APIC_DISABLED)
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val &= ~APICBASE_X2APIC;
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new &= ~APICBASE_X2APIC;
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vlapic->msr_apicbase = val;
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old = vlapic->msr_apicbase;
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vlapic->msr_apicbase = new;
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/*
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* If the vlapic is switching between xAPIC and x2APIC modes then
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* reset the mode-dependent registers.
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*/
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if ((old ^ new) & APICBASE_X2APIC) {
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lapic = vlapic->apic_page;
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lapic->id = vlapic_get_id(vlapic);
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if (x2apic(vlapic)) {
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lapic->ldr = x2apic_ldr(vlapic);
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lapic->dfr = 0;
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} else {
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lapic->ldr = 0;
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lapic->dfr = 0xffffffff;
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}
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}
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}
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void
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@ -70,4 +70,9 @@ bool vlapic_enabled(struct vlapic *vlapic);
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void vlapic_deliver_intr(struct vm *vm, bool level, uint32_t dest, bool phys,
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int delmode, int vec);
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void vlapic_post_intr(struct vlapic *vlapic, int hostcpu);
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/* APIC write handlers */
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void vlapic_id_write_handler(struct vlapic *vlapic);
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void vlapic_ldr_write_handler(struct vlapic *vlapic);
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void vlapic_dfr_write_handler(struct vlapic *vlapic);
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#endif /* _VLAPIC_H_ */
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