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Backout bogus checkin to HEAD

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Approved by: scottl
This commit is contained in:
jfv 2006-10-28 08:11:07 +00:00
parent 4aff3f8e66
commit 4061ab1e3c
5 changed files with 1707 additions and 1503 deletions
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1535
sys/dev/em/if_em.c
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170
sys/dev/em/if_em.h
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@ -30,6 +30,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/ ***************************************************************************/
/*$FreeBSD$*/ /*$FreeBSD$*/
#ifndef _EM_H_DEFINED_ #ifndef _EM_H_DEFINED_
@ -85,8 +86,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define EM_TIDV 64 #define EM_TIDV 64
/* /*
* EM_TADV - Transmit Absolute Interrupt Delay Value * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
* (Not valid for 82542/82543/82544)
* Valid Range: 0-65535 (0=off) * Valid Range: 0-65535 (0=off)
* Default Value: 64 * Default Value: 64
* This value, in units of 1.024 microseconds, limits the delay in which a * This value, in units of 1.024 microseconds, limits the delay in which a
@ -112,10 +112,10 @@ POSSIBILITY OF SUCH DAMAGE.
* *
* CAUTION: When setting EM_RDTR to a value other than 0, adapters * CAUTION: When setting EM_RDTR to a value other than 0, adapters
* may hang (stop transmitting) under certain network conditions. * may hang (stop transmitting) under certain network conditions.
* If this occurs a WATCHDOG message is logged in the system * If this occurs a WATCHDOG message is logged in the system event log.
* event log. In addition, the controller is automatically reset, * In addition, the controller is automatically reset, restoring the
* restoring the network connection. To eliminate the potential * network connection. To eliminate the potential for the hang
* for the hang ensure that EM_RDTR is set to 0. * ensure that EM_RDTR is set to 0.
*/ */
#define EM_RDTR 0 #define EM_RDTR 0
@ -137,12 +137,10 @@ POSSIBILITY OF SUCH DAMAGE.
*/ */
#define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) #define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP)
#ifdef EM_TSO
/* /*
* Inform the stack about transmit segmentation offload capabilities. * Inform the stack about transmit segmentation offload capabilities.
*/ */
#define EM_TCPSEG_FEATURES CSUM_TSO #define EM_TCPSEG_FEATURES CSUM_TSO
#endif
/* /*
* This parameter controls the duration of transmit watchdog timer. * This parameter controls the duration of transmit watchdog timer.
@ -171,10 +169,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define WAIT_FOR_AUTO_NEG_DEFAULT 0 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
/* /*
* EM_MASTER_SLAVE is only defined to enable a workaround for a known * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
* compatibility issue with 82541/82547 devices and some switches. * with 82541/82547 devices and some switches. See the "Known Limitations" section of
* See the "Known Limitations" section of the README file for a complete * the README file for a complete description and a list of affected switches.
* description and a list of affected switches.
* *
* 0 = Hardware default * 0 = Hardware default
* 1 = Master mode * 1 = Master mode
@ -185,12 +182,12 @@ POSSIBILITY OF SUCH DAMAGE.
/* Tunables -- End */ /* Tunables -- End */
#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
ADVERTISE_1000_FULL) ADVERTISE_1000_FULL)
#define EM_VENDOR_ID 0x8086 #define EM_VENDOR_ID 0x8086
#define EM_FLASH 0x0014 /* Flash memory on ICH8 */ #define EM_FLASH 0x0014 /* Flash memory on ICH8 */
#define EM_JUMBO_PBA 0x00000028 #define EM_JUMBO_PBA 0x00000028
#define EM_DEFAULT_PBA 0x00000030 #define EM_DEFAULT_PBA 0x00000030
@ -210,22 +207,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
/* PCI Config defines */
#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
#define EM_BAR_TYPE_MASK 0x00000001
#define EM_BAR_TYPE_MMEM 0x00000000
#define EM_BAR_TYPE_IO 0x00000001
#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
#define EM_BAR_MEM_TYPE_MASK 0x00000006
#define EM_BAR_MEM_TYPE_32BIT 0x00000000
#define EM_BAR_MEM_TYPE_64BIT 0x00000004
/*
* Backward compatibility hack
*/
#if !defined(PCIR_CIS)
#define PCIR_CIS PCIR_CARDBUSCIS
#endif
/* Defines for printing debug information */ /* Defines for printing debug information */
#define DEBUG_INIT 0 #define DEBUG_INIT 0
#define DEBUG_IOCTL 0 #define DEBUG_IOCTL 0
@ -248,43 +229,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define EM_RXBUFFER_8192 8192 #define EM_RXBUFFER_8192 8192
#define EM_RXBUFFER_16384 16384 #define EM_RXBUFFER_16384 16384
#define EM_MAX_SCATTER 64 #define EM_MAX_SCATTER 64
#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */ #define EM_TSO_SIZE 65535
/* ******************************************************************************
* vendor_info_array
*
* This array contains the list of Subvendor/Subdevice IDs on which the driver
* should load.
*
* ******************************************************************************/
typedef struct _em_vendor_info_t {
unsigned int vendor_id;
unsigned int device_id;
unsigned int subvendor_id;
unsigned int subdevice_id;
unsigned int index;
} em_vendor_info_t;
struct em_buffer {
int next_eop; /* Index of the desc to watch */
struct mbuf *m_head;
bus_dmamap_t map; /* bus_dma map for packet */
};
/*
* Bus dma allocation structure used by
* em_dma_malloc and em_dma_free.
*/
struct em_dma_alloc {
bus_addr_t dma_paddr;
caddr_t dma_vaddr;
bus_dma_tag_t dma_tag;
bus_dmamap_t dma_map;
bus_dma_segment_t dma_seg;
int dma_nseg;
};
typedef enum _XSUM_CONTEXT_T { typedef enum _XSUM_CONTEXT_T {
OFFLOAD_NONE, OFFLOAD_NONE,
@ -292,27 +238,28 @@ typedef enum _XSUM_CONTEXT_T {
OFFLOAD_UDP_IP OFFLOAD_UDP_IP
} XSUM_CONTEXT_T; } XSUM_CONTEXT_T;
struct adapter adapter; /* XXX: ugly forward declaration */ struct adapter;
struct em_int_delay_info { struct em_int_delay_info {
struct adapter *adapter; /* Back-pointer to the adapter struct */ struct adapter *adapter; /* Back-pointer to the adapter struct */
int offset; /* Register offset to read/write */ int offset; /* Register offset to read/write */
int value; /* Current value in usecs */ int value; /* Current value in usecs */
}; };
/* For 82544 PCIX Workaround */ /*
typedef struct _ADDRESS_LENGTH_PAIR * Bus dma allocation structure used by
{ * em_dma_malloc() and em_dma_free().
uint64_t address; */
uint32_t length; struct em_dma_alloc {
} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; bus_addr_t dma_paddr;
caddr_t dma_vaddr;
bus_dma_tag_t dma_tag;
bus_dmamap_t dma_map;
bus_dma_segment_t dma_seg;
int dma_nseg;
};
typedef struct _DESCRIPTOR_PAIR /* Driver softc. */
{
ADDRESS_LENGTH_PAIR descriptor[4];
uint32_t elements;
} DESC_ARRAY, *PDESC_ARRAY;
/* Our adapter structure */
struct adapter { struct adapter {
struct ifnet *ifp; struct ifnet *ifp;
struct em_hw hw; struct em_hw hw;
@ -332,6 +279,10 @@ struct adapter {
int if_flags; int if_flags;
struct mtx mtx; struct mtx mtx;
int em_insert_vlan_header; int em_insert_vlan_header;
struct task link_task;
struct task rxtx_task;
struct taskqueue *tq; /* private task queue */
/* Info about the board itself */ /* Info about the board itself */
uint32_t part_num; uint32_t part_num;
uint8_t link_active; uint8_t link_active;
@ -357,13 +308,13 @@ struct adapter {
struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
struct em_tx_desc *tx_desc_base; struct em_tx_desc *tx_desc_base;
uint32_t next_avail_tx_desc; uint32_t next_avail_tx_desc;
uint32_t next_tx_to_clean; uint32_t oldest_used_tx_desc;
volatile uint16_t num_tx_desc_avail; volatile uint16_t num_tx_desc_avail;
uint16_t num_tx_desc; uint16_t num_tx_desc;
uint32_t txd_cmd; uint32_t txd_cmd;
struct em_buffer *tx_buffer_area; struct em_buffer *tx_buffer_area;
bus_dma_tag_t txtag; /* dma tag for tx */ bus_dma_tag_t txtag; /* dma tag for tx */
uint32_t tx_tso; /* last tx was tso */ uint32_t tx_tso; /* last tx was tso */
/* /*
* Receive definitions * Receive definitions
@ -381,16 +332,13 @@ struct adapter {
int rx_process_limit; int rx_process_limit;
struct em_buffer *rx_buffer_area; struct em_buffer *rx_buffer_area;
bus_dma_tag_t rxtag; bus_dma_tag_t rxtag;
bus_dmamap_t rx_sparemap;
/* /* First/last mbuf pointers, for collecting multisegment RX packets. */
* First/last mbuf pointers, for
* collecting multisegment RX packets.
*/
struct mbuf *fmp; struct mbuf *fmp;
struct mbuf *lmp; struct mbuf *lmp;
/* Misc stats maintained by the driver */ /* Misc stats maintained by the driver */
unsigned long dropped_pkts;
unsigned long mbuf_alloc_failed; unsigned long mbuf_alloc_failed;
unsigned long mbuf_cluster_failed; unsigned long mbuf_cluster_failed;
unsigned long no_tx_desc_avail1; unsigned long no_tx_desc_avail1;
@ -422,6 +370,40 @@ struct adapter {
struct em_hw_stats stats; struct em_hw_stats stats;
}; };
/* ******************************************************************************
* vendor_info_array
*
* This array contains the list of Subvendor/Subdevice IDs on which the driver
* should load.
*
* ******************************************************************************/
typedef struct _em_vendor_info_t {
unsigned int vendor_id;
unsigned int device_id;
unsigned int subvendor_id;
unsigned int subdevice_id;
unsigned int index;
} em_vendor_info_t;
struct em_buffer {
struct mbuf *m_head;
bus_dmamap_t map; /* bus_dma map for packet */
};
/* For 82544 PCIX Workaround */
typedef struct _ADDRESS_LENGTH_PAIR
{
u_int64_t address;
u_int32_t length;
} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
typedef struct _DESCRIPTOR_PAIR
{
ADDRESS_LENGTH_PAIR descriptor[4];
u_int32_t elements;
} DESC_ARRAY, *PDESC_ARRAY;
#define EM_LOCK_INIT(_sc, _name) \ #define EM_LOCK_INIT(_sc, _name) \
mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) #define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)

1113
sys/dev/em/if_em_hw.c
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292
sys/dev/em/if_em_hw.h
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@ -1,38 +1,35 @@
/******************************************************************************* /*******************************************************************************
Copyright (c) 2001-2005, Intel Corporation
All rights reserved.
Copyright (c) 2001-2005, Intel Corporation Redistribution and use in source and binary forms, with or without
All rights reserved. modification, are permitted provided that the following conditions are met:
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/ *******************************************************************************/
/*$FreeBSD$*/ /* $FreeBSD$ */
/* if_em_hw.h /* if_em_hw.h
* Structures, enums, and macros for the MAC * Structures, enums, and macros for the MAC
*/ */
@ -40,7 +37,11 @@
#ifndef _EM_HW_H_ #ifndef _EM_HW_H_
#define _EM_HW_H_ #define _EM_HW_H_
#ifdef LM
#include "if_em_osdep.h"
#else
#include <dev/em/if_em_osdep.h> #include <dev/em/if_em_osdep.h>
#endif
/* Forward declarations of structures used by the shared code */ /* Forward declarations of structures used by the shared code */
@ -97,6 +98,15 @@ typedef enum {
em_100_full = 3 em_100_full = 3
} em_speed_duplex_type; } em_speed_duplex_type;
/* Flow Control Settings */
typedef enum {
em_fc_none = 0,
em_fc_rx_pause = 1,
em_fc_tx_pause = 2,
em_fc_full = 3,
em_fc_default = 0xFF
} em_fc_type;
struct em_shadow_ram { struct em_shadow_ram {
uint16_t eeprom_word; uint16_t eeprom_word;
boolean_t modified; boolean_t modified;
@ -126,13 +136,11 @@ typedef enum {
/* PCI bus widths */ /* PCI bus widths */
typedef enum { typedef enum {
em_bus_width_unknown = 0, em_bus_width_unknown = 0,
/* These PCIe values should literally match the possible return values
* from config space */
em_bus_width_pciex_1 = 1,
em_bus_width_pciex_2 = 2,
em_bus_width_pciex_4 = 4,
em_bus_width_32, em_bus_width_32,
em_bus_width_64, em_bus_width_64,
em_bus_width_pciex_1,
em_bus_width_pciex_2,
em_bus_width_pciex_4,
em_bus_width_reserved em_bus_width_reserved
} em_bus_width; } em_bus_width;
@ -301,13 +309,11 @@ typedef enum {
#define E1000_BLK_PHY_RESET 12 #define E1000_BLK_PHY_RESET 12
#define E1000_ERR_SWFW_SYNC 13 #define E1000_ERR_SWFW_SYNC 13
#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
(((_value) & 0xff00) >> 8))
/* Function prototypes */ /* Function prototypes */
/* Initialization */ /* Initialization */
int32_t em_reset_hw(struct em_hw *hw); int32_t em_reset_hw(struct em_hw *hw);
int32_t em_init_hw(struct em_hw *hw); int32_t em_init_hw(struct em_hw *hw);
int32_t em_id_led_init(struct em_hw * hw);
int32_t em_set_mac_type(struct em_hw *hw); int32_t em_set_mac_type(struct em_hw *hw);
void em_set_media_type(struct em_hw *hw); void em_set_media_type(struct em_hw *hw);
@ -315,23 +321,39 @@ void em_set_media_type(struct em_hw *hw);
int32_t em_setup_link(struct em_hw *hw); int32_t em_setup_link(struct em_hw *hw);
int32_t em_phy_setup_autoneg(struct em_hw *hw); int32_t em_phy_setup_autoneg(struct em_hw *hw);
void em_config_collision_dist(struct em_hw *hw); void em_config_collision_dist(struct em_hw *hw);
int32_t em_config_fc_after_link_up(struct em_hw *hw);
int32_t em_check_for_link(struct em_hw *hw); int32_t em_check_for_link(struct em_hw *hw);
int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex); int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t * speed, uint16_t * duplex);
int32_t em_wait_autoneg(struct em_hw *hw);
int32_t em_force_mac_fc(struct em_hw *hw); int32_t em_force_mac_fc(struct em_hw *hw);
/* PHY */ /* PHY */
int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data); int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data); int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
int32_t em_phy_hw_reset(struct em_hw *hw); int32_t em_phy_hw_reset(struct em_hw *hw);
int32_t em_phy_reset(struct em_hw *hw); int32_t em_phy_reset(struct em_hw *hw);
int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
int32_t em_validate_mdi_setting(struct em_hw *hw);
void em_phy_powerdown_workaround(struct em_hw *hw); void em_phy_powerdown_workaround(struct em_hw *hw);
int32_t em_kumeran_lock_loss_workaround(struct em_hw *hw);
int32_t em_duplex_reversal(struct em_hw *hw);
int32_t em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
int32_t em_init_lcd_from_nvm(struct em_hw *hw);
int32_t em_detect_gig_phy(struct em_hw *hw);
int32_t em_phy_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
int32_t em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
int32_t em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info);
int32_t em_get_cable_length(struct em_hw *hw, uint16_t *min_length, uint16_t *max_length);
int32_t em_check_polarity(struct em_hw *hw, uint16_t *polarity);
int32_t em_check_downshift(struct em_hw *hw);
int32_t em_validate_mdi_setting(struct em_hw *hw);
int32_t em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data);
int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data);
/* EEPROM Functions */ /* EEPROM Functions */
int32_t em_init_eeprom_params(struct em_hw *hw); int32_t em_init_eeprom_params(struct em_hw *hw);
boolean_t em_is_onboard_nvm_eeprom(struct em_hw *hw);
int32_t em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
int32_t em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
int32_t em_poll_eerd_eewr_done(struct em_hw *hw, int eerd);
/* MNG HOST IF functions */ /* MNG HOST IF functions */
uint32_t em_enable_mng_pass_thru(struct em_hw *hw); uint32_t em_enable_mng_pass_thru(struct em_hw *hw);
@ -375,24 +397,37 @@ struct em_host_mng_dhcp_cookie{
uint8_t checksum; uint8_t checksum;
}; };
int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer, int32_t em_mng_write_dhcp_info(struct em_hw *hw, uint8_t *buffer,
uint16_t length); uint16_t length);
boolean_t em_check_mng_mode(struct em_hw *hw); boolean_t em_check_mng_mode(struct em_hw *hw);
boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw); boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw);
int32_t em_mng_enable_host_if(struct em_hw *hw);
int32_t em_mng_host_if_write(struct em_hw *hw, uint8_t *buffer,
uint16_t length, uint16_t offset, uint8_t *sum);
int32_t em_mng_write_cmd_header(struct em_hw* hw,
struct em_host_mng_command_header* hdr);
int32_t em_mng_write_commit(struct em_hw *hw);
int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
int32_t em_validate_eeprom_checksum(struct em_hw *hw); int32_t em_validate_eeprom_checksum(struct em_hw *hw);
int32_t em_update_eeprom_checksum(struct em_hw *hw); int32_t em_update_eeprom_checksum(struct em_hw *hw);
int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
int32_t em_read_part_num(struct em_hw *hw, uint32_t * part_num);
int32_t em_read_mac_addr(struct em_hw * hw); int32_t em_read_mac_addr(struct em_hw * hw);
int32_t em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask);
void em_swfw_sync_release(struct em_hw *hw, uint16_t mask);
void em_release_software_flag(struct em_hw *hw);
int32_t em_get_software_flag(struct em_hw *hw);
/* Filters (multicast, vlan, receive) */ /* Filters (multicast, vlan, receive) */
void em_init_rx_addrs(struct em_hw *hw);
void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count); void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr); uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t * mc_addr);
void em_mta_set(struct em_hw *hw, uint32_t hash_value); void em_mta_set(struct em_hw *hw, uint32_t hash_value);
void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index); void em_rar_set(struct em_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value); void em_write_vfta(struct em_hw *hw, uint32_t offset, uint32_t value);
void em_clear_vfta(struct em_hw *hw);
/* LED functions */ /* LED functions */
int32_t em_setup_led(struct em_hw *hw); int32_t em_setup_led(struct em_hw *hw);
@ -405,7 +440,6 @@ int32_t em_blink_led_start(struct em_hw *hw);
/* Everything else */ /* Everything else */
void em_clear_hw_cntrs(struct em_hw *hw); void em_clear_hw_cntrs(struct em_hw *hw);
void em_reset_adaptive(struct em_hw *hw); void em_reset_adaptive(struct em_hw *hw);
void em_update_adaptive(struct em_hw *hw); void em_update_adaptive(struct em_hw *hw);
void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr); void em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
@ -414,14 +448,60 @@ void em_pci_set_mwi(struct em_hw *hw);
void em_pci_clear_mwi(struct em_hw *hw); void em_pci_clear_mwi(struct em_hw *hw);
void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value); void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value); void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t * value);
int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value);
/* Port I/O is only supported on 82544 and newer */ /* Port I/O is only supported on 82544 and newer */
uint32_t em_io_read(struct em_hw *hw, unsigned long port); uint32_t em_read_reg_io(struct em_hw *hw, uint32_t offset);
void em_io_write(struct em_hw *hw, unsigned long port, uint32_t value); void em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value);
int32_t em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up);
int32_t em_set_d3_lplu_state(struct em_hw *hw, boolean_t active);
int32_t em_set_d0_lplu_state(struct em_hw *hw, boolean_t active);
void em_set_pci_express_master_disable(struct em_hw *hw);
void em_enable_pciex_master(struct em_hw *hw);
int32_t em_disable_pciex_master(struct em_hw *hw); int32_t em_disable_pciex_master(struct em_hw *hw);
int32_t em_get_auto_rd_done(struct em_hw *hw);
int32_t em_get_phy_cfg_done(struct em_hw *hw);
int32_t em_get_software_semaphore(struct em_hw *hw);
void em_release_software_semaphore(struct em_hw *hw);
int32_t em_check_phy_reset_block(struct em_hw *hw); int32_t em_check_phy_reset_block(struct em_hw *hw);
int32_t em_get_hw_eeprom_semaphore(struct em_hw *hw);
void em_put_hw_eeprom_semaphore(struct em_hw *hw);
int32_t em_commit_shadow_ram(struct em_hw *hw);
uint8_t em_arc_subsystem_valid(struct em_hw *hw);
int32_t em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop);
int32_t em_read_ich8_byte(struct em_hw *hw, uint32_t index,
uint8_t *data);
int32_t em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index,
uint8_t byte);
int32_t em_write_ich8_byte(struct em_hw *hw, uint32_t index,
uint8_t byte);
int32_t em_read_ich8_word(struct em_hw *hw, uint32_t index,
uint16_t *data);
int32_t em_write_ich8_word(struct em_hw *hw, uint32_t index,
uint16_t word);
int32_t em_read_ich8_data(struct em_hw *hw, uint32_t index,
uint32_t size, uint16_t *data);
int32_t em_write_ich8_data(struct em_hw *hw, uint32_t index,
uint32_t size, uint16_t data);
int32_t em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset,
uint16_t words, uint16_t *data);
int32_t em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset,
uint16_t words, uint16_t *data);
int32_t em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t segment);
int32_t em_ich8_cycle_init(struct em_hw *hw);
int32_t em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout);
int32_t em_phy_ife_get_info(struct em_hw *hw,
struct em_phy_info *phy_info);
int32_t em_ife_disable_dynamic_power_down(struct em_hw *hw);
int32_t em_ife_enable_dynamic_power_down(struct em_hw *hw);
#define E1000_BAR_TYPE(v) ((v) & E1000_BAR_TYPE_MASK)
#define E1000_BAR_TYPE_MASK 0x00000001
#define E1000_BAR_TYPE_MEM 0x00000000
#define E1000_BAR_TYPE_IO 0x00000001
#define E1000_BAR_MEM_TYPE(v) ((v) & E1000_BAR_MEM_TYPE_MASK)
#define E1000_BAR_MEM_TYPE_MASK 0x00000006
#define E1000_BAR_MEM_TYPE_32BIT 0x00000000
#define E1000_BAR_MEM_TYPE_64BIT 0x00000004
#ifndef E1000_READ_REG_IO #ifndef E1000_READ_REG_IO
#define E1000_READ_REG_IO(a, reg) \ #define E1000_READ_REG_IO(a, reg) \
@ -470,7 +550,6 @@ int32_t em_check_phy_reset_block(struct em_hw *hw);
#define E1000_DEV_ID_82571EB_FIBER 0x105F #define E1000_DEV_ID_82571EB_FIBER 0x105F
#define E1000_DEV_ID_82571EB_SERDES 0x1060 #define E1000_DEV_ID_82571EB_SERDES 0x1060
#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
#define E1000_DEV_ID_82572EI_COPPER 0x107D #define E1000_DEV_ID_82572EI_COPPER 0x107D
#define E1000_DEV_ID_82572EI_FIBER 0x107E #define E1000_DEV_ID_82572EI_FIBER 0x107E
#define E1000_DEV_ID_82572EI_SERDES 0x107F #define E1000_DEV_ID_82572EI_SERDES 0x107F
@ -488,8 +567,6 @@ int32_t em_check_phy_reset_block(struct em_hw *hw);
#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
#define E1000_DEV_ID_ICH8_IGP_C 0x104B #define E1000_DEV_ID_ICH8_IGP_C 0x104B
#define E1000_DEV_ID_ICH8_IFE 0x104C #define E1000_DEV_ID_ICH8_IFE 0x104C
#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
#define E1000_DEV_ID_ICH8_IGP_M 0x104D #define E1000_DEV_ID_ICH8_IGP_M 0x104D
@ -559,9 +636,9 @@ int32_t em_check_phy_reset_block(struct em_hw *hw);
E1000_IMS_TXDW | \ E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \ E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \ E1000_IMS_RXSEQ | \
E1000_IMS_RXO | \
E1000_IMS_LSC) E1000_IMS_LSC)
/* Additional interrupts need to be handled for em_ich8lan: /* Additional interrupts need to be handled for em_ich8lan:
DSW = The FW changed the status of the DISSW bit in FWSM DSW = The FW changed the status of the DISSW bit in FWSM
PHYINT = The LAN connected device generates an interrupt PHYINT = The LAN connected device generates an interrupt
@ -571,18 +648,16 @@ int32_t em_check_phy_reset_block(struct em_hw *hw);
E1000_IMS_PHYINT | \ E1000_IMS_PHYINT | \
E1000_IMS_EPRST) E1000_IMS_EPRST)
/* Number of high/low register pairs in the RAR. The RAR (Receive Address /* Number of high/low register pairs in the RAR. The RAR (Receive Address
* Registers) holds the directed and multicast addresses that we monitor. We * Registers) holds the directed and multicast addresses that we monitor. We
* reserve one of these spots for our directed address, allowing us room for * reserve one of these spots for our directed address, allowing us room for
* E1000_RAR_ENTRIES - 1 multicast addresses. * E1000_RAR_ENTRIES - 1 multicast addresses.
*/ */
#define E1000_RAR_ENTRIES 15 #define E1000_RAR_ENTRIES 15
#define E1000_RAR_ENTRIES_ICH8LAN 7
#define E1000_RAR_ENTRIES_ICH8LAN 6 #define MIN_NUMBER_OF_DESCRIPTORS 8
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
#define MIN_NUMBER_OF_DESCRIPTORS 8
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
/* Receive Descriptor */ /* Receive Descriptor */
struct em_rx_desc { struct em_rx_desc {
@ -703,7 +778,6 @@ union em_rx_desc_packet_split {
E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_CXE | \
E1000_RXDEXT_STATERR_RXE) E1000_RXDEXT_STATERR_RXE)
/* Transmit Descriptor */ /* Transmit Descriptor */
struct em_tx_desc { struct em_tx_desc {
uint64_t buffer_addr; /* Address of the descriptor's data buffer */ uint64_t buffer_addr; /* Address of the descriptor's data buffer */
@ -1382,7 +1456,7 @@ struct em_hw {
struct em_shadow_ram *eeprom_shadow_ram; struct em_shadow_ram *eeprom_shadow_ram;
uint32_t flash_bank_size; uint32_t flash_bank_size;
uint32_t flash_base_addr; uint32_t flash_base_addr;
uint32_t fc; em_fc_type fc;
em_bus_speed bus_speed; em_bus_speed bus_speed;
em_bus_width bus_width; em_bus_width bus_width;
em_bus_type bus_type; em_bus_type bus_type;
@ -1394,7 +1468,6 @@ struct em_hw {
uint32_t eeprom_semaphore_present; uint32_t eeprom_semaphore_present;
uint32_t swfw_sync_present; uint32_t swfw_sync_present;
uint32_t swfwhw_semaphore_present; uint32_t swfwhw_semaphore_present;
unsigned long io_base; unsigned long io_base;
uint32_t phy_id; uint32_t phy_id;
uint32_t phy_revision; uint32_t phy_revision;
@ -1446,7 +1519,6 @@ struct em_hw {
boolean_t tbi_compatibility_on; boolean_t tbi_compatibility_on;
boolean_t laa_is_present; boolean_t laa_is_present;
boolean_t phy_reset_disable; boolean_t phy_reset_disable;
boolean_t initialize_hw_bits_disable;
boolean_t fc_send_xon; boolean_t fc_send_xon;
boolean_t fc_strict_ieee; boolean_t fc_strict_ieee;
boolean_t report_tx_early; boolean_t report_tx_early;
@ -1505,6 +1577,7 @@ struct em_hw {
#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
/* Device Status */ /* Device Status */
#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
@ -1578,8 +1651,8 @@ struct em_hw {
#define E1000_HICR_FW_RESET 0xC0 #define E1000_HICR_FW_RESET 0xC0
#define E1000_SHADOW_RAM_WORDS 2048 #define E1000_SHADOW_RAM_WORDS 2048
#define E1000_ICH_NVM_SIG_WORD 0x13 #define E1000_ICH8_NVM_SIG_WORD 0x13
#define E1000_ICH_NVM_SIG_MASK 0xC0 #define E1000_ICH8_NVM_SIG_MASK 0xC0
/* EEPROM Read */ /* EEPROM Read */
#define E1000_EERD_START 0x00000001 /* Start Read */ #define E1000_EERD_START 0x00000001 /* Start Read */
@ -1619,17 +1692,16 @@ struct em_hw {
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
@ -1764,7 +1836,6 @@ struct em_hw {
#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
/* Interrupt Cause Set */ /* Interrupt Cause Set */
#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
@ -1794,7 +1865,6 @@ struct em_hw {
#define E1000_ICS_PHYINT E1000_ICR_PHYINT #define E1000_ICS_PHYINT E1000_ICR_PHYINT
#define E1000_ICS_EPRST E1000_ICR_EPRST #define E1000_ICS_EPRST E1000_ICR_EPRST
/* Interrupt Mask Set */ /* Interrupt Mask Set */
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
@ -1824,7 +1894,6 @@ struct em_hw {
#define E1000_IMS_PHYINT E1000_ICR_PHYINT #define E1000_IMS_PHYINT E1000_ICR_PHYINT
#define E1000_IMS_EPRST E1000_ICR_EPRST #define E1000_IMS_EPRST E1000_ICR_EPRST
/* Interrupt Mask Clear */ /* Interrupt Mask Clear */
#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
@ -1854,7 +1923,6 @@ struct em_hw {
#define E1000_IMC_PHYINT E1000_ICR_PHYINT #define E1000_IMC_PHYINT E1000_ICR_PHYINT
#define E1000_IMC_EPRST E1000_ICR_EPRST #define E1000_IMC_EPRST E1000_ICR_EPRST
/* Receive Control */ /* Receive Control */
#define E1000_RCTL_RST 0x00000001 /* Software reset */ #define E1000_RCTL_RST 0x00000001 /* Software reset */
#define E1000_RCTL_EN 0x00000002 /* enable */ #define E1000_RCTL_EN 0x00000002 /* enable */
@ -1942,13 +2010,6 @@ struct em_hw {
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
/* Flow Control Settings */
#define E1000_FC_NONE 0
#define E1000_FC_RX_PAUSE 1
#define E1000_FC_TX_PAUSE 2
#define E1000_FC_FULL 3
#define E1000_FC_DEFAULT 0xFF
/* Header split receive */ /* Header split receive */
#define E1000_RFCTL_ISCSI_DIS 0x00000001 #define E1000_RFCTL_ISCSI_DIS 0x00000001
#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
@ -2236,11 +2297,6 @@ struct em_host_command_info {
#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
/* PCI-Ex Config Space */
#define PCI_EX_LINK_STATUS 0x12
#define PCI_EX_LINK_WIDTH_MASK 0x3F0
#define PCI_EX_LINK_WIDTH_SHIFT 4
/* EEPROM Commands - Microwire */ /* EEPROM Commands - Microwire */
#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
@ -2548,7 +2604,6 @@ struct em_host_command_info {
#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
/* PHY 1000 MII Register/Bit Definitions */ /* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */ /* PHY Registers defined by IEEE */
#define PHY_CTRL 0x00 /* Control Register */ #define PHY_CTRL 0x00 /* Control Register */
@ -3144,7 +3199,6 @@ struct em_host_command_info {
/* I = Integrated /* I = Integrated
* E = External * E = External
*/ */
#define M88_VENDOR 0x0141
#define M88E1000_E_PHY_ID 0x01410C50 #define M88E1000_E_PHY_ID 0x01410C50
#define M88E1000_I_PHY_ID 0x01410C30 #define M88E1000_I_PHY_ID 0x01410C30
#define M88E1011_I_PHY_ID 0x01410C20 #define M88E1011_I_PHY_ID 0x01410C20
@ -3185,7 +3239,6 @@ struct em_host_command_info {
#define IGP3_VR_CTRL \ #define IGP3_VR_CTRL \
PHY_REG(776, 18) /* Voltage regulator control register */ PHY_REG(776, 18) /* Voltage regulator control register */
#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
#define IGP3_CAPABILITY \ #define IGP3_CAPABILITY \
PHY_REG(776, 19) /* IGP3 Capability Register */ PHY_REG(776, 19) /* IGP3 Capability Register */
@ -3270,40 +3323,39 @@ struct em_host_command_info {
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ #define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ #define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ #define ICH8_FLASH_SEG_SIZE_256 256
#define ICH_FLASH_SEG_SIZE_256 256 #define ICH8_FLASH_SEG_SIZE_4K 4096
#define ICH_FLASH_SEG_SIZE_4K 4096 #define ICH8_FLASH_SEG_SIZE_64K 65536
#define ICH_FLASH_SEG_SIZE_64K 65536
#define ICH_CYCLE_READ 0x0 #define ICH8_CYCLE_READ 0x0
#define ICH_CYCLE_RESERVED 0x1 #define ICH8_CYCLE_RESERVED 0x1
#define ICH_CYCLE_WRITE 0x2 #define ICH8_CYCLE_WRITE 0x2
#define ICH_CYCLE_ERASE 0x3 #define ICH8_CYCLE_ERASE 0x3
#define ICH_FLASH_GFPREG 0x0000 #define ICH8_FLASH_GFPREG 0x0000
#define ICH_FLASH_HSFSTS 0x0004 #define ICH8_FLASH_HSFSTS 0x0004
#define ICH_FLASH_HSFCTL 0x0006 #define ICH8_FLASH_HSFCTL 0x0006
#define ICH_FLASH_FADDR 0x0008 #define ICH8_FLASH_FADDR 0x0008
#define ICH_FLASH_FDATA0 0x0010 #define ICH8_FLASH_FDATA0 0x0010
#define ICH_FLASH_FRACC 0x0050 #define ICH8_FLASH_FRACC 0x0050
#define ICH_FLASH_FREG0 0x0054 #define ICH8_FLASH_FREG0 0x0054
#define ICH_FLASH_FREG1 0x0058 #define ICH8_FLASH_FREG1 0x0058
#define ICH_FLASH_FREG2 0x005C #define ICH8_FLASH_FREG2 0x005C
#define ICH_FLASH_FREG3 0x0060 #define ICH8_FLASH_FREG3 0x0060
#define ICH_FLASH_FPR0 0x0074 #define ICH8_FLASH_FPR0 0x0074
#define ICH_FLASH_FPR1 0x0078 #define ICH8_FLASH_FPR1 0x0078
#define ICH_FLASH_SSFSTS 0x0090 #define ICH8_FLASH_SSFSTS 0x0090
#define ICH_FLASH_SSFCTL 0x0092 #define ICH8_FLASH_SSFCTL 0x0092
#define ICH_FLASH_PREOP 0x0094 #define ICH8_FLASH_PREOP 0x0094
#define ICH_FLASH_OPTYPE 0x0096 #define ICH8_FLASH_OPTYPE 0x0096
#define ICH_FLASH_OPMENU 0x0098 #define ICH8_FLASH_OPMENU 0x0098
#define ICH_FLASH_REG_MAPSIZE 0x00A0 #define ICH8_FLASH_REG_MAPSIZE 0x00A0
#define ICH_FLASH_SECTOR_SIZE 4096 #define ICH8_FLASH_SECTOR_SIZE 4096
#define ICH_GFPREG_BASE_MASK 0x1FFF #define ICH8_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF #define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */ /* Offset 04h HSFSTS */
@ -3374,5 +3426,3 @@ union ich8_hws_flash_regacc {
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
#endif /* _EM_HW_H_ */ #endif /* _EM_HW_H_ */

100
sys/dev/em/if_em_osdep.h
View File

@ -37,27 +37,19 @@ POSSIBILITY OF SUCH DAMAGE.
#define _FREEBSD_OS_H_ #define _FREEBSD_OS_H_
#include <sys/types.h> #include <sys/types.h>
#include <sys/param.h>
#include <sys/systm.h> #include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/bus.h> #include <sys/bus.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/socket.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <sys/rman.h> #include <sys/rman.h>
#include <machine/resource.h> #include <machine/resource.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/clock.h>
#include <dev/pci/pcivar.h> #include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h> #include <dev/pci/pcireg.h>
#define ASSERT(x) if(!(x)) panic("EM: x")
/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
#define usec_delay(x) DELAY(x) #define usec_delay(x) DELAY(x)
#define msec_delay(x) DELAY(1000*(x)) #define msec_delay(x) DELAY(1000*(x))
/* TODO: Should we be paranoid about delaying in interrupt context? */ /* TODO: Should we be paranoid about delaying in interrupt context? */
@ -65,7 +57,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define MSGOUT(S, A, B) printf(S "\n", A, B) #define MSGOUT(S, A, B) printf(S "\n", A, B)
#define DEBUGFUNC(F) DEBUGOUT(F); #define DEBUGFUNC(F) DEBUGOUT(F);
#if DBG #ifdef DBG
#define DEBUGOUT(S) printf(S "\n") #define DEBUGOUT(S) printf(S "\n")
#define DEBUGOUT1(S,A) printf(S "\n",A) #define DEBUGOUT1(S,A) printf(S "\n",A)
#define DEBUGOUT2(S,A,B) printf(S "\n",A,B) #define DEBUGOUT2(S,A,B) printf(S "\n",A,B)
@ -92,80 +84,94 @@ struct em_osdep
bus_space_handle_t io_bus_space_handle; bus_space_handle_t io_bus_space_handle;
bus_space_tag_t flash_bus_space_tag; bus_space_tag_t flash_bus_space_tag;
bus_space_handle_t flash_bus_space_handle; bus_space_handle_t flash_bus_space_handle;
struct device *dev; device_t dev;
}; };
#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) #define E1000_WRITE_FLUSH(hw) E1000_READ_REG(hw, STATUS)
/* Read from an absolute offset in the adapter's memory space */ /* Read from an absolute offset in the adapter's memory space */
#define E1000_READ_OFFSET(hw, offset) \ #define E1000_READ_OFFSET(hw, offset) \
bus_space_read_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ bus_space_read_4( ((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, offset) ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, offset)
/* Write to an absolute offset in the adapter's memory space */ /* Write to an absolute offset in the adapter's memory space */
#define E1000_WRITE_OFFSET(hw, offset, value) \ #define E1000_WRITE_OFFSET(hw, offset, value) \
bus_space_write_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ bus_space_write_4( ((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, offset, value) ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, offset, value)
/* Convert a register name to its offset in the adapter's memory space */ /* Convert a register name to its offset in the adapter's memory space */
#define E1000_REG_OFFSET(hw, reg) \ #define E1000_REG_OFFSET(hw, reg) \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) ((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg)
/* Register READ/WRITE macros */ /*
* Register READ/WRITE macros.
*
* XXXGL: Due to define's namespace mangling in recent version of
* if_em_hw.*, we prepend "_" to the register name in all macros,
* to prevent reg from being substituted, and then, in E1000_REG_OFFSET()
* we prepend either "E1000" or "E1000_82542".
*
* P.S. The problematic defines are E1000_PHY_CTRL and PHY_CTRL.
*
* P.P.S. Intel has removed E1000_REG_OFFSET() and copy-pasted it to all
* macros.
*/
#define _E1000_REG_OFFSET(hw, reg) \
((hw)->mac_type >= em_82543 ? E1000##reg : E1000_82542##reg)
#define E1000_READ_REG(hw, reg) \ #define E1000_READ_REG(hw, reg) \
bus_space_read_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ E1000_READ_OFFSET(hw, _E1000_REG_OFFSET(hw, _##reg))
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg))
#define E1000_WRITE_REG(hw, reg, value) \ #define E1000_WRITE_REG(hw, reg, value) \
bus_space_write_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ E1000_WRITE_OFFSET(hw, _E1000_REG_OFFSET(hw, _##reg), value)
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg), \
value)
#define E1000_READ_REG_ARRAY(hw, reg, index) \ #define E1000_READ_REG_ARRAY(hw, reg, index) \
bus_space_read_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ E1000_READ_OFFSET(hw, _E1000_REG_OFFSET(hw, _##reg) + ((index) << 2))
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) \
+ ((index) << 2))
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
bus_space_write_4(((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg) \
+ ((index) << 2), value)
#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
E1000_WRITE_OFFSET(hw, _E1000_REG_OFFSET(hw, _##reg) + ((index) << 2), value)
#define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \ #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
bus_space_write_1( ((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ bus_space_write_1( ((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \ ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg \ _E1000_REG_OFFSET(hw, _##reg) + (index), \
+ index), value) value)
#define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \ #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
bus_space_write_2( ((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \ bus_space_write_2( ((struct em_osdep *)(hw)->back)->mem_bus_space_tag, \
((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \ ((struct em_osdep *)(hw)->back)->mem_bus_space_handle, \
((hw)->mac_type >= em_82543 ? E1000_##reg : E1000_82542_##reg \ _E1000_REG_OFFSET(hw, _##reg) + (index), \
+ (index << 1)), value) value)
#define E1000_READ_ICH_FLASH_REG(hw, reg) \ #define E1000_WRITE_REG_ARRAY_DWORD(hw, reg, index, value) \
E1000_WRITE_OFFSET(hw, _E1000_REG_OFFSET(hw, _##reg) + ((index) << 2), value)
#define E1000_READ_ICH8_REG(hw, reg) \
bus_space_read_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \ bus_space_read_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg) ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
#define E1000_READ_ICH_FLASH_REG16(hw, reg) \ #define E1000_READ_ICH8_REG16(hw, reg) \
bus_space_read_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \ bus_space_read_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg) ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg)
#define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \ #define E1000_WRITE_ICH8_REG(hw, reg, value) \
bus_space_write_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \ bus_space_write_4(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg, value) ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
#define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \ #define E1000_WRITE_ICH8_REG16(hw, reg, value) \
bus_space_write_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \ bus_space_write_2(((struct em_osdep *)(hw)->back)->flash_bus_space_tag, \
((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg, value) ((struct em_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
#define em_io_read(hw, port) \
bus_space_read_4(((struct em_osdep *)(hw)->back)->io_bus_space_tag, \
((struct em_osdep *)(hw)->back)->io_bus_space_handle, (port))
#define em_io_write(hw, port, value) \
bus_space_write_4(((struct em_osdep *)(hw)->back)->io_bus_space_tag, \
((struct em_osdep *)(hw)->back)->io_bus_space_handle, (port), \
(value))
#endif /* _FREEBSD_OS_H_ */ #endif /* _FREEBSD_OS_H_ */