From 4141a1b905a9472ce89f7d7ddd103276317d53e7 Mon Sep 17 00:00:00 2001 From: br Date: Sat, 19 Nov 2016 15:38:13 +0000 Subject: [PATCH] Add Ingenic XBurst coprocessor 0 extra bits. Submitted by: kan Sponsored by: DARPA, AFRL --- sys/mips/include/cpufunc.h | 7 +++++++ sys/mips/include/cpuregs.h | 8 +++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h index d891b17ba780..5ebaf4cc1720 100644 --- a/sys/mips/include/cpufunc.h +++ b/sys/mips/include/cpufunc.h @@ -279,6 +279,13 @@ MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); MIPS_RW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); +#ifdef CPU_XBURST +MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0); +MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1); +MIPS_RW32_COP0_SEL(xburst_core_ctl, MIPS_COP_0_XBURST_C12, 2); +MIPS_RW32_COP0_SEL(xburst_core_sts, MIPS_COP_0_XBURST_C12, 3); +MIPS_RW32_COP0_SEL(xburst_reim, MIPS_COP_0_XBURST_C12, 4); +#endif MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h index 4ce7e1b4fb2a..26bee195e648 100644 --- a/sys/mips/include/cpuregs.h +++ b/sys/mips/include/cpuregs.h @@ -522,12 +522,18 @@ #define MIPS_COP_0_COUNT _(9) #define MIPS_COP_0_COMPARE _(11) - +#ifdef CPU_XBURST +#define MIPS_COP_0_XBURST_C12 _(12) +#endif #define MIPS_COP_0_CONFIG _(16) #define MIPS_COP_0_LLADDR _(17) #define MIPS_COP_0_WATCH_LO _(18) #define MIPS_COP_0_WATCH_HI _(19) #define MIPS_COP_0_TLB_XCONTEXT _(20) +#ifdef CPU_XBURST +#define MIPS_COP_0_XBURST_MBOX _(20) +#endif + #define MIPS_COP_0_ECC _(26) #define MIPS_COP_0_CACHE_ERR _(27) #define MIPS_COP_0_TAG_LO _(28)