From 41e1215847cc839d99395c64d761c781f869dbad Mon Sep 17 00:00:00 2001 From: jhibbits Date: Wed, 22 May 2019 02:43:17 +0000 Subject: [PATCH] powerpc/booke: Use wrtee instead of msr to restore EE bit The MSR[EE] bit does not require synchronization when changing. This is a trivial micro-optimization, removing the trailing isync from mtmsr(). MFC after: 1 week --- sys/powerpc/booke/pmap.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sys/powerpc/booke/pmap.c b/sys/powerpc/booke/pmap.c index 009dff7d5af6..5448770b1787 100644 --- a/sys/powerpc/booke/pmap.c +++ b/sys/powerpc/booke/pmap.c @@ -3916,7 +3916,7 @@ tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) entry->mas7 = 0; break; } - mtmsr(msr); + __asm __volatile("wrtee %0" :: "r"(msr)); entry->virt = entry->mas2 & MAS2_EPN_MASK; entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | @@ -3991,7 +3991,7 @@ tlb1_write_entry(tlb_entry_t *e, unsigned int idx) msr = mfmsr(); __asm __volatile("wrteei 0"); tlb1_write_entry_int(&args); - mtmsr(msr); + __asm __volatile("wrtee %0" :: "r"(msr)); } } @@ -4390,7 +4390,7 @@ tid_flush(tlbtid_t tid) mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT); /* tlbilxpid */ __asm __volatile("isync; .long 0x7c000024; isync; msync"); - mtmsr(msr); + __asm __volatile("wrtee %0" :: "r"(msr)); return; } @@ -4415,7 +4415,7 @@ tid_flush(tlbtid_t tid) mtspr(SPR_MAS1, mas1); __asm __volatile("isync; tlbwe; isync; msync"); } - mtmsr(msr); + __asm __volatile("wrtee %0" :: "r"(msr)); } #ifdef DDB