Add some isync()s related to the 64-bit MMU scratch page to avoid race

conditions on its invalidation.

sys/powerpc/aim/mmu_oea64.c

@@ -1114,6 +1114,7 @@ void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
 	MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
 	    &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
 	    moea64_scratchpage_pvo[which]->pvo_vpn);
+	isync();
 }
 
 void

sys/powerpc/aim/moea64_native.c

@@ -292,6 +292,9 @@ moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
 
 	pvo_pt->pte_hi &= ~LPTE_VALID;
 
+	/* Finish all pending operations */
+	isync();
+
 	/*
 	 * Force the reg & chg bits back into the PTEs.
 	 */