Replace GPL'd headers in the emu10kx snd driver code.
This uses the emuxkireg.h already used in the emu10k1 snd driver. Special thanks go to Alexander Motin as he was able to find some errors and reverse engineer some wrong values in the emuxkireg header. The emu10kx driver is now free from the GPL. PR: 153901 Tested by: mav, joel Approved by: jhb (mentor) MFC after: 2 weeks
This commit is contained in:
pfg
parent
3c57775efe
commit
42fe35cfd7
@ -50,11 +50,6 @@ aic79xx_reg_print.c optional ahd pci \
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aic79xx_reg_print.o optional ahd pci ahd_reg_pretty_print \
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compile-with "${NORMAL_C}" \
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no-implicit-rule local
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emu10k1-alsa%diked.h optional snd_emu10kx \
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dependency "$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/emu10k1-alsa.h" \
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compile-with "CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/emu10k1-alsa.h emu10k1-alsa%diked.h" \
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no-obj no-implicit-rule before-depend \
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clean "emu10k1-alsa%diked.h"
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#
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# The 'fdt_dtb_file' target covers an actual DTB file name, which is derived
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# from the specified source (DTS) file: <platform>.dts -> <platform>.dtb
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@ -67,16 +62,6 @@ fdt_static_dtb.h optional fdt fdt_dtb_static \
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compile-with "sh $S/tools/fdt/make_dtbh.sh ${FDT_DTS_FILE} ." \
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no-obj no-implicit-rule before-depend \
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clean "fdt_static_dtb.h"
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p16v-alsa%diked.h optional snd_emu10kx pci \
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dependency "$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p16v-alsa.h" \
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compile-with "CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p16v-alsa.h p16v-alsa%diked.h" \
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no-obj no-implicit-rule before-depend \
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clean "p16v-alsa%diked.h"
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p17v-alsa%diked.h optional snd_emu10kx pci \
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dependency "$S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p17v-alsa.h" \
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compile-with "CC='${CC}' AWK=${AWK} sh $S/tools/sound/emu10k1-mkalsa.sh $S/gnu/dev/sound/pci/p17v-alsa.h p17v-alsa%diked.h" \
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no-obj no-implicit-rule before-depend \
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clean "p17v-alsa%diked.h"
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feeder_eq_gen.h optional sound \
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dependency "$S/tools/sound/feeder_eq_mkfilter.awk" \
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compile-with "${AWK} -f $S/tools/sound/feeder_eq_mkfilter.awk -- ${FEEDER_EQ_PRESETS} > feeder_eq_gen.h" \
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@ -1733,19 +1718,9 @@ dev/sound/pci/csa.c optional snd_csa pci \
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dev/sound/pci/csapcm.c optional snd_csa pci
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dev/sound/pci/ds1.c optional snd_ds1 pci
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dev/sound/pci/emu10k1.c optional snd_emu10k1 pci
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dev/sound/pci/emu10kx.c optional snd_emu10kx pci \
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dependency "emu10k1-alsa%diked.h" \
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dependency "p16v-alsa%diked.h" \
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dependency "p17v-alsa%diked.h" \
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warning "kernel contains GPL contaminated emu10kx headers"
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dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci \
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dependency "emu10k1-alsa%diked.h" \
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dependency "p16v-alsa%diked.h" \
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dependency "p17v-alsa%diked.h" \
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warning "kernel contains GPL contaminated emu10kx headers"
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dev/sound/pci/emu10kx-midi.c optional snd_emu10kx pci \
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dependency "emu10k1-alsa%diked.h" \
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warning "kernel contains GPL contaminated emu10kx headers"
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dev/sound/pci/emu10kx.c optional snd_emu10kx pci
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dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci
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dev/sound/pci/emu10kx-midi.c optional snd_emu10kx pci
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dev/sound/pci/envy24.c optional snd_envy24 pci
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dev/sound/pci/envy24ht.c optional snd_envy24ht pci
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dev/sound/pci/es137x.c optional snd_es137x pci
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@ -50,8 +50,8 @@
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#include <dev/sound/midi/mpu401.h>
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#include "mpufoi_if.h"
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#include <dev/sound/pci/emuxkireg.h>
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#include <dev/sound/pci/emu10kx.h>
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#include "emu10k1-alsa%diked.h"
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struct emu_midi_softc {
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struct mtx mtx;
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@ -176,25 +176,25 @@ emu_midi_attach(device_t dev)
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if (scp->is_emu10k1) {
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/* SB Live! - only one MIDI device here */
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inte_val = 0;
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/* inte_val |= INTE_MIDITXENABLE;*/
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inte_val |= INTE_MIDIRXENABLE;
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ipr_val = IPR_MIDITRANSBUFEMPTY;
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ipr_val |= IPR_MIDIRECVBUFEMPTY;
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/* inte_val |= EMU_INTE_MIDITXENABLE;*/
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inte_val |= EMU_INTE_MIDIRXENABLE;
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ipr_val = EMU_IPR_MIDITRANSBUFE;
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ipr_val |= EMU_IPR_MIDIRECVBUFE;
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} else {
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if (scp->port == A_MUDATA1) {
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if (scp->port == EMU_A_MUDATA1) {
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/* EXTERNAL MIDI (AudigyDrive) */
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inte_val = 0;
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/* inte_val |= A_INTE_MIDITXENABLE1;*/
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inte_val |= INTE_MIDIRXENABLE;
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ipr_val = IPR_MIDITRANSBUFEMPTY;
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ipr_val |= IPR_MIDIRECVBUFEMPTY;
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/* inte_val |= A_EMU_INTE_MIDITXENABLE1;*/
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inte_val |= EMU_INTE_MIDIRXENABLE;
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ipr_val = EMU_IPR_MIDITRANSBUFE;
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ipr_val |= EMU_IPR_MIDIRECVBUFE;
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} else {
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/* MIDI hw config port 2 */
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inte_val = 0;
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/* inte_val |= A_INTE_MIDITXENABLE2;*/
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inte_val |= INTE_A_MIDIRXENABLE2;
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ipr_val = IPR_A_MIDITRANSBUFEMPTY2;
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ipr_val |= IPR_A_MIDIRECVBUFEMPTY2;
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/* inte_val |= A_EMU_INTE_MIDITXENABLE2;*/
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inte_val |= EMU_INTE_A_MIDIRXENABLE2;
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ipr_val = EMU_IPR_A_MIDITRANSBUFE2;
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ipr_val |= EMU_IPR_A_MIDIRECBUFE2;
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}
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}
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@ -214,7 +214,7 @@ emu_midi_attach(device_t dev)
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if (scp->is_emu10k1)
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emu_enable_ir(scp->card);
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else {
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if (scp->port == A_MUDATA1)
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if (scp->port == EMU_A_MUDATA1)
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emu_enable_ir(scp->card);
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}
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@ -49,8 +49,8 @@
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#include "mixer_if.h"
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#include <dev/sound/pci/emuxkireg.h>
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#include <dev/sound/pci/emu10kx.h>
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#include "emu10k1-alsa%diked.h"
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struct emu_pcm_pchinfo {
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int spd;
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@ -555,8 +555,8 @@ emu_ac97_read_emulation(struct emu_pcm_info *sc, int regno)
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break;
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}
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emu_wr(sc->card, AC97ADDRESS, regno, 1);
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tmp = emu_rd(sc->card, AC97DATA, 2);
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emu_wr(sc->card, EMU_AC97ADDR, regno, 1);
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tmp = emu_rd(sc->card, EMU_AC97DATA, 2);
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if (use_ac97)
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emulated = tmp;
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@ -621,8 +621,8 @@ emu_ac97_write_emulation(struct emu_pcm_info *sc, int regno, uint32_t data)
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break;
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}
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if (write_ac97) {
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emu_wr(sc->card, AC97ADDRESS, regno, 1);
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emu_wr(sc->card, AC97DATA, data, 2);
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emu_wr(sc->card, EMU_AC97ADDR, regno, 1);
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emu_wr(sc->card, EMU_AC97DATA, data, 2);
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}
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}
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@ -658,8 +658,8 @@ emu_rdcd(kobj_t obj __unused, void *devinfo, int regno)
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struct emu_pcm_info *sc = (struct emu_pcm_info *)devinfo;
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KASSERT(sc->card != NULL, ("emu_rdcd: no soundcard"));
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emu_wr(sc->card, AC97ADDRESS, regno, 1);
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rd = emu_rd(sc->card, AC97DATA, 2);
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emu_wr(sc->card, EMU_AC97ADDR, regno, 1);
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rd = emu_rd(sc->card, EMU_AC97DATA, 2);
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return (rd);
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}
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@ -669,8 +669,8 @@ emu_wrcd(kobj_t obj __unused, void *devinfo, int regno, uint32_t data)
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struct emu_pcm_info *sc = (struct emu_pcm_info *)devinfo;
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KASSERT(sc->card != NULL, ("emu_wrcd: no soundcard"));
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emu_wr(sc->card, AC97ADDRESS, regno, 1);
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emu_wr(sc->card, AC97DATA, data, 2);
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emu_wr(sc->card, EMU_AC97ADDR, regno, 1);
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emu_wr(sc->card, EMU_AC97DATA, data, 2);
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return (0);
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}
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@ -870,12 +870,12 @@ emurchan_init(kobj_t obj __unused, void *devinfo, struct snd_dbuf *b, struct pcm
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ch->blksz = sc->bufsz / 2; /* We rise interrupt for half-full buffer */
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ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
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ch->spd = 8000;
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ch->idxreg = sc->is_emu10k1 ? ADCIDX : A_ADCIDX;
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ch->basereg = ADCBA;
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ch->sizereg = ADCBS;
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ch->setupreg = ADCCR;
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ch->irqmask = INTE_ADCBUFENABLE;
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ch->iprmask = IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL;
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ch->idxreg = sc->is_emu10k1 ? EMU_ADCIDX : EMU_A_ADCIDX;
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ch->basereg = EMU_ADCBA;
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ch->sizereg = EMU_ADCBS;
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ch->setupreg = EMU_ADCCR;
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ch->irqmask = EMU_INTE_ADCBUFENABLE;
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ch->iprmask = EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL;
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if (sndbuf_alloc(ch->buffer, emu_gettag(sc->card), 0, sc->bufsz) != 0)
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return (NULL);
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@ -953,22 +953,22 @@ emurchan_trigger(kobj_t obj __unused, void *c_devinfo, int go)
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switch (sc->bufsz) {
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case 4096:
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sz = ADCBS_BUFSIZE_4096;
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sz = EMU_RECBS_BUFSIZE_4096;
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break;
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case 8192:
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sz = ADCBS_BUFSIZE_8192;
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sz = EMU_RECBS_BUFSIZE_8192;
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break;
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case 16384:
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sz = ADCBS_BUFSIZE_16384;
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sz = EMU_RECBS_BUFSIZE_16384;
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break;
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case 32768:
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sz = ADCBS_BUFSIZE_32768;
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sz = EMU_RECBS_BUFSIZE_32768;
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break;
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case 65536:
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sz = ADCBS_BUFSIZE_65536;
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sz = EMU_RECBS_BUFSIZE_65536;
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break;
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default:
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sz = ADCBS_BUFSIZE_4096;
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sz = EMU_RECBS_BUFSIZE_4096;
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}
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snd_mtxlock(sc->lock);
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@ -976,9 +976,9 @@ emurchan_trigger(kobj_t obj __unused, void *c_devinfo, int go)
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case PCMTRIG_START:
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ch->run = 1;
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emu_wrptr(sc->card, 0, ch->sizereg, sz);
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val = sc->is_emu10k1 ? ADCCR_LCHANENABLE : A_ADCCR_LCHANENABLE;
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val = sc->is_emu10k1 ? EMU_ADCCR_LCHANENABLE : EMU_A_ADCCR_LCHANENABLE;
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if (AFMT_CHANNEL(ch->fmt) > 1)
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val |= sc->is_emu10k1 ? ADCCR_RCHANENABLE : A_ADCCR_RCHANENABLE;
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val |= sc->is_emu10k1 ? EMU_ADCCR_RCHANENABLE : EMU_A_ADCCR_RCHANENABLE;
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val |= sc->is_emu10k1 ? emu_k1_recval(ch->spd) : emu_k2_recval(ch->spd);
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emu_wrptr(sc->card, 0, ch->setupreg, 0);
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emu_wrptr(sc->card, 0, ch->setupreg, val);
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@ -1049,11 +1049,11 @@ emufxrchan_init(kobj_t obj __unused, void *devinfo, struct snd_dbuf *b, struct p
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ch = &(sc->rch_efx);
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ch->fmt = SND_FORMAT(AFMT_S16_LE, 1, 0);
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ch->spd = sc->is_emu10k1 ? 48000*32 : 48000 * 64;
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ch->idxreg = FXIDX;
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ch->basereg = FXBA;
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ch->sizereg = FXBS;
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ch->irqmask = INTE_EFXBUFENABLE;
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ch->iprmask = IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL;
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ch->idxreg = EMU_FXIDX;
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ch->basereg = EMU_FXBA;
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ch->sizereg = EMU_FXBS;
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ch->irqmask = EMU_INTE_EFXBUFENABLE;
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ch->iprmask = EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL;
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ch->buffer = b;
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ch->pcm = sc;
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ch->channel = c;
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@ -1113,22 +1113,22 @@ emufxrchan_trigger(kobj_t obj __unused, void *c_devinfo, int go)
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switch (sc->bufsz) {
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case 4096:
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sz = ADCBS_BUFSIZE_4096;
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sz = EMU_RECBS_BUFSIZE_4096;
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break;
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case 8192:
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sz = ADCBS_BUFSIZE_8192;
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sz = EMU_RECBS_BUFSIZE_8192;
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break;
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case 16384:
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sz = ADCBS_BUFSIZE_16384;
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sz = EMU_RECBS_BUFSIZE_16384;
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break;
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case 32768:
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sz = ADCBS_BUFSIZE_32768;
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sz = EMU_RECBS_BUFSIZE_32768;
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break;
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case 65536:
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sz = ADCBS_BUFSIZE_65536;
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sz = EMU_RECBS_BUFSIZE_65536;
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break;
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default:
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sz = ADCBS_BUFSIZE_4096;
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sz = EMU_RECBS_BUFSIZE_4096;
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}
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snd_mtxlock(sc->lock);
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@ -1140,14 +1140,14 @@ emufxrchan_trigger(kobj_t obj __unused, void *c_devinfo, int go)
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/*
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* SB Live! is limited to 32 mono channels. Audigy
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* has 64 mono channels. Channels are enabled
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* by setting a bit in A_FXWC[1|2] registers.
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* by setting a bit in EMU_A_FXWC[1|2] registers.
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*/
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/* XXX there is no way to demultiplex this streams for now */
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if (sc->is_emu10k1) {
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emu_wrptr(sc->card, 0, FXWC, 0xffffffff);
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emu_wrptr(sc->card, 0, EMU_FXWC, 0xffffffff);
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} else {
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emu_wrptr(sc->card, 0, A_FXWC1, 0xffffffff);
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emu_wrptr(sc->card, 0, A_FXWC2, 0xffffffff);
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emu_wrptr(sc->card, 0, EMU_A_FXWC1, 0xffffffff);
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emu_wrptr(sc->card, 0, EMU_A_FXWC2, 0xffffffff);
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}
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break;
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case PCMTRIG_STOP:
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@ -1155,10 +1155,10 @@ emufxrchan_trigger(kobj_t obj __unused, void *c_devinfo, int go)
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case PCMTRIG_ABORT:
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ch->run = 0;
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if (sc->is_emu10k1) {
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emu_wrptr(sc->card, 0, FXWC, 0x0);
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emu_wrptr(sc->card, 0, EMU_FXWC, 0x0);
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} else {
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emu_wrptr(sc->card, 0, A_FXWC1, 0x0);
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emu_wrptr(sc->card, 0, A_FXWC2, 0x0);
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emu_wrptr(sc->card, 0, EMU_A_FXWC1, 0x0);
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emu_wrptr(sc->card, 0, EMU_A_FXWC2, 0x0);
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}
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emu_wrptr(sc->card, 0, ch->sizereg, 0);
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(void)emu_intr_unregister(sc->card, ch->ihandle);
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@ -1238,8 +1238,8 @@ emu_pcm_intr(void *pcm, uint32_t stat)
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snd_mtxlock(sc->lock);
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if (stat & IPR_INTERVALTIMER) {
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ack |= IPR_INTERVALTIMER;
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if (stat & EMU_IPR_INTERVALTIMER) {
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ack |= EMU_IPR_INTERVALTIMER;
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for (i = 0; i < MAX_CHANNELS; i++)
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if (sc->pch[i].channel) {
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if (sc->pch[i].run == 1) {
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@ -1262,8 +1262,8 @@ emu_pcm_intr(void *pcm, uint32_t stat)
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}
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if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) {
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ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL);
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if (stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL)) {
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ack |= stat & (EMU_IPR_ADCBUFFULL | EMU_IPR_ADCBUFHALFFULL);
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if (sc->rch_adc.channel) {
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snd_mtxunlock(sc->lock);
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chn_intr(sc->rch_adc.channel);
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@ -1271,8 +1271,8 @@ emu_pcm_intr(void *pcm, uint32_t stat)
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}
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}
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if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) {
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ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL);
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if (stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL)) {
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ack |= stat & (EMU_IPR_EFXBUFFULL | EMU_IPR_EFXBUFHALFFULL);
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if (sc->rch_efx.channel) {
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snd_mtxunlock(sc->lock);
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chn_intr(sc->rch_efx.channel);
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@ -1450,8 +1450,8 @@ emu_pcm_attach(device_t dev)
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goto bad;
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}
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inte = INTE_INTERVALTIMERENB;
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ipr = IPR_INTERVALTIMER; /* Used by playback & ADC */
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inte = EMU_INTE_INTERTIMERENB;
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ipr = EMU_IPR_INTERVALTIMER; /* Used by playback & ADC */
|
||||
sc->ihandle = emu_intr_register(sc->card, inte, ipr, &emu_pcm_intr, sc);
|
||||
|
||||
if (emu_pcm_init(sc) == -1) {
|
||||
|
||||
@ -53,6 +53,7 @@
|
||||
#include <dev/sound/pcm/sound.h>
|
||||
#include <dev/sound/pcm/ac97.h>
|
||||
|
||||
#include <dev/sound/pci/emuxkireg.h>
|
||||
#include <dev/sound/pci/emu10kx.h>
|
||||
|
||||
/* hw flags */
|
||||
@ -181,7 +182,7 @@
|
||||
#define A_IN_AUX2_R 0x0d
|
||||
#define A_IN_AUX2 A_IN_AUX2_L
|
||||
|
||||
/* Audigiy Outputs */
|
||||
/* Audigy Outputs */
|
||||
#define A_OUT_D_FRONT_L 0x00
|
||||
#define A_OUT_D_FRONT_R 0x01
|
||||
#define A_OUT_D_FRONT A_OUT_D_FRONT_L
|
||||
@ -217,9 +218,19 @@
|
||||
#define A_OUT_ADC_REC_R 0x17
|
||||
#define A_OUT_ADC_REC A_OUT_ADC_REC_L
|
||||
|
||||
#include "emu10k1-alsa%diked.h"
|
||||
#include "p16v-alsa%diked.h"
|
||||
#include "p17v-alsa%diked.h"
|
||||
#define EMU_DATA2 0x24
|
||||
#define EMU_IPR2 0x28
|
||||
#define EMU_INTE2 0x2c
|
||||
#define EMU_IPR3 0x38
|
||||
#define EMU_INTE3 0x3c
|
||||
|
||||
#define EMU_A2_SRCSel 0x60
|
||||
#define EMU_A2_SRCMULTI_ENABLE 0x6e
|
||||
|
||||
#define EMU_A_I2S_CAPTURE_96000 0x00000400
|
||||
|
||||
#define EMU_A2_MIXER_I2S_ENABLE 0x7B
|
||||
#define EMU_A2_MIXER_SPDIF_ENABLE 0x7A
|
||||
|
||||
#define C_FRONT_L 0
|
||||
#define C_FRONT_R 1
|
||||
@ -630,7 +641,7 @@ emu_wr_nolock(struct emu_sc_info *sc, unsigned int regno, uint32_t data, unsigne
|
||||
}
|
||||
}
|
||||
/*
|
||||
* PTR / DATA interface. Access to EMU10Kx is made
|
||||
* EMU_PTR / EMU_DATA interface. Access to EMU10Kx is made
|
||||
* via (channel, register) pair. Some registers are channel-specific,
|
||||
* some not.
|
||||
*/
|
||||
@ -639,11 +650,11 @@ emu_rdptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg)
|
||||
{
|
||||
uint32_t ptr, val, mask, size, offset;
|
||||
|
||||
ptr = ((reg << 16) & sc->address_mask) | (chn & PTR_CHANNELNUM_MASK);
|
||||
ptr = ((reg << 16) & sc->address_mask) | (chn & EMU_PTR_CHNO_MASK);
|
||||
|
||||
EMU_RWLOCK();
|
||||
emu_wr_nolock(sc, PTR, ptr, 4);
|
||||
val = emu_rd_nolock(sc, DATA, 4);
|
||||
emu_wr_nolock(sc, EMU_PTR, ptr, 4);
|
||||
val = emu_rd_nolock(sc, EMU_DATA, 4);
|
||||
EMU_RWUNLOCK();
|
||||
|
||||
/*
|
||||
@ -666,10 +677,10 @@ emu_wrptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg, uint32_t d
|
||||
{
|
||||
uint32_t ptr, mask, size, offset;
|
||||
|
||||
ptr = ((reg << 16) & sc->address_mask) | (chn & PTR_CHANNELNUM_MASK);
|
||||
ptr = ((reg << 16) & sc->address_mask) | (chn & EMU_PTR_CHNO_MASK);
|
||||
|
||||
EMU_RWLOCK();
|
||||
emu_wr_nolock(sc, PTR, ptr, 4);
|
||||
emu_wr_nolock(sc, EMU_PTR, ptr, 4);
|
||||
/*
|
||||
* XXX Another kind of magic encoding in register number. This can
|
||||
* give you side effect - it will read previous data from register
|
||||
@ -681,13 +692,13 @@ emu_wrptr(struct emu_sc_info *sc, unsigned int chn, unsigned int reg, uint32_t d
|
||||
mask = ((1 << size) - 1) << offset;
|
||||
data <<= offset;
|
||||
data &= mask;
|
||||
data |= emu_rd_nolock(sc, DATA, 4) & ~mask;
|
||||
data |= emu_rd_nolock(sc, EMU_DATA, 4) & ~mask;
|
||||
}
|
||||
emu_wr_nolock(sc, DATA, data, 4);
|
||||
emu_wr_nolock(sc, EMU_DATA, data, 4);
|
||||
EMU_RWUNLOCK();
|
||||
}
|
||||
/*
|
||||
* PTR2 / DATA2 interface. Access to P16v is made
|
||||
* EMU_A2_PTR / EMU_DATA2 interface. Access to P16v is made
|
||||
* via (channel, register) pair. Some registers are channel-specific,
|
||||
* some not. This interface is supported by CA0102 and CA0108 chips only.
|
||||
*/
|
||||
@ -698,8 +709,8 @@ emu_rd_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg)
|
||||
|
||||
/* XXX separate lock? */
|
||||
EMU_RWLOCK();
|
||||
emu_wr_nolock(sc, PTR2, (reg << 16) | chn, 4);
|
||||
val = emu_rd_nolock(sc, DATA2, 4);
|
||||
emu_wr_nolock(sc, EMU_A2_PTR, (reg << 16) | chn, 4);
|
||||
val = emu_rd_nolock(sc, EMU_DATA2, 4);
|
||||
|
||||
EMU_RWUNLOCK();
|
||||
|
||||
@ -711,8 +722,8 @@ emu_wr_p16vptr(struct emu_sc_info *sc, uint16_t chn, uint16_t reg, uint32_t data
|
||||
{
|
||||
|
||||
EMU_RWLOCK();
|
||||
emu_wr_nolock(sc, PTR2, (reg << 16) | chn, 4);
|
||||
emu_wr_nolock(sc, DATA2, data, 4);
|
||||
emu_wr_nolock(sc, EMU_A2_PTR, (reg << 16) | chn, 4);
|
||||
emu_wr_nolock(sc, EMU_DATA2, data, 4);
|
||||
EMU_RWUNLOCK();
|
||||
}
|
||||
/*
|
||||
@ -737,13 +748,13 @@ emu_wr_cbptr(struct emu_sc_info *sc, uint32_t data)
|
||||
|
||||
/*
|
||||
* Direct hardware register access
|
||||
* Assume that it is never used to access PTR-based registers and can run unlocked.
|
||||
* Assume that it is never used to access EMU_PTR-based registers and can run unlocked.
|
||||
*/
|
||||
void
|
||||
emu_wr(struct emu_sc_info *sc, unsigned int regno, uint32_t data, unsigned int size)
|
||||
{
|
||||
KASSERT(regno != PTR, ("emu_wr: attempt to write to PTR"));
|
||||
KASSERT(regno != PTR2, ("emu_wr: attempt to write to PTR2"));
|
||||
KASSERT(regno != EMU_PTR, ("emu_wr: attempt to write to EMU_PTR"));
|
||||
KASSERT(regno != EMU_A2_PTR, ("emu_wr: attempt to write to EMU_A2_PTR"));
|
||||
|
||||
emu_wr_nolock(sc, regno, data, size);
|
||||
}
|
||||
@ -753,8 +764,8 @@ emu_rd(struct emu_sc_info *sc, unsigned int regno, unsigned int size)
|
||||
{
|
||||
uint32_t rd;
|
||||
|
||||
KASSERT(regno != DATA, ("emu_rd: attempt to read DATA"));
|
||||
KASSERT(regno != DATA2, ("emu_rd: attempt to read DATA2"));
|
||||
KASSERT(regno != EMU_DATA, ("emu_rd: attempt to read DATA"));
|
||||
KASSERT(regno != EMU_DATA2, ("emu_rd: attempt to read DATA2"));
|
||||
|
||||
rd = emu_rd_nolock(sc, regno, size);
|
||||
return (rd);
|
||||
@ -770,24 +781,24 @@ emu_enable_ir(struct emu_sc_info *sc)
|
||||
uint32_t iocfg;
|
||||
|
||||
if (sc->is_emu10k2 || sc->is_ca0102) {
|
||||
iocfg = emu_rd_nolock(sc, A_IOCFG, 2);
|
||||
emu_wr_nolock(sc, A_IOCFG, iocfg | A_IOCFG_GPOUT2, 2);
|
||||
iocfg = emu_rd_nolock(sc, EMU_A_IOCFG, 2);
|
||||
emu_wr_nolock(sc, EMU_A_IOCFG, iocfg | EMU_A_IOCFG_GPOUT2, 2);
|
||||
DELAY(500);
|
||||
emu_wr_nolock(sc, A_IOCFG, iocfg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, 2);
|
||||
emu_wr_nolock(sc, EMU_A_IOCFG, iocfg | EMU_A_IOCFG_GPOUT1 | EMU_A_IOCFG_GPOUT2, 2);
|
||||
DELAY(500);
|
||||
emu_wr_nolock(sc, A_IOCFG, iocfg | A_IOCFG_GPOUT1, 2);
|
||||
emu_wr_nolock(sc, EMU_A_IOCFG, iocfg | EMU_A_IOCFG_GPOUT1, 2);
|
||||
DELAY(100);
|
||||
emu_wr_nolock(sc, A_IOCFG, iocfg, 2);
|
||||
emu_wr_nolock(sc, EMU_A_IOCFG, iocfg, 2);
|
||||
device_printf(sc->dev, "Audigy IR MIDI events enabled.\n");
|
||||
sc->enable_ir = 1;
|
||||
}
|
||||
if (sc->is_emu10k1) {
|
||||
iocfg = emu_rd_nolock(sc, HCFG, 4);
|
||||
emu_wr_nolock(sc, HCFG, iocfg | HCFG_GPOUT2, 4);
|
||||
iocfg = emu_rd_nolock(sc, EMU_HCFG, 4);
|
||||
emu_wr_nolock(sc, EMU_HCFG, iocfg | EMU_HCFG_GPOUT2, 4);
|
||||
DELAY(500);
|
||||
emu_wr_nolock(sc, HCFG, iocfg | HCFG_GPOUT1 | HCFG_GPOUT2, 4);
|
||||
emu_wr_nolock(sc, EMU_HCFG, iocfg | EMU_HCFG_GPOUT1 | EMU_HCFG_GPOUT2, 4);
|
||||
DELAY(100);
|
||||
emu_wr_nolock(sc, HCFG, iocfg, 4);
|
||||
emu_wr_nolock(sc, EMU_HCFG, iocfg, 4);
|
||||
device_printf(sc->dev, "SB Live! IR MIDI events enabled.\n");
|
||||
sc->enable_ir = 1;
|
||||
}
|
||||
@ -835,7 +846,7 @@ emu_timer_set(struct emu_sc_info *sc, int timer, int delay)
|
||||
sc->timerinterval = sc->timer[i];
|
||||
|
||||
/* XXX */
|
||||
emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
|
||||
emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2);
|
||||
mtx_unlock(&sc->lock);
|
||||
|
||||
return (timer);
|
||||
@ -868,16 +879,16 @@ emu_timer_enable(struct emu_sc_info *sc, int timer, int go)
|
||||
ena_int = 1;
|
||||
}
|
||||
|
||||
emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
|
||||
emu_wr(sc, EMU_TIMER, sc->timerinterval & 0x03ff, 2);
|
||||
|
||||
if (ena_int == 1) {
|
||||
x = emu_rd(sc, INTE, 4);
|
||||
x |= INTE_INTERVALTIMERENB;
|
||||
emu_wr(sc, INTE, x, 4);
|
||||
x = emu_rd(sc, EMU_INTE, 4);
|
||||
x |= EMU_INTE_INTERTIMERENB;
|
||||
emu_wr(sc, EMU_INTE, x, 4);
|
||||
} else {
|
||||
x = emu_rd(sc, INTE, 4);
|
||||
x &= ~INTE_INTERVALTIMERENB;
|
||||
emu_wr(sc, INTE, x, 4);
|
||||
x = emu_rd(sc, EMU_INTE, 4);
|
||||
x &= ~EMU_INTE_INTERTIMERENB;
|
||||
emu_wr(sc, EMU_INTE, x, 4);
|
||||
}
|
||||
mtx_unlock(&sc->lock);
|
||||
return (0);
|
||||
@ -917,9 +928,9 @@ emu_intr_register(struct emu_sc_info *sc, uint32_t inte_mask, uint32_t intr_mask
|
||||
sc->ihandler[i].intr_mask = intr_mask;
|
||||
sc->ihandler[i].softc = isc;
|
||||
sc->ihandler[i].irq_func = func;
|
||||
x = emu_rd(sc, INTE, 4);
|
||||
x = emu_rd(sc, EMU_INTE, 4);
|
||||
x |= inte_mask;
|
||||
emu_wr(sc, INTE, x, 4);
|
||||
emu_wr(sc, EMU_INTE, x, 4);
|
||||
mtx_unlock(&sc->lock);
|
||||
if (sc->dbg_level > 1)
|
||||
device_printf(sc->dev, "ihandle %d registered\n", i);
|
||||
@ -946,7 +957,7 @@ emu_intr_unregister(struct emu_sc_info *sc, int hnumber)
|
||||
return (-1);
|
||||
}
|
||||
|
||||
x = emu_rd(sc, INTE, 4);
|
||||
x = emu_rd(sc, EMU_INTE, 4);
|
||||
x &= ~sc->ihandler[hnumber].inte_mask;
|
||||
|
||||
sc->ihandler[hnumber].inte_mask = 0;
|
||||
@ -954,12 +965,12 @@ emu_intr_unregister(struct emu_sc_info *sc, int hnumber)
|
||||
sc->ihandler[hnumber].softc = NULL;
|
||||
sc->ihandler[hnumber].irq_func = NULL;
|
||||
|
||||
/* other interrupt handlers may use this INTE value */
|
||||
/* other interrupt handlers may use this EMU_INTE value */
|
||||
for (i = 0; i < EMU_MAX_IRQ_CONSUMERS; i++)
|
||||
if (sc->ihandler[i].inte_mask != 0)
|
||||
x |= sc->ihandler[i].inte_mask;
|
||||
|
||||
emu_wr(sc, INTE, x, 4);
|
||||
emu_wr(sc, EMU_INTE, x, 4);
|
||||
|
||||
mtx_unlock(&sc->lock);
|
||||
return (hnumber);
|
||||
@ -973,11 +984,11 @@ emu_intr(void *p)
|
||||
int i;
|
||||
|
||||
for (;;) {
|
||||
stat = emu_rd(sc, IPR, 4);
|
||||
stat = emu_rd(sc, EMU_IPR, 4);
|
||||
ack = 0;
|
||||
if (stat == 0)
|
||||
break;
|
||||
emu_wr(sc, IPR, stat, 4);
|
||||
emu_wr(sc, EMU_IPR, stat, 4);
|
||||
for (i = 0; i < EMU_MAX_IRQ_CONSUMERS; i++) {
|
||||
if ((((sc->ihandler[i].intr_mask) & stat) != 0) &&
|
||||
(((void *)sc->ihandler[i].irq_func) != NULL)) {
|
||||
@ -993,13 +1004,13 @@ emu_intr(void *p)
|
||||
|
||||
if ((sc->is_ca0102) || (sc->is_ca0108))
|
||||
for (;;) {
|
||||
stat = emu_rd(sc, IPR2, 4);
|
||||
stat = emu_rd(sc, EMU_IPR2, 4);
|
||||
ack = 0;
|
||||
if (stat == 0)
|
||||
break;
|
||||
emu_wr(sc, IPR2, stat, 4);
|
||||
emu_wr(sc, EMU_IPR2, stat, 4);
|
||||
if (sc->dbg_level > 1)
|
||||
device_printf(sc->dev, "IPR2: %08x\n", stat);
|
||||
device_printf(sc->dev, "EMU_IPR2: %08x\n", stat);
|
||||
|
||||
break; /* to avoid infinite loop. shoud be removed
|
||||
* after completion of P16V interface. */
|
||||
@ -1007,13 +1018,13 @@ emu_intr(void *p)
|
||||
|
||||
if (sc->is_ca0102)
|
||||
for (;;) {
|
||||
stat = emu_rd(sc, IPR3, 4);
|
||||
stat = emu_rd(sc, EMU_IPR3, 4);
|
||||
ack = 0;
|
||||
if (stat == 0)
|
||||
break;
|
||||
emu_wr(sc, IPR3, stat, 4);
|
||||
emu_wr(sc, EMU_IPR3, stat, 4);
|
||||
if (sc->dbg_level > 1)
|
||||
device_printf(sc->dev, "IPR3: %08x\n", stat);
|
||||
device_printf(sc->dev, "EMU_IPR3: %08x\n", stat);
|
||||
|
||||
break; /* to avoid infinite loop. should be removed
|
||||
* after completion of S/PDIF interface */
|
||||
@ -1374,61 +1385,61 @@ emu_vwrite(struct emu_sc_info *sc, struct emu_voice *v)
|
||||
|
||||
|
||||
if (v->stereo) {
|
||||
emu_wrptr(sc, v->vnum, CPF, CPF_STEREO_MASK);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, EMU_CHAN_CPF_STEREO_MASK);
|
||||
} else {
|
||||
emu_wrptr(sc, v->vnum, CPF, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CPF, 0);
|
||||
}
|
||||
val = v->stereo ? 28 : 30;
|
||||
val *= v->b16 ? 1 : 2;
|
||||
start = v->sa + val;
|
||||
|
||||
if (sc->is_emu10k1) {
|
||||
emu_wrptr(sc, v->vnum, FXRT, ((v->routing[3] << 12) |
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_FXRT, ((v->routing[3] << 12) |
|
||||
(v->routing[2] << 8) |
|
||||
(v->routing[1] << 4) |
|
||||
(v->routing[0] << 0)) << 16);
|
||||
} else {
|
||||
emu_wrptr(sc, v->vnum, A_FXRT1, (v->routing[3] << 24) |
|
||||
emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT1, (v->routing[3] << 24) |
|
||||
(v->routing[2] << 16) |
|
||||
(v->routing[1] << 8) |
|
||||
(v->routing[0] << 0));
|
||||
emu_wrptr(sc, v->vnum, A_FXRT2, (v->routing[7] << 24) |
|
||||
emu_wrptr(sc, v->vnum, EMU_A_CHAN_FXRT2, (v->routing[7] << 24) |
|
||||
(v->routing[6] << 16) |
|
||||
(v->routing[5] << 8) |
|
||||
(v->routing[4] << 0));
|
||||
emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, (v->amounts[7] << 24) |
|
||||
emu_wrptr(sc, v->vnum, EMU_A_CHAN_SENDAMOUNTS, (v->amounts[7] << 24) |
|
||||
(v->amounts[6] << 26) |
|
||||
(v->amounts[5] << 8) |
|
||||
(v->amounts[4] << 0));
|
||||
}
|
||||
emu_wrptr(sc, v->vnum, PTRX, (v->amounts[0] << 8) | (v->amounts[1] << 0));
|
||||
emu_wrptr(sc, v->vnum, DSL, v->ea | (v->amounts[3] << 24));
|
||||
emu_wrptr(sc, v->vnum, PSST, v->sa | (v->amounts[2] << 24));
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX, (v->amounts[0] << 8) | (v->amounts[1] << 0));
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_DSL, v->ea | (v->amounts[3] << 24));
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_PSST, v->sa | (v->amounts[2] << 24));
|
||||
|
||||
emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT));
|
||||
emu_wrptr(sc, v->vnum, Z1, 0);
|
||||
emu_wrptr(sc, v->vnum, Z2, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CCCA, start | (v->b16 ? 0 : EMU_CHAN_CCCA_8BITSELECT));
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_Z1, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_Z2, 0);
|
||||
|
||||
silent_page = ((uint32_t) (sc->mem.silent_page_addr) << 1) | MAP_PTI_MASK;
|
||||
emu_wrptr(sc, v->vnum, MAPA, silent_page);
|
||||
emu_wrptr(sc, v->vnum, MAPB, silent_page);
|
||||
silent_page = ((uint32_t) (sc->mem.silent_page_addr) << 1) | EMU_CHAN_MAP_PTI_MASK;
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_MAPA, silent_page);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_MAPB, silent_page);
|
||||
|
||||
emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK);
|
||||
emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK);
|
||||
emu_wrptr(sc, v->vnum, ATKHLDM, 0);
|
||||
emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK);
|
||||
emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000);
|
||||
emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000);
|
||||
emu_wrptr(sc, v->vnum, FMMOD, 0);
|
||||
emu_wrptr(sc, v->vnum, TREMFRQ, 0);
|
||||
emu_wrptr(sc, v->vnum, FM2FRQ2, 0);
|
||||
emu_wrptr(sc, v->vnum, ENVVAL, 0x8000);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, EMU_CHAN_CVCF_CURRFILTER_MASK);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, EMU_CHAN_VTFT_FILTERTARGET_MASK);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDM, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSM, EMU_CHAN_DCYSUSM_DECAYTIME_MASK);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL1, 0x8000);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_LFOVAL2, 0x8000);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_FMMOD, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_TREMFRQ, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_FM2FRQ2, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVAL, 0x8000);
|
||||
|
||||
emu_wrptr(sc, v->vnum, ATKHLDV, ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK);
|
||||
emu_wrptr(sc, v->vnum, ENVVOL, 0x8000);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_ATKHLDV, EMU_CHAN_ATKHLDV_HOLDTIME_MASK | EMU_CHAN_ATKHLDV_ATTACKTIME_MASK);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_ENVVOL, 0x8000);
|
||||
|
||||
emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f);
|
||||
emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_FILTERAMOUNT, 0x7f);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_PEFE_PITCHAMOUNT, 0);
|
||||
if ((v->stereo) && (v->slave != NULL))
|
||||
emu_vwrite(sc, v->slave);
|
||||
}
|
||||
@ -1438,7 +1449,7 @@ emu_vstop(struct emu_sc_info *sc, char channel, int enable)
|
||||
{
|
||||
int reg;
|
||||
|
||||
reg = (channel & 0x20) ? SOLEH : SOLEL;
|
||||
reg = (channel & 0x20) ? EMU_SOLEH : EMU_SOLEL;
|
||||
channel &= 0x1f;
|
||||
reg |= 1 << 24;
|
||||
reg |= channel << 16;
|
||||
@ -1459,29 +1470,29 @@ emu_vtrigger(struct emu_sc_info *sc, struct emu_voice *v, int go)
|
||||
ccis *= v->b16 ? 1 : 2;
|
||||
sample = v->b16 ? 0x00000000 : 0x80808080;
|
||||
for (i = 0; i < cs; i++)
|
||||
emu_wrptr(sc, v->vnum, CD0 + i, sample);
|
||||
emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0);
|
||||
emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra);
|
||||
emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CD0 + i, sample);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_READADDRESS, cra);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CCR_CACHEINVALIDSIZE, ccis);
|
||||
|
||||
emu_wrptr(sc, v->vnum, IFATN, 0xff00);
|
||||
emu_wrptr(sc, v->vnum, VTFT, 0xffffffff);
|
||||
emu_wrptr(sc, v->vnum, CVCF, 0xffffffff);
|
||||
emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xff00);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0xffffffff);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0xffffffff);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_DCYSUSV, 0x00007f7f);
|
||||
emu_vstop(sc, v->vnum, 0);
|
||||
|
||||
pitch_target = emu_rate_to_linearpitch(v->speed);
|
||||
initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
|
||||
emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target);
|
||||
emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target);
|
||||
emu_wrptr(sc, v->vnum, IP, initial_pitch);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, pitch_target);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, pitch_target);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_IP, initial_pitch);
|
||||
} else {
|
||||
emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0);
|
||||
emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0);
|
||||
emu_wrptr(sc, v->vnum, IFATN, 0xffff);
|
||||
emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff);
|
||||
emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff);
|
||||
emu_wrptr(sc, v->vnum, IP, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_PTRX_PITCHTARGET, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CPF_PITCH, 0);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_IFATN, 0xffff);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_VTFT, 0x0000ffff);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_CVCF, 0x0000ffff);
|
||||
emu_wrptr(sc, v->vnum, EMU_CHAN_IP, 0);
|
||||
emu_vstop(sc, v->vnum, 1);
|
||||
}
|
||||
if ((v->stereo) && (v->slave != NULL))
|
||||
@ -1494,7 +1505,7 @@ emu_vpos(struct emu_sc_info *sc, struct emu_voice *v)
|
||||
int s, ptr;
|
||||
|
||||
s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
|
||||
ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s;
|
||||
ptr = (emu_rdptr(sc, v->vnum, EMU_CHAN_CCCA_CURRADDR) - (v->start >> s)) << s;
|
||||
return (ptr & ~0x0000001f);
|
||||
}
|
||||
|
||||
@ -1694,9 +1705,9 @@ emu_initefx(struct emu_sc_info *sc)
|
||||
|
||||
/* stop DSP */
|
||||
if (sc->is_emu10k1) {
|
||||
emu_wrptr(sc, 0, DBG, EMU10K1_DBG_SINGLE_STEP);
|
||||
emu_wrptr(sc, 0, EMU_DBG, EMU_DBG_SINGLE_STEP);
|
||||
} else {
|
||||
emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
|
||||
emu_wrptr(sc, 0, EMU_A_DBG, EMU_A_DBG_SINGLE_STEP);
|
||||
}
|
||||
|
||||
/* code size is in instructions */
|
||||
@ -2162,9 +2173,9 @@ emu_initefx(struct emu_sc_info *sc)
|
||||
|
||||
/* start DSP */
|
||||
if (sc->is_emu10k1) {
|
||||
emu_wrptr(sc, 0, DBG, 0);
|
||||
emu_wrptr(sc, 0, EMU_DBG, 0);
|
||||
} else {
|
||||
emu_wrptr(sc, 0, A_DBG, 0);
|
||||
emu_wrptr(sc, 0, EMU_A_DBG, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2450,24 +2461,24 @@ emumix_set_mode(struct emu_sc_info *sc, int mode)
|
||||
return;
|
||||
}
|
||||
|
||||
hcfg = HCFG_AUDIOENABLE | HCFG_AUTOMUTE;
|
||||
hcfg = EMU_HCFG_AUDIOENABLE | EMU_HCFG_AUTOMUTE;
|
||||
a_iocfg = 0;
|
||||
|
||||
if (sc->rev >= 6)
|
||||
hcfg |= HCFG_JOYENABLE;
|
||||
hcfg |= EMU_HCFG_JOYENABLE;
|
||||
|
||||
if (sc->is_emu10k1)
|
||||
hcfg |= HCFG_LOCKTANKCACHE_MASK;
|
||||
hcfg |= EMU_HCFG_LOCKTANKCACHE_MASK;
|
||||
else
|
||||
hcfg |= HCFG_CODECFORMAT_I2S | HCFG_JOYENABLE;
|
||||
hcfg |= EMU_HCFG_CODECFMT_I2S | EMU_HCFG_JOYENABLE;
|
||||
|
||||
|
||||
if (mode == MODE_DIGITAL) {
|
||||
if (sc->broken_digital) {
|
||||
device_printf(sc->dev, "Digital mode is reported as broken on this card.\n");
|
||||
}
|
||||
a_iocfg |= A_IOCFG_ENABLE_DIGITAL;
|
||||
hcfg |= HCFG_GPOUT0;
|
||||
a_iocfg |= EMU_A_IOCFG_GPOUT1;
|
||||
hcfg |= EMU_HCFG_GPOUT0;
|
||||
}
|
||||
|
||||
if (mode == MODE_ANALOG)
|
||||
@ -2478,12 +2489,12 @@ emumix_set_mode(struct emu_sc_info *sc, int mode)
|
||||
|
||||
if ((sc->is_ca0102) || (sc->is_ca0108))
|
||||
/*
|
||||
* Setting A_IOCFG_DISABLE_ANALOG will do opposite things
|
||||
* Setting EMU_A_IOCFG_DISABLE_ANALOG will do opposite things
|
||||
* on diffrerent cards.
|
||||
* "don't disable analog outs" on Audigy 2 (ca0102/ca0108)
|
||||
* "disable analog outs" on Audigy (emu10k2)
|
||||
*/
|
||||
a_iocfg |= A_IOCFG_DISABLE_ANALOG;
|
||||
a_iocfg |= EMU_A_IOCFG_DISABLE_ANALOG;
|
||||
|
||||
if (sc->is_ca0108)
|
||||
a_iocfg |= 0x20; /* XXX */
|
||||
@ -2492,12 +2503,12 @@ emumix_set_mode(struct emu_sc_info *sc, int mode)
|
||||
if (mode == MODE_DIGITAL)
|
||||
emumix_set_gpr(sc, sc->mute_gpr[ANALOGMUTE], 1);
|
||||
|
||||
emu_wr(sc, HCFG, hcfg, 4);
|
||||
emu_wr(sc, EMU_HCFG, hcfg, 4);
|
||||
|
||||
if ((sc->is_emu10k2) || (sc->is_ca0102) || (sc->is_ca0108)) {
|
||||
tmp = emu_rd(sc, A_IOCFG, 2);
|
||||
tmp = emu_rd(sc, EMU_A_IOCFG, 2);
|
||||
tmp = a_iocfg;
|
||||
emu_wr(sc, A_IOCFG, tmp, 2);
|
||||
emu_wr(sc, EMU_A_IOCFG, tmp, 2);
|
||||
}
|
||||
|
||||
/* Unmute if we have changed mode to analog. */
|
||||
@ -2523,16 +2534,16 @@ emumix_set_spdif_mode(struct emu_sc_info *sc, int mode)
|
||||
return;
|
||||
}
|
||||
|
||||
spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
|
||||
SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
|
||||
SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
|
||||
SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
|
||||
spcs = EMU_SPCS_CLKACCY_1000PPM | EMU_SPCS_SAMPLERATE_48 |
|
||||
EMU_SPCS_CHANNELNUM_LEFT | EMU_SPCS_SOURCENUM_UNSPEC |
|
||||
EMU_SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
|
||||
EMU_SPCS_EMPHASIS_NONE | EMU_SPCS_COPYRIGHT;
|
||||
|
||||
mode = SPDIF_MODE_PCM;
|
||||
|
||||
emu_wrptr(sc, 0, SPCS0, spcs);
|
||||
emu_wrptr(sc, 0, SPCS1, spcs);
|
||||
emu_wrptr(sc, 0, SPCS2, spcs);
|
||||
emu_wrptr(sc, 0, EMU_SPCS0, spcs);
|
||||
emu_wrptr(sc, 0, EMU_SPCS1, spcs);
|
||||
emu_wrptr(sc, 0, EMU_SPCS2, spcs);
|
||||
}
|
||||
|
||||
#define L2L_POINTS 10
|
||||
@ -2635,8 +2646,8 @@ emu_cardbus_init(struct emu_sc_info *sc)
|
||||
{
|
||||
|
||||
/*
|
||||
* XXX May not need this if we have IPR3 handler.
|
||||
* Is it a real init calls, or IPR3 interrupt acknowledgments?
|
||||
* XXX May not need this if we have EMU_IPR3 handler.
|
||||
* Is it a real init calls, or EMU_IPR3 interrupt acknowledgments?
|
||||
* Looks much like "(data << 16) | register".
|
||||
*/
|
||||
emu_wr_cbptr(sc, (0x00d0 << 16) | 0x0000);
|
||||
@ -2660,42 +2671,42 @@ emu_init(struct emu_sc_info *sc)
|
||||
int i;
|
||||
|
||||
/* disable audio and lock cache */
|
||||
emu_wr(sc, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 4);
|
||||
emu_wr(sc, EMU_HCFG, EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE, 4);
|
||||
|
||||
/* reset recording buffers */
|
||||
emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, MICBA, 0);
|
||||
emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, FXBA, 0);
|
||||
emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, ADCBA, 0);
|
||||
emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, EMU_MICBA, 0);
|
||||
emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, EMU_FXBA, 0);
|
||||
emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, EMU_ADCBA, 0);
|
||||
|
||||
/* disable channel interrupt */
|
||||
emu_wr(sc, INTE, INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE, 4);
|
||||
emu_wrptr(sc, 0, CLIEL, 0);
|
||||
emu_wrptr(sc, 0, CLIEH, 0);
|
||||
emu_wrptr(sc, 0, SOLEL, 0);
|
||||
emu_wrptr(sc, 0, SOLEH, 0);
|
||||
emu_wr(sc, EMU_INTE, EMU_INTE_INTERTIMERENB | EMU_INTE_SAMPLERATER | EMU_INTE_PCIERRENABLE, 4);
|
||||
emu_wrptr(sc, 0, EMU_CLIEL, 0);
|
||||
emu_wrptr(sc, 0, EMU_CLIEH, 0);
|
||||
emu_wrptr(sc, 0, EMU_SOLEL, 0);
|
||||
emu_wrptr(sc, 0, EMU_SOLEH, 0);
|
||||
|
||||
/* disable P16V and S/PDIF interrupts */
|
||||
if ((sc->is_ca0102) || (sc->is_ca0108))
|
||||
emu_wr(sc, INTE2, 0, 4);
|
||||
emu_wr(sc, EMU_INTE2, 0, 4);
|
||||
|
||||
if (sc->is_ca0102)
|
||||
emu_wr(sc, INTE3, 0, 4);
|
||||
emu_wr(sc, EMU_INTE3, 0, 4);
|
||||
|
||||
/* init phys inputs and outputs */
|
||||
ac97slot = 0;
|
||||
if (sc->has_51)
|
||||
ac97slot = AC97SLOT_CNTR | AC97SLOT_LFE;
|
||||
ac97slot = EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE;
|
||||
if (sc->has_71)
|
||||
ac97slot = AC97SLOT_CNTR | AC97SLOT_LFE | AC97SLOT_REAR_LEFT | AC97SLOT_REAR_RIGHT;
|
||||
ac97slot = EMU_AC97SLOT_CENTER | EMU_AC97SLOT_LFE | EMU_AC97SLOT_REAR_LEFT | EMU_AC97SLOT_REAR_RIGHT;
|
||||
if (sc->is_emu10k2)
|
||||
ac97slot |= 0x40;
|
||||
emu_wrptr(sc, 0, AC97SLOT, ac97slot);
|
||||
emu_wrptr(sc, 0, EMU_AC97SLOT, ac97slot);
|
||||
|
||||
if (sc->is_emu10k2) /* XXX for later cards? */
|
||||
emu_wrptr(sc, 0, SPBYPASS, 0xf00); /* What will happen if
|
||||
emu_wrptr(sc, 0, EMU_SPBYPASS, 0xf00); /* What will happen if
|
||||
* we write 1 here? */
|
||||
|
||||
if (bus_dma_tag_create( /* parent */ bus_get_dma_tag(sc->dev),
|
||||
@ -2729,61 +2740,61 @@ emu_init(struct emu_sc_info *sc)
|
||||
sc->mem.ptb_pages[i] = tmp | i;
|
||||
|
||||
for (ch = 0; ch < NUM_G; ch++) {
|
||||
emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK);
|
||||
emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_MAPA, tmp | EMU_CHAN_MAP_PTI_MASK);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_MAPB, tmp | EMU_CHAN_MAP_PTI_MASK);
|
||||
}
|
||||
emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr));
|
||||
emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */
|
||||
emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */
|
||||
emu_wrptr(sc, 0, EMU_PTB, (sc->mem.ptb_pages_addr));
|
||||
emu_wrptr(sc, 0, EMU_TCB, 0); /* taken from original driver */
|
||||
emu_wrptr(sc, 0, EMU_TCBS, 0); /* taken from original driver */
|
||||
|
||||
/* init envelope engine */
|
||||
for (ch = 0; ch < NUM_G; ch++) {
|
||||
emu_wrptr(sc, ch, DCYSUSV, 0);
|
||||
emu_wrptr(sc, ch, IP, 0);
|
||||
emu_wrptr(sc, ch, VTFT, 0xffff);
|
||||
emu_wrptr(sc, ch, CVCF, 0xffff);
|
||||
emu_wrptr(sc, ch, PTRX, 0);
|
||||
emu_wrptr(sc, ch, CPF, 0);
|
||||
emu_wrptr(sc, ch, CCR, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_IP, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0xffff);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0xffff);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_CCR, 0);
|
||||
|
||||
emu_wrptr(sc, ch, PSST, 0);
|
||||
emu_wrptr(sc, ch, DSL, 0x10);
|
||||
emu_wrptr(sc, ch, CCCA, 0);
|
||||
emu_wrptr(sc, ch, Z1, 0);
|
||||
emu_wrptr(sc, ch, Z2, 0);
|
||||
emu_wrptr(sc, ch, FXRT, 0xd01c0000);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_PSST, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_DSL, 0x10);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_CCCA, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_Z1, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_Z2, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_FXRT, 0xd01c0000);
|
||||
|
||||
emu_wrptr(sc, ch, ATKHLDM, 0);
|
||||
emu_wrptr(sc, ch, DCYSUSM, 0);
|
||||
emu_wrptr(sc, ch, IFATN, 0xffff);
|
||||
emu_wrptr(sc, ch, PEFE, 0);
|
||||
emu_wrptr(sc, ch, FMMOD, 0);
|
||||
emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */
|
||||
emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */
|
||||
emu_wrptr(sc, ch, TEMPENV, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_ATKHLDM, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_DCYSUSM, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_IFATN, 0xffff);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_PEFE, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_FMMOD, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_TREMFRQ, 24); /* 1 Hz */
|
||||
emu_wrptr(sc, ch, EMU_CHAN_FM2FRQ2, 24); /* 1 Hz */
|
||||
emu_wrptr(sc, ch, EMU_CHAN_TEMPENV, 0);
|
||||
|
||||
/*** these are last so OFF prevents writing ***/
|
||||
emu_wrptr(sc, ch, LFOVAL2, 0);
|
||||
emu_wrptr(sc, ch, LFOVAL1, 0);
|
||||
emu_wrptr(sc, ch, ATKHLDV, 0);
|
||||
emu_wrptr(sc, ch, ENVVOL, 0);
|
||||
emu_wrptr(sc, ch, ENVVAL, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_LFOVAL2, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_LFOVAL1, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_ATKHLDV, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_ENVVOL, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_ENVVAL, 0);
|
||||
|
||||
if ((sc->is_emu10k2) || (sc->is_ca0102) || (sc->is_ca0108)) {
|
||||
emu_wrptr(sc, ch, 0x4c, 0x0);
|
||||
emu_wrptr(sc, ch, 0x4d, 0x0);
|
||||
emu_wrptr(sc, ch, 0x4e, 0x0);
|
||||
emu_wrptr(sc, ch, 0x4f, 0x0);
|
||||
emu_wrptr(sc, ch, A_FXRT1, 0x3f3f3f3f);
|
||||
emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f);
|
||||
emu_wrptr(sc, ch, A_SENDAMOUNTS, 0x0);
|
||||
emu_wrptr(sc, ch, EMU_A_CHAN_FXRT1, 0x3f3f3f3f);
|
||||
emu_wrptr(sc, ch, EMU_A_CHAN_FXRT2, 0x3f3f3f3f);
|
||||
emu_wrptr(sc, ch, EMU_A_CHAN_SENDAMOUNTS, 0x0);
|
||||
}
|
||||
}
|
||||
|
||||
emumix_set_spdif_mode(sc, SPDIF_MODE_PCM);
|
||||
|
||||
if ((sc->is_emu10k2) || (sc->is_ca0102) || (sc->is_ca0108))
|
||||
emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, A_SPDIF_48000);
|
||||
emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, EMU_A_SPDIF_48000);
|
||||
|
||||
/*
|
||||
* CAxxxx cards needs additional setup:
|
||||
@ -2793,23 +2804,23 @@ emu_init(struct emu_sc_info *sc)
|
||||
*/
|
||||
if ((sc->is_ca0102) || (sc->is_ca0108)) {
|
||||
|
||||
spdif_sr = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE);
|
||||
spdif_sr = emu_rdptr(sc, 0, EMU_A_SPDIF_SAMPLERATE);
|
||||
spdif_sr &= 0xfffff1ff;
|
||||
spdif_sr |= A_I2S_CAPTURE_96000;
|
||||
emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, spdif_sr);
|
||||
spdif_sr |= EMU_A_I2S_CAPTURE_96000;
|
||||
emu_wrptr(sc, 0, EMU_A_SPDIF_SAMPLERATE, spdif_sr);
|
||||
|
||||
/* Disable P16v processing */
|
||||
emu_wr_p16vptr(sc, 0, SRCSel, 0x14);
|
||||
emu_wr_p16vptr(sc, 0, EMU_A2_SRCSel, 0x14);
|
||||
|
||||
/* Setup P16v/P17v sound routing */
|
||||
if (sc->is_ca0102)
|
||||
emu_wr_p16vptr(sc, 0, SRCMULTI_ENABLE, 0xFF00FF00);
|
||||
emu_wr_p16vptr(sc, 0, EMU_A2_SRCMULTI_ENABLE, 0xFF00FF00);
|
||||
else {
|
||||
emu_wr_p16vptr(sc, 0, P17V_MIXER_I2S_ENABLE, 0xFF000000);
|
||||
emu_wr_p16vptr(sc, 0, P17V_MIXER_SPDIF_ENABLE, 0xFF000000);
|
||||
emu_wr_p16vptr(sc, 0, EMU_A2_MIXER_I2S_ENABLE, 0xFF000000);
|
||||
emu_wr_p16vptr(sc, 0, EMU_A2_MIXER_SPDIF_ENABLE, 0xFF000000);
|
||||
|
||||
tmp = emu_rd(sc, A_IOCFG, 2);
|
||||
emu_wr(sc, A_IOCFG, tmp & ~0x8, 2);
|
||||
tmp = emu_rd(sc, EMU_A_IOCFG, 2);
|
||||
emu_wr(sc, EMU_A_IOCFG, tmp & ~0x8, 2);
|
||||
}
|
||||
}
|
||||
emu_initefx(sc);
|
||||
@ -2824,7 +2835,7 @@ emu_init(struct emu_sc_info *sc)
|
||||
emumix_set_mode(sc, def_mode);
|
||||
|
||||
if (bootverbose) {
|
||||
tmp = emu_rd(sc, HCFG, 4);
|
||||
tmp = emu_rd(sc, EMU_HCFG, 4);
|
||||
device_printf(sc->dev, "Card Configuration ( 0x%08x )\n", tmp);
|
||||
device_printf(sc->dev, "Card Configuration ( & 0xff000000 ) : %s%s%s%s%s%s%s%s\n",
|
||||
(tmp & 0x80000000 ? "[Legacy MPIC] " : ""),
|
||||
@ -2864,7 +2875,7 @@ emu_init(struct emu_sc_info *sc)
|
||||
(tmp & 0x00000001 ? "[AUDIOENABLE]" : " "));
|
||||
|
||||
if ((sc->is_emu10k2) || (sc->is_ca0102) || (sc->is_ca0108)) {
|
||||
tmp = emu_rd(sc, A_IOCFG, 2);
|
||||
tmp = emu_rd(sc, EMU_A_IOCFG, 2);
|
||||
device_printf(sc->dev, "Audigy Card Configuration ( 0x%04x )\n", tmp);
|
||||
device_printf(sc->dev, "Audigy Card Configuration ( & 0xff00 )");
|
||||
printf(" : %s%s%s%s%s%s%s%s\n",
|
||||
@ -2897,36 +2908,36 @@ emu_uninit(struct emu_sc_info *sc)
|
||||
uint32_t ch;
|
||||
struct emu_memblk *blk;
|
||||
|
||||
emu_wr(sc, INTE, 0, 4);
|
||||
emu_wr(sc, EMU_INTE, 0, 4);
|
||||
for (ch = 0; ch < NUM_G; ch++)
|
||||
emu_wrptr(sc, ch, DCYSUSV, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_DCYSUSV, 0);
|
||||
for (ch = 0; ch < NUM_G; ch++) {
|
||||
emu_wrptr(sc, ch, VTFT, 0);
|
||||
emu_wrptr(sc, ch, CVCF, 0);
|
||||
emu_wrptr(sc, ch, PTRX, 0);
|
||||
emu_wrptr(sc, ch, CPF, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_VTFT, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_CVCF, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_PTRX, 0);
|
||||
emu_wrptr(sc, ch, EMU_CHAN_CPF, 0);
|
||||
}
|
||||
|
||||
/* disable audio and lock cache */
|
||||
emu_wr(sc, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, 4);
|
||||
emu_wr(sc, EMU_HCFG, EMU_HCFG_LOCKSOUNDCACHE | EMU_HCFG_LOCKTANKCACHE_MASK | EMU_HCFG_MUTEBUTTONENABLE, 4);
|
||||
|
||||
emu_wrptr(sc, 0, PTB, 0);
|
||||
emu_wrptr(sc, 0, EMU_PTB, 0);
|
||||
/* reset recording buffers */
|
||||
emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, MICBA, 0);
|
||||
emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, FXBA, 0);
|
||||
emu_wrptr(sc, 0, FXWC, 0);
|
||||
emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, ADCBA, 0);
|
||||
emu_wrptr(sc, 0, TCB, 0);
|
||||
emu_wrptr(sc, 0, TCBS, 0);
|
||||
emu_wrptr(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, EMU_MICBA, 0);
|
||||
emu_wrptr(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, EMU_FXBA, 0);
|
||||
emu_wrptr(sc, 0, EMU_FXWC, 0);
|
||||
emu_wrptr(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
|
||||
emu_wrptr(sc, 0, EMU_ADCBA, 0);
|
||||
emu_wrptr(sc, 0, EMU_TCB, 0);
|
||||
emu_wrptr(sc, 0, EMU_TCBS, 0);
|
||||
|
||||
/* disable channel interrupt */
|
||||
emu_wrptr(sc, 0, CLIEL, 0);
|
||||
emu_wrptr(sc, 0, CLIEH, 0);
|
||||
emu_wrptr(sc, 0, SOLEL, 0);
|
||||
emu_wrptr(sc, 0, SOLEH, 0);
|
||||
emu_wrptr(sc, 0, EMU_CLIEL, 0);
|
||||
emu_wrptr(sc, 0, EMU_CLIEH, 0);
|
||||
emu_wrptr(sc, 0, EMU_SOLEL, 0);
|
||||
emu_wrptr(sc, 0, EMU_SOLEH, 0);
|
||||
|
||||
if (!SLIST_EMPTY(&sc->mem.blocks))
|
||||
device_printf(sc->dev, "warning: memblock list not empty\n");
|
||||
@ -3137,9 +3148,9 @@ emu_pci_attach(device_t dev)
|
||||
/* 0xe0...0x100 are unknown */
|
||||
/* sc->tram_base = 0x200 */
|
||||
/* sc->tram_addr_base = 0x300 */
|
||||
sc->gpr_base = A_FXGPREGBASE;
|
||||
sc->gpr_base = EMU_A_FXGPREGBASE;
|
||||
sc->num_gprs = 0x200;
|
||||
sc->code_base = A_MICROCODEBASE;
|
||||
sc->code_base = EMU_A_MICROCODEBASE;
|
||||
sc->code_size = 0x800 / 2; /* 0x600-0xdff, 2048 words,
|
||||
* 1024 instructions */
|
||||
|
||||
@ -3147,16 +3158,16 @@ emu_pci_attach(device_t dev)
|
||||
sc->num_fxbuses = 16;
|
||||
sc->num_inputs = 8;
|
||||
sc->num_outputs = 16;
|
||||
sc->address_mask = A_PTR_ADDRESS_MASK;
|
||||
sc->address_mask = EMU_A_PTR_ADDR_MASK;
|
||||
}
|
||||
if (sc->is_emu10k1) {
|
||||
sc->has_51 = 0; /* We don't support 5.1 sound on SB Live! 5.1 */
|
||||
sc->opcode_shift = 20;
|
||||
sc->high_operand_shift = 10;
|
||||
sc->code_base = MICROCODEBASE;
|
||||
sc->code_base = EMU_MICROCODEBASE;
|
||||
sc->code_size = 0x400 / 2; /* 0x400-0x7ff, 1024 words,
|
||||
* 512 instructions */
|
||||
sc->gpr_base = FXGPREGBASE;
|
||||
sc->gpr_base = EMU_FXGPREGBASE;
|
||||
sc->num_gprs = 0x100;
|
||||
sc->input_base = 0x10;
|
||||
sc->output_base = 0x20;
|
||||
@ -3171,7 +3182,7 @@ emu_pci_attach(device_t dev)
|
||||
sc->num_fxbuses = 8;
|
||||
sc->num_inputs = 8;
|
||||
sc->num_outputs = 16;
|
||||
sc->address_mask = PTR_ADDRESS_MASK;
|
||||
sc->address_mask = EMU_PTR_ADDR_MASK;
|
||||
}
|
||||
if (sc->opcode_shift == 0)
|
||||
goto bad;
|
||||
@ -3379,7 +3390,7 @@ emu_pci_attach(device_t dev)
|
||||
}
|
||||
midiinfo->card = sc;
|
||||
if (sc->is_emu10k2 || (sc->is_ca0102)) {
|
||||
midiinfo->port = A_MUDATA1;
|
||||
midiinfo->port = EMU_A_MUDATA1;
|
||||
midiinfo->portnr = 1;
|
||||
}
|
||||
if (sc->is_emu10k1) {
|
||||
@ -3405,7 +3416,7 @@ emu_pci_attach(device_t dev)
|
||||
}
|
||||
midiinfo->card = sc;
|
||||
|
||||
midiinfo->port = A_MUDATA2;
|
||||
midiinfo->port = EMU_A_MUDATA2;
|
||||
midiinfo->portnr = 2;
|
||||
|
||||
func->func = SCF_MIDI;
|
||||
|
||||
@ -52,6 +52,14 @@
|
||||
#define EMU_VAR_MCH_DISABLED 3
|
||||
#define EMU_VAR_MCH_REC 4
|
||||
|
||||
#define EMU_A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 */
|
||||
#define EMU_A_IOCFG_GPOUT2 0x0001
|
||||
#define EMU_AC97SLOT_REAR_RIGHT 0x01
|
||||
#define EMU_AC97SLOT_REAR_LEFT 0x02
|
||||
#define EMU_HCFG_GPOUT0 0x00001000
|
||||
#define EMU_HCFG_GPOUT1 0x00000800
|
||||
#define EMU_HCFG_GPOUT2 0x00000400
|
||||
|
||||
#define RT_FRONT 0
|
||||
#define RT_REAR 1
|
||||
#define RT_CENTER 2
|
||||
|
||||
@ -168,8 +168,8 @@
|
||||
#define EMU_A_IOCFG 0x18
|
||||
#define EMU_A_GPINPUT_MASK 0xff00
|
||||
#define EMU_A_GPOUTPUT_MASK 0x00ff
|
||||
#define EMU_A_IOCFG_GPOUT0 0x0040
|
||||
#define EMU_A_IOCFG_GPOUT1 0x0004
|
||||
#define EMU_A_IOCFG_GPOUT0 0x0044
|
||||
#define EMU_A_IOCFG_GPOUT1 0x0002
|
||||
|
||||
#define EMU_TIMER 0x1a
|
||||
#define EMU_TIMER_RATE_MASK 0x000003ff
|
||||
@ -532,8 +532,8 @@
|
||||
#define EMU_A_FXWC1 0x74
|
||||
#define EMU_A_FXWC2 0x75
|
||||
#define EMU_A_SPDIF_SAMPLERATE 0x76
|
||||
#define EMU_A_SPDIF_48000 0x00000080
|
||||
#define EMU_A_SPDIF_44100 0x00000000
|
||||
#define EMU_A_SPDIF_44100 0x00000080
|
||||
#define EMU_A_SPDIF_48000 0x00000000
|
||||
#define EMU_A_SPDIF_96000 0x00000040
|
||||
#define EMU_A2_SPDIF_SAMPLERATE EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE)
|
||||
#define EMU_A2_SPDIF_MASK 0x00000e00
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,301 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
|
||||
* Driver p16v chips
|
||||
* Version: 0.21
|
||||
*
|
||||
* FEATURES currently supported:
|
||||
* Output fixed at S32_LE, 2 channel to hw:0,0
|
||||
* Rates: 44.1, 48, 96, 192.
|
||||
*
|
||||
* Changelog:
|
||||
* 0.8
|
||||
* Use separate card based buffer for periods table.
|
||||
* 0.9
|
||||
* Use 2 channel output streams instead of 8 channel.
|
||||
* (8 channel output streams might be good for ASIO type output)
|
||||
* Corrected speaker output, so Front -> Front etc.
|
||||
* 0.10
|
||||
* Fixed missed interrupts.
|
||||
* 0.11
|
||||
* Add Sound card model number and names.
|
||||
* Add Analog volume controls.
|
||||
* 0.12
|
||||
* Corrected playback interrupts. Now interrupt per period, instead of half period.
|
||||
* 0.13
|
||||
* Use single trigger for multichannel.
|
||||
* 0.14
|
||||
* Mic capture now works at fixed: S32_LE, 96000Hz, Stereo.
|
||||
* 0.15
|
||||
* Force buffer_size / period_size == INTEGER.
|
||||
* 0.16
|
||||
* Update p16v.c to work with changed alsa api.
|
||||
* 0.17
|
||||
* Update p16v.c to work with changed alsa api. Removed boot_devs.
|
||||
* 0.18
|
||||
* Merging with snd-emu10k1 driver.
|
||||
* 0.19
|
||||
* One stereo channel at 24bit now works.
|
||||
* 0.20
|
||||
* Added better register defines.
|
||||
* 0.21
|
||||
* Split from p16v.c
|
||||
*
|
||||
*
|
||||
* BUGS:
|
||||
* Some stability problems when unloading the snd-p16v kernel module.
|
||||
* --
|
||||
*
|
||||
* TODO:
|
||||
* SPDIF out.
|
||||
* Find out how to change capture sample rates. E.g. To record SPDIF at 48000Hz.
|
||||
* Currently capture fixed at 48000Hz.
|
||||
*
|
||||
* --
|
||||
* GENERAL INFO:
|
||||
* Model: SB0240
|
||||
* P16V Chip: CA0151-DBS
|
||||
* Audigy 2 Chip: CA0102-IAT
|
||||
* AC97 Codec: STAC 9721
|
||||
* ADC: Philips 1361T (Stereo 24bit)
|
||||
* DAC: CS4382-K (8-channel, 24bit, 192Khz)
|
||||
*
|
||||
* This code was initally based on code from ALSA's emu10k1x.c which is:
|
||||
* Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/********************************************************************************************************/
|
||||
/* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */
|
||||
/********************************************************************************************************/
|
||||
|
||||
/* The sample rate of the SPDIF outputs is set by modifying a register in the EMU10K2 PTR register A_SPDIF_SAMPLERATE.
|
||||
* The sample rate is also controlled by the same registers that control the rate of the EMU10K2 sample rate converters.
|
||||
*/
|
||||
|
||||
/* Initally all registers from 0x00 to 0x3f have zero contents. */
|
||||
#define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
|
||||
/* One list entry: 4 bytes for DMA address,
|
||||
* 4 bytes for period_size << 16.
|
||||
* One list entry is 8 bytes long.
|
||||
* One list entry for each period in the buffer.
|
||||
*/
|
||||
#define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
|
||||
#define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
|
||||
#define PLAYBACK_UNKNOWN3 0x03 /* Not used */
|
||||
#define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA addresss */
|
||||
#define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */
|
||||
#define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
|
||||
#define PLAYBACK_FIFO_END_ADDRESS 0x07 /* Playback FIFO end address */
|
||||
#define PLAYBACK_FIFO_POINTER 0x08 /* Playback FIFO pointer and number of valid sound samples in cache */
|
||||
#define PLAYBACK_UNKNOWN9 0x09 /* Not used */
|
||||
#define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
|
||||
#define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
|
||||
#define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
|
||||
#define CAPTURE_FIFO_POINTER 0x13 /* Capture FIFO pointer and number of valid sound samples in cache */
|
||||
#define CAPTURE_P16V_VOLUME1 0x14 /* Low: Capture volume 0xXXXX3030 */
|
||||
#define CAPTURE_P16V_VOLUME2 0x15 /* High:Has no effect on capture volume */
|
||||
#define CAPTURE_P16V_SOURCE 0x16 /* P16V source select. Set to 0x0700E4E5 for AC97 CAPTURE */
|
||||
/* [0:1] Capture input 0 channel select. 0 = Capture output 0.
|
||||
* 1 = Capture output 1.
|
||||
* 2 = Capture output 2.
|
||||
* 3 = Capture output 3.
|
||||
* [3:2] Capture input 1 channel select. 0 = Capture output 0.
|
||||
* 1 = Capture output 1.
|
||||
* 2 = Capture output 2.
|
||||
* 3 = Capture output 3.
|
||||
* [5:4] Capture input 2 channel select. 0 = Capture output 0.
|
||||
* 1 = Capture output 1.
|
||||
* 2 = Capture output 2.
|
||||
* 3 = Capture output 3.
|
||||
* [7:6] Capture input 3 channel select. 0 = Capture output 0.
|
||||
* 1 = Capture output 1.
|
||||
* 2 = Capture output 2.
|
||||
* 3 = Capture output 3.
|
||||
* [9:8] Playback input 0 channel select. 0 = Play output 0.
|
||||
* 1 = Play output 1.
|
||||
* 2 = Play output 2.
|
||||
* 3 = Play output 3.
|
||||
* [11:10] Playback input 1 channel select. 0 = Play output 0.
|
||||
* 1 = Play output 1.
|
||||
* 2 = Play output 2.
|
||||
* 3 = Play output 3.
|
||||
* [13:12] Playback input 2 channel select. 0 = Play output 0.
|
||||
* 1 = Play output 1.
|
||||
* 2 = Play output 2.
|
||||
* 3 = Play output 3.
|
||||
* [15:14] Playback input 3 channel select. 0 = Play output 0.
|
||||
* 1 = Play output 1.
|
||||
* 2 = Play output 2.
|
||||
* 3 = Play output 3.
|
||||
* [19:16] Playback mixer output enable. 1 bit per channel.
|
||||
* [23:20] Capture mixer output enable. 1 bit per channel.
|
||||
* [26:24] FX engine channel capture 0 = 0x60-0x67.
|
||||
* 1 = 0x68-0x6f.
|
||||
* 2 = 0x70-0x77.
|
||||
* 3 = 0x78-0x7f.
|
||||
* 4 = 0x80-0x87.
|
||||
* 5 = 0x88-0x8f.
|
||||
* 6 = 0x90-0x97.
|
||||
* 7 = 0x98-0x9f.
|
||||
* [31:27] Not used.
|
||||
*/
|
||||
|
||||
/* 0x1 = capture on.
|
||||
* 0x100 = capture off.
|
||||
* 0x200 = capture off.
|
||||
* 0x1000 = capture off.
|
||||
*/
|
||||
#define CAPTURE_RATE_STATUS 0x17 /* Capture sample rate. Read only */
|
||||
/* [15:0] Not used.
|
||||
* [18:16] Channel 0 Detected sample rate. 0 - 44.1khz
|
||||
* 1 - 48 khz
|
||||
* 2 - 96 khz
|
||||
* 3 - 192 khz
|
||||
* 7 - undefined rate.
|
||||
* [19] Channel 0. 1 - Valid, 0 - Not Valid.
|
||||
* [22:20] Channel 1 Detected sample rate.
|
||||
* [23] Channel 1. 1 - Valid, 0 - Not Valid.
|
||||
* [26:24] Channel 2 Detected sample rate.
|
||||
* [27] Channel 2. 1 - Valid, 0 - Not Valid.
|
||||
* [30:28] Channel 3 Detected sample rate.
|
||||
* [31] Channel 3. 1 - Valid, 0 - Not Valid.
|
||||
*/
|
||||
/* 0x18 - 0x1f unused */
|
||||
#define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played. Read only */
|
||||
/* 0x21 - 0x3f unused */
|
||||
#define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */
|
||||
/* Playback (0x1<<channel_id) Don't touch high 16bits. */
|
||||
/* Capture (0x100<<channel_id). not tested */
|
||||
/* Start Playback [3:0] (one bit per channel)
|
||||
* Start Capture [11:8] (one bit per channel)
|
||||
* Record source select for channel 0 [18:16]
|
||||
* Record source select for channel 1 [22:20]
|
||||
* Record source select for channel 2 [26:24]
|
||||
* Record source select for channel 3 [30:28]
|
||||
* 0 - SPDIF channel.
|
||||
* 1 - I2S channel.
|
||||
* 2 - SRC48 channel.
|
||||
* 3 - SRCMulti_SPDIF channel.
|
||||
* 4 - SRCMulti_I2S channel.
|
||||
* 5 - SPDIF channel.
|
||||
* 6 - fxengine capture.
|
||||
* 7 - AC97 capture.
|
||||
*/
|
||||
/* Default 41110000.
|
||||
* Writing 0xffffffff hangs the PC.
|
||||
* Writing 0xffff0000 -> 77770000 so it must be some sort of route.
|
||||
* bit 0x1 starts DMA playback on channel_id 0
|
||||
*/
|
||||
/* 0x41,42 take values from 0 - 0xffffffff, but have no effect on playback */
|
||||
/* 0x43,0x48 do not remember settings */
|
||||
/* 0x41-45 unused */
|
||||
#define WATERMARK 0x46 /* Test bit to indicate cache level usage */
|
||||
/* Values it can have while playing on channel 0.
|
||||
* 0000f000, 0000f004, 0000f008, 0000f00c.
|
||||
* Readonly.
|
||||
*/
|
||||
/* 0x47-0x4f unused */
|
||||
/* 0x50-0x5f Capture cache data */
|
||||
#define SRCSel 0x60 /* SRCSel. Default 0x4. Bypass P16V 0x14 */
|
||||
/* [0] 0 = 10K2 audio, 1 = SRC48 mixer output.
|
||||
* [2] 0 = 10K2 audio, 1 = SRCMulti SPDIF mixer output.
|
||||
* [4] 0 = 10K2 audio, 1 = SRCMulti I2S mixer output.
|
||||
*/
|
||||
/* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
|
||||
/* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
|
||||
/* SRC48 and SRCMULTI sample rate select and output select. */
|
||||
/* 0xffffffff -> 0xC0000015
|
||||
* 0xXXXXXXX4 = Enable Front Left/Right
|
||||
* Enable PCMs
|
||||
*/
|
||||
|
||||
/* 0x61 -> 0x6c are Volume controls */
|
||||
#define PLAYBACK_VOLUME_MIXER1 0x61 /* SRC48 Low to mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER2 0x62 /* SRC48 High to mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER3 0x63 /* SRCMULTI SPDIF Low to mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER4 0x64 /* SRCMULTI SPDIF High to mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER5 0x65 /* SRCMULTI I2S Low to mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER6 0x66 /* SRCMULTI I2S High to mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER7 0x67 /* P16V Low to SRCMULTI SPDIF mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER8 0x68 /* P16V High to SRCMULTI SPDIF mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER9 0x69 /* P16V Low to SRCMULTI I2S mixer input volume control. */
|
||||
/* 0xXXXX3030 = PCM0 Volume (Front).
|
||||
* 0x3030XXXX = PCM1 Volume (Center)
|
||||
*/
|
||||
#define PLAYBACK_VOLUME_MIXER10 0x6a /* P16V High to SRCMULTI I2S mixer input volume control. */
|
||||
/* 0x3030XXXX = PCM3 Volume (Rear). */
|
||||
#define PLAYBACK_VOLUME_MIXER11 0x6b /* E10K2 Low to SRC48 mixer input volume control. */
|
||||
#define PLAYBACK_VOLUME_MIXER12 0x6c /* E10K2 High to SRC48 mixer input volume control. */
|
||||
|
||||
#define SRC48_ENABLE 0x6d /* SRC48 input audio enable */
|
||||
/* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
|
||||
/* [23:16] The corresponding P16V channel to SRC48 enabled if == 1.
|
||||
* [31:24] The corresponding E10K2 channel to SRC48 enabled.
|
||||
*/
|
||||
#define SRCMULTI_ENABLE 0x6e /* SRCMulti input audio enable. Default 0xffffffff */
|
||||
/* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
|
||||
/* [7:0] The corresponding P16V channel to SRCMulti_I2S enabled if == 1.
|
||||
* [15:8] The corresponding E10K2 channel to SRCMulti I2S enabled.
|
||||
* [23:16] The corresponding P16V channel to SRCMulti SPDIF enabled.
|
||||
* [31:24] The corresponding E10K2 channel to SRCMulti SPDIF enabled.
|
||||
*/
|
||||
/* Bypass P16V 0xff00ff00
|
||||
* Bitmap. 0 = Off, 1 = On.
|
||||
* P16V playback outputs:
|
||||
* 0xXXXXXXX1 = PCM0 Left. (Front)
|
||||
* 0xXXXXXXX2 = PCM0 Right.
|
||||
* 0xXXXXXXX4 = PCM1 Left. (Center/LFE)
|
||||
* 0xXXXXXXX8 = PCM1 Right.
|
||||
* 0xXXXXXX1X = PCM2 Left. (Unknown)
|
||||
* 0xXXXXXX2X = PCM2 Right.
|
||||
* 0xXXXXXX4X = PCM3 Left. (Rear)
|
||||
* 0xXXXXXX8X = PCM3 Right.
|
||||
*/
|
||||
#define AUDIO_OUT_ENABLE 0x6f /* Default: 000100FF */
|
||||
/* [3:0] Does something, but not documented. Probably capture enable.
|
||||
* [7:4] Playback channels enable. not documented.
|
||||
* [16] AC97 output enable if == 1
|
||||
* [30] 0 = SRCMulti_I2S input from fxengine 0x68-0x6f.
|
||||
* 1 = SRCMulti_I2S input from SRC48 output.
|
||||
* [31] 0 = SRCMulti_SPDIF input from fxengine 0x60-0x67.
|
||||
* 1 = SRCMulti_SPDIF input from SRC48 output.
|
||||
*/
|
||||
/* 0xffffffff -> C00100FF */
|
||||
/* 0 -> Not playback sound, irq still running */
|
||||
/* 0xXXXXXX10 = PCM0 Left/Right On. (Front)
|
||||
* 0xXXXXXX20 = PCM1 Left/Right On. (Center/LFE)
|
||||
* 0xXXXXXX40 = PCM2 Left/Right On. (Unknown)
|
||||
* 0xXXXXXX80 = PCM3 Left/Right On. (Rear)
|
||||
*/
|
||||
#define PLAYBACK_SPDIF_SELECT 0x70 /* Default: 12030F00 */
|
||||
/* 0xffffffff -> 3FF30FFF */
|
||||
/* 0x00000001 pauses stream/irq fail. */
|
||||
/* All other bits do not effect playback */
|
||||
#define PLAYBACK_SPDIF_SRC_SELECT 0x71 /* Default: 0000E4E4 */
|
||||
/* 0xffffffff -> F33FFFFF */
|
||||
/* All bits do not effect playback */
|
||||
#define PLAYBACK_SPDIF_USER_DATA0 0x72 /* SPDIF out user data 0 */
|
||||
#define PLAYBACK_SPDIF_USER_DATA1 0x73 /* SPDIF out user data 1 */
|
||||
/* 0x74-0x75 unknown */
|
||||
#define CAPTURE_SPDIF_CONTROL 0x76 /* SPDIF in control setting */
|
||||
#define CAPTURE_SPDIF_STATUS 0x77 /* SPDIF in status */
|
||||
#define CAPURE_SPDIF_USER_DATA0 0x78 /* SPDIF in user data 0 */
|
||||
#define CAPURE_SPDIF_USER_DATA1 0x79 /* SPDIF in user data 1 */
|
||||
#define CAPURE_SPDIF_USER_DATA2 0x7a /* SPDIF in user data 2 */
|
||||
|
||||
@ -1,113 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
|
||||
* Driver p17v chips
|
||||
* Version: 0.01
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Audigy2Value Tina (P17V) pointer-offset register set,
|
||||
* accessed through the PTR20 and DATA24 registers */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 00 - 07: Not used */
|
||||
#define P17V_PLAYBACK_FIFO_PTR 0x08 /* Current playback fifo pointer
|
||||
* and number of sound samples in cache.
|
||||
*/
|
||||
/* 09 - 12: Not used */
|
||||
#define P17V_CAPTURE_FIFO_PTR 0x13 /* Current capture fifo pointer
|
||||
* and number of sound samples in cache.
|
||||
*/
|
||||
/* 14 - 17: Not used */
|
||||
#define P17V_PB_CHN_SEL 0x18 /* P17v playback channel select */
|
||||
#define P17V_SE_SLOT_SEL_L 0x19 /* Sound Engine slot select low */
|
||||
#define P17V_SE_SLOT_SEL_H 0x1a /* Sound Engine slot select high */
|
||||
/* 1b - 1f: Not used */
|
||||
/* 20 - 2f: Not used */
|
||||
/* 30 - 3b: Not used */
|
||||
#define P17V_SPI 0x3c /* SPI interface register */
|
||||
#define P17V_I2C_ADDR 0x3d /* I2C Address */
|
||||
#define P17V_I2C_0 0x3e /* I2C Data */
|
||||
#define P17V_I2C_1 0x3f /* I2C Data */
|
||||
|
||||
#define P17V_START_AUDIO 0x40 /* Start Audio bit */
|
||||
/* 41 - 47: Reserved */
|
||||
#define P17V_START_CAPTURE 0x48 /* Start Capture bit */
|
||||
#define P17V_CAPTURE_FIFO_BASE 0x49 /* Record FIFO base address */
|
||||
#define P17V_CAPTURE_FIFO_SIZE 0x4a /* Record FIFO buffer size */
|
||||
#define P17V_CAPTURE_FIFO_INDEX 0x4b /* Record FIFO capture index */
|
||||
#define P17V_CAPTURE_VOL_H 0x4c /* P17v capture volume control */
|
||||
#define P17V_CAPTURE_VOL_L 0x4d /* P17v capture volume control */
|
||||
/* 4e - 4f: Not used */
|
||||
/* 50 - 5f: Not used */
|
||||
#define P17V_SRCSel 0x60 /* SRC48 and SRCMulti sample rate select
|
||||
* and output select
|
||||
*/
|
||||
#define P17V_MIXER_AC97_10K1_VOL_L 0x61 /* 10K to Mixer_AC97 input volume control */
|
||||
#define P17V_MIXER_AC97_10K1_VOL_H 0x62 /* 10K to Mixer_AC97 input volume control */
|
||||
#define P17V_MIXER_AC97_P17V_VOL_L 0x63 /* P17V to Mixer_AC97 input volume control */
|
||||
#define P17V_MIXER_AC97_P17V_VOL_H 0x64 /* P17V to Mixer_AC97 input volume control */
|
||||
#define P17V_MIXER_AC97_SRP_REC_VOL_L 0x65 /* SRP Record to Mixer_AC97 input volume control */
|
||||
#define P17V_MIXER_AC97_SRP_REC_VOL_H 0x66 /* SRP Record to Mixer_AC97 input volume control */
|
||||
/* 67 - 68: Reserved */
|
||||
#define P17V_MIXER_Spdif_10K1_VOL_L 0x69 /* 10K to Mixer_Spdif input volume control */
|
||||
#define P17V_MIXER_Spdif_10K1_VOL_H 0x6A /* 10K to Mixer_Spdif input volume control */
|
||||
#define P17V_MIXER_Spdif_P17V_VOL_L 0x6B /* P17V to Mixer_Spdif input volume control */
|
||||
#define P17V_MIXER_Spdif_P17V_VOL_H 0x6C /* P17V to Mixer_Spdif input volume control */
|
||||
#define P17V_MIXER_Spdif_SRP_REC_VOL_L 0x6D /* SRP Record to Mixer_Spdif input volume control */
|
||||
#define P17V_MIXER_Spdif_SRP_REC_VOL_H 0x6E /* SRP Record to Mixer_Spdif input volume control */
|
||||
/* 6f - 70: Reserved */
|
||||
#define P17V_MIXER_I2S_10K1_VOL_L 0x71 /* 10K to Mixer_I2S input volume control */
|
||||
#define P17V_MIXER_I2S_10K1_VOL_H 0x72 /* 10K to Mixer_I2S input volume control */
|
||||
#define P17V_MIXER_I2S_P17V_VOL_L 0x73 /* P17V to Mixer_I2S input volume control */
|
||||
#define P17V_MIXER_I2S_P17V_VOL_H 0x74 /* P17V to Mixer_I2S input volume control */
|
||||
#define P17V_MIXER_I2S_SRP_REC_VOL_L 0x75 /* SRP Record to Mixer_I2S input volume control */
|
||||
#define P17V_MIXER_I2S_SRP_REC_VOL_H 0x76 /* SRP Record to Mixer_I2S input volume control */
|
||||
/* 77 - 78: Reserved */
|
||||
#define P17V_MIXER_AC97_ENABLE 0x79 /* Mixer AC97 input audio enable */
|
||||
#define P17V_MIXER_SPDIF_ENABLE 0x7A /* Mixer SPDIF input audio enable */
|
||||
#define P17V_MIXER_I2S_ENABLE 0x7B /* Mixer I2S input audio enable */
|
||||
#define P17V_AUDIO_OUT_ENABLE 0x7C /* Audio out enable */
|
||||
#define P17V_MIXER_ATT 0x7D /* SRP Mixer Attenuation Select */
|
||||
#define P17V_SRP_RECORD_SRR 0x7E /* SRP Record channel source Select */
|
||||
#define P17V_SOFT_RESET_SRP_MIXER 0x7F /* SRP and mixer soft reset */
|
||||
|
||||
#define P17V_AC97_OUT_MASTER_VOL_L 0x80 /* AC97 Output master volume control */
|
||||
#define P17V_AC97_OUT_MASTER_VOL_H 0x81 /* AC97 Output master volume control */
|
||||
#define P17V_SPDIF_OUT_MASTER_VOL_L 0x82 /* SPDIF Output master volume control */
|
||||
#define P17V_SPDIF_OUT_MASTER_VOL_H 0x83 /* SPDIF Output master volume control */
|
||||
#define P17V_I2S_OUT_MASTER_VOL_L 0x84 /* I2S Output master volume control */
|
||||
#define P17V_I2S_OUT_MASTER_VOL_H 0x85 /* I2S Output master volume control */
|
||||
/* 86 - 87: Not used */
|
||||
#define P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE 0x88 /* I2S out mono channel swap
|
||||
* and phase inverse */
|
||||
#define P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE 0x89 /* SPDIF out mono channel swap
|
||||
* and phase inverse */
|
||||
/* 8A: Not used */
|
||||
#define P17V_SRP_P17V_ESR 0x8B /* SRP_P17V estimated sample rate and rate lock */
|
||||
#define P17V_SRP_REC_ESR 0x8C /* SRP_REC estimated sample rate and rate lock */
|
||||
#define P17V_SRP_BYPASS 0x8D /* srps channel bypass and srps bypass */
|
||||
/* 8E - 92: Not used */
|
||||
#define P17V_I2S_SRC_SEL 0x93 /* I2SIN mode sel */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -11,29 +11,6 @@ SRCS+= vnode_if.h
|
||||
SRCS+= emu10kx.c
|
||||
SRCS+= emu10kx-pcm.c
|
||||
SRCS+= emu10kx-midi.c
|
||||
# de-GPLed Makefiles
|
||||
SRCS+= emu10k1-alsa%diked.h
|
||||
SRCS+= p16v-alsa%diked.h
|
||||
SRCS+= p17v-alsa%diked.h
|
||||
|
||||
emu10k1-alsa%diked.h: emu10k1-alsa.h
|
||||
grep -v '#include' ${.OODATE} | $(CC) -E -D__KERNEL__ -dM - \
|
||||
| awk -F"[ (]" '/define/ \
|
||||
{ print "#ifndef " $$2 ; print ; print "#endif" }' \
|
||||
>${.TARGET}
|
||||
p16v-alsa%diked.h: p16v-alsa.h
|
||||
grep -v '#include' ${.OODATE} | $(CC) -E -D__KERNEL__ -dM - \
|
||||
| awk -F"[ (]" '/define/ \
|
||||
{ print "#ifndef " $$2 ; print ; print "#endif" }' \
|
||||
>${.TARGET}
|
||||
p17v-alsa%diked.h: p17v-alsa.h
|
||||
grep -v '#include' ${.OODATE} | $(CC) -E -D__KERNEL__ -dM - \
|
||||
| awk -F"[ (]" '/define/ \
|
||||
{ print "#ifndef " $$2 ; print ; print "#endif" }' \
|
||||
>${.TARGET}
|
||||
|
||||
CLEANFILES+= emu10k1-alsa%diked.h
|
||||
CLEANFILES+= p16v-alsa%diked.h
|
||||
CLEANFILES+= p17v-alsa%diked.h
|
||||
SRCS+= emuxkireg.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user