From 43ad9f79cd483a53709246de5b9aee34bf7d493c Mon Sep 17 00:00:00 2001 From: andrew Date: Mon, 3 Oct 2016 11:57:10 +0000 Subject: [PATCH] Use C99 designated initializers to create the armv6 cpu_functions structs. This will help with a later cleanup of what functions we implement. Sponsored by: ABT Systems Ltd --- sys/arm/arm/cpufunc.c | 175 ++++++++++++++++++------------------------ 1 file changed, 73 insertions(+), 102 deletions(-) diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 9a848f5bb6a3..06c40e0ebedc 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -243,49 +243,40 @@ struct cpu_functions sheeva_cpufuncs = { #ifdef CPU_MV_PJ4B struct cpu_functions pj4bv7_cpufuncs = { /* CPU functions */ - - armv7_drain_writebuf, /* cpwait */ + .cf_cpwait = armv7_drain_writebuf, /* MMU functions */ - - cpufunc_control, /* control */ - armv7_setttb, /* Setttb */ + .cf_control = cpufunc_control, + .cf_setttb = armv7_setttb, /* TLB functions */ - - armv7_tlb_flushID, /* tlb_flushID */ - armv7_tlb_flushID_SE, /* tlb_flushID_SE */ - armv7_tlb_flushID, /* tlb_flushD */ - armv7_tlb_flushID_SE, /* tlb_flushD_SE */ + .cf_tlb_flushID = armv7_tlb_flushID, + .cf_tlb_flushID_SE = armv7_tlb_flushID_SE, + .cf_tlb_flushD = armv7_tlb_flushID, + .cf_tlb_flushD_SE = armv7_tlb_flushID_SE, /* Cache operations */ - armv7_icache_sync_range, /* icache_sync_range */ - - armv7_dcache_wbinv_all, /* dcache_wbinv_all */ - armv7_dcache_wbinv_range, /* dcache_wbinv_range */ - armv7_dcache_inv_range, /* dcache_inv_range */ - armv7_dcache_wb_range, /* dcache_wb_range */ - - armv7_idcache_inv_all, /* idcache_inv_all */ - armv7_idcache_wbinv_all, /* idcache_wbinv_all */ - armv7_idcache_wbinv_range, /* idcache_wbinv_all */ - - (void *)cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ + .cf_icache_sync_range = armv7_icache_sync_range, + .cf_dcache_wbinv_all = armv7_dcache_wbinv_all, + .cf_dcache_wbinv_range = armv7_dcache_wbinv_range, + .cf_dcache_inv_range = armv7_dcache_inv_range, + .cf_dcache_wb_range = armv7_dcache_wb_range, + .cf_idcache_inv_all = armv7_idcache_inv_all, + .cf_idcache_wbinv_all = armv7_idcache_wbinv_all, + .cf_idcache_wbinv_range = armv7_idcache_wbinv_range, + .cf_l2cache_wbinv_all = (void *)cpufunc_nullop, + .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, + .cf_l2cache_inv_range = (void *)cpufunc_nullop, + .cf_l2cache_wb_range = (void *)cpufunc_nullop, + .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, /* Other functions */ - - armv7_drain_writebuf, /* drain_writebuf */ - - (void *)cpufunc_nullop, /* sleep */ + .cf_drain_writebuf = armv7_drain_writebuf, + .cf_sleep = (void *)cpufunc_nullop, /* Soft functions */ - armv7_context_switch, /* context_switch */ - - pj4bv7_setup /* cpu setup */ + .cf_context_switch = armv7_context_switch, + .cf_setup = pj4bv7_setup }; #endif /* CPU_MV_PJ4B */ @@ -446,64 +437,51 @@ struct cpu_functions fa526_cpufuncs = { #if defined(CPU_ARM1176) struct cpu_functions arm1176_cpufuncs = { /* CPU functions */ - - cpufunc_nullop, /* cpwait */ - + .cf_cpwait = cpufunc_nullop, + /* MMU functions */ - - cpufunc_control, /* control */ - arm11x6_setttb, /* Setttb */ + .cf_control = cpufunc_control, + .cf_setttb = arm11x6_setttb, /* TLB functions */ - - arm11_tlb_flushID, /* tlb_flushID */ - arm11_tlb_flushID_SE, /* tlb_flushID_SE */ - arm11_tlb_flushD, /* tlb_flushD */ - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ + .cf_tlb_flushID = arm11_tlb_flushID, + .cf_tlb_flushID_SE = arm11_tlb_flushID_SE, + .cf_tlb_flushD = arm11_tlb_flushD, + .cf_tlb_flushD_SE = arm11_tlb_flushD_SE, /* Cache operations */ - - arm11x6_icache_sync_range, /* icache_sync_range */ - - arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */ - armv6_dcache_wbinv_range, /* dcache_wbinv_range */ - armv6_dcache_inv_range, /* dcache_inv_range */ - armv6_dcache_wb_range, /* dcache_wb_range */ - - armv6_idcache_inv_all, /* idcache_inv_all */ - arm11x6_idcache_wbinv_all, /* idcache_wbinv_all */ - arm11x6_idcache_wbinv_range, /* idcache_wbinv_range */ - - (void *)cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ + .cf_icache_sync_range = arm11x6_icache_sync_range, + .cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all, + .cf_dcache_wbinv_range = armv6_dcache_wbinv_range, + .cf_dcache_inv_range = armv6_dcache_inv_range, + .cf_dcache_wb_range = armv6_dcache_wb_range, + .cf_idcache_inv_all = armv6_idcache_inv_all, + .cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all, + .cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range, + .cf_l2cache_wbinv_all = (void *)cpufunc_nullop, + .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, + .cf_l2cache_inv_range = (void *)cpufunc_nullop, + .cf_l2cache_wb_range = (void *)cpufunc_nullop, + .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, /* Other functions */ - - arm11_drain_writebuf, /* drain_writebuf */ - - arm11x6_sleep, /* sleep */ + .cf_drain_writebuf = arm11_drain_writebuf, + .cf_sleep = arm11x6_sleep, /* Soft functions */ - - arm11_context_switch, /* context_switch */ - - arm11x6_setup /* cpu setup */ + .cf_context_switch = arm11_context_switch, + .cf_setup = arm11x6_setup }; #endif /*CPU_ARM1176 */ #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) struct cpu_functions cortexa_cpufuncs = { /* CPU functions */ - - cpufunc_nullop, /* cpwait */ + .cf_cpwait = cpufunc_nullop, /* MMU functions */ - - cpufunc_control, /* control */ - armv7_setttb, /* Setttb */ + .cf_control = cpufunc_control, + .cf_setttb = armv7_setttb, /* * TLB functions. ARMv7 does all TLB ops based on a unified TLB model @@ -511,45 +489,38 @@ struct cpu_functions cortexa_cpufuncs = { * same 'ID' functions for all 3 variations. */ - armv7_tlb_flushID, /* tlb_flushID */ - armv7_tlb_flushID_SE, /* tlb_flushID_SE */ - armv7_tlb_flushID, /* tlb_flushD */ - armv7_tlb_flushID_SE, /* tlb_flushD_SE */ + .cf_tlb_flushID = armv7_tlb_flushID, + .cf_tlb_flushID_SE = armv7_tlb_flushID_SE, + .cf_tlb_flushD = armv7_tlb_flushID, + .cf_tlb_flushD_SE = armv7_tlb_flushID_SE, /* Cache operations */ - - armv7_icache_sync_range, /* icache_sync_range */ - - armv7_dcache_wbinv_all, /* dcache_wbinv_all */ - armv7_dcache_wbinv_range, /* dcache_wbinv_range */ - armv7_dcache_inv_range, /* dcache_inv_range */ - armv7_dcache_wb_range, /* dcache_wb_range */ - - armv7_idcache_inv_all, /* idcache_inv_all */ - armv7_idcache_wbinv_all, /* idcache_wbinv_all */ - armv7_idcache_wbinv_range, /* idcache_wbinv_range */ + .cf_icache_sync_range = armv7_icache_sync_range, + .cf_dcache_wbinv_all = armv7_dcache_wbinv_all, + .cf_dcache_wbinv_range = armv7_dcache_wbinv_range, + .cf_dcache_inv_range = armv7_dcache_inv_range, + .cf_dcache_wb_range = armv7_dcache_wb_range, + .cf_idcache_inv_all = armv7_idcache_inv_all, + .cf_idcache_wbinv_all = armv7_idcache_wbinv_all, + .cf_idcache_wbinv_range = armv7_idcache_wbinv_range, /* * Note: For CPUs using the PL310 the L2 ops are filled in when the * L2 cache controller is actually enabled. */ - cpufunc_nullop, /* l2cache_wbinv_all */ - (void *)cpufunc_nullop, /* l2cache_wbinv_range */ - (void *)cpufunc_nullop, /* l2cache_inv_range */ - (void *)cpufunc_nullop, /* l2cache_wb_range */ - (void *)cpufunc_nullop, /* l2cache_drain_writebuf */ + .cf_l2cache_wbinv_all = cpufunc_nullop, + .cf_l2cache_wbinv_range = (void *)cpufunc_nullop, + .cf_l2cache_inv_range = (void *)cpufunc_nullop, + .cf_l2cache_wb_range = (void *)cpufunc_nullop, + .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop, /* Other functions */ - - armv7_drain_writebuf, /* drain_writebuf */ - - armv7_cpu_sleep, /* sleep */ + .cf_drain_writebuf = armv7_drain_writebuf, + .cf_sleep = armv7_cpu_sleep, /* Soft functions */ - - armv7_context_switch, /* context_switch */ - - cortexa_setup /* cpu setup */ + .cf_context_switch = armv7_context_switch, + .cf_setup = cortexa_setup }; #endif /* CPU_CORTEXA */