- Move the remainder of host controller capability registers reading from
xhci_start_controller() to xhci_init(). These values don't change at run- time so there's no point of acquiring them on every USB_HW_POWER_RESUME instead of only once during initialization. In r276717, reading the first couple of registers in question already had been moved as a prerequisite for the changes in that revision. - Identify ASMedia ASM1042A controllers. - Use NULL instead of 0 for pointers. MFC after: 3 days
This commit is contained in:
Marius Strobl
parent
891c57d8a9
commit
43bc87c459
@ -375,54 +375,12 @@ xhci_start_controller(struct xhci_softc *sc)
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return (USB_ERR_IOERROR);
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}
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if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
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device_printf(sc->sc_bus.parent, "Controller does "
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"not support 4K page size.\n");
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return (USB_ERR_IOERROR);
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}
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
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i = XHCI_HCS1_N_PORTS(temp);
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if (i == 0) {
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device_printf(sc->sc_bus.parent, "Invalid number "
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"of ports: %u\n", i);
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return (USB_ERR_IOERROR);
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}
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sc->sc_noport = i;
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sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
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if (sc->sc_noslot > XHCI_MAX_DEVICES)
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sc->sc_noslot = XHCI_MAX_DEVICES;
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/* set up number of device slots */
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DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
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XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
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XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
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DPRINTF("Max slots: %u\n", sc->sc_noslot);
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
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sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
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if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
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device_printf(sc->sc_bus.parent, "XHCI request "
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"too many scratchpads\n");
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return (USB_ERR_NOMEM);
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}
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DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
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sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
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XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
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temp = XREAD4(sc, oper, XHCI_USBSTS);
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/* clear interrupts */
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@ -454,29 +412,13 @@ xhci_start_controller(struct xhci_softc *sc)
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XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
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XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
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/* Setup event table size */
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
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DPRINTF("HCS2=0x%08x\n", temp);
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temp = XHCI_HCS2_ERST_MAX(temp);
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temp = 1U << temp;
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if (temp > XHCI_MAX_RSEG)
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temp = XHCI_MAX_RSEG;
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sc->sc_erst_max = temp;
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/* set up event table size */
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DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
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XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
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XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
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XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
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XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
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/* Check if we should use the default IMOD value */
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if (sc->sc_imod_default == 0)
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sc->sc_imod_default = XHCI_IMOD_DEFAULT;
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/* Setup interrupt rate */
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/* set up interrupt rate */
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XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
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usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
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@ -503,8 +445,7 @@ xhci_start_controller(struct xhci_softc *sc)
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XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
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XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
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/* Setup interrupter registers */
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/* set up interrupter registers */
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temp = XREAD4(sc, runt, XHCI_IMAN(0));
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temp |= XHCI_IMAN_INTR_ENA;
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XWRITE4(sc, runt, XHCI_IMAN(0), temp);
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@ -615,6 +556,12 @@ xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
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DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
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if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
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device_printf(sc->sc_bus.parent, "Controller does "
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"not support 4K page size.\n");
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return (ENXIO);
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}
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
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DPRINTF("HCS0 = 0x%08x\n", temp);
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@ -633,6 +580,55 @@ xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
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device_printf(self, "%d bytes context size, %d-bit DMA\n",
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sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
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/* get number of device slots */
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sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
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if (sc->sc_noport == 0) {
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device_printf(sc->sc_bus.parent, "Invalid number "
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"of ports: %u\n", sc->sc_noport);
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return (ENXIO);
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}
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sc->sc_noport = sc->sc_noport;
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sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
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DPRINTF("Max slots: %u\n", sc->sc_noslot);
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if (sc->sc_noslot > XHCI_MAX_DEVICES)
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sc->sc_noslot = XHCI_MAX_DEVICES;
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
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DPRINTF("HCS2=0x%08x\n", temp);
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/* get number of scratchpads */
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sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
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if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
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device_printf(sc->sc_bus.parent, "XHCI request "
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"too many scratchpads\n");
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return (ENOMEM);
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}
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DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
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/* get event table size */
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sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
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if (sc->sc_erst_max > XHCI_MAX_RSEG)
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sc->sc_erst_max = XHCI_MAX_RSEG;
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temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
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/* get maximum exit latency */
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sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
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XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
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/* Check if we should use the default IMOD value. */
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if (sc->sc_imod_default == 0)
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sc->sc_imod_default = XHCI_IMOD_DEFAULT;
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/* get all DMA memory */
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if (usb_bus_mem_alloc_all(&sc->sc_bus,
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USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
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@ -86,10 +86,9 @@ static driver_t xhci_driver = {
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static devclass_t xhci_devclass;
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DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, 0, 0);
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DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
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MODULE_DEPEND(xhci, usb, 1, 1, 1);
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static const char *
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xhci_pci_match(device_t self)
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{
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@ -101,6 +100,8 @@ xhci_pci_match(device_t self)
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case 0x10421b21:
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return ("ASMedia ASM1042 USB 3.0 controller");
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case 0x11421b21:
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return ("ASMedia ASM1042A USB 3.0 controller");
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case 0x0f358086:
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return ("Intel Intel BayTrail USB 3.0 controller");
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@ -193,16 +194,28 @@ xhci_pci_attach(device_t self)
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sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
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sc->sc_io_size = rman_get_size(sc->sc_io_res);
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/* check for USB 3.0 controllers which don't support 64-bit DMA */
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switch (pci_get_devid(self)) {
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case 0x01941033: /* NEC uPD720200 USB 3.0 controller */
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/* Don't use 64-bit DMA on these controllers. */
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usedma32 = 1;
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break;
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case 0x0f358086: /* BayTrail */
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case 0x9c318086: /* Panther Point */
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case 0x1e318086: /* Panther Point */
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case 0x8c318086: /* Lynx Point */
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case 0x8cb18086: /* Wildcat Point */
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/*
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* On Intel chipsets, reroute ports from EHCI to XHCI
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* controller and use a different IMOD value.
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*/
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sc->sc_port_route = &xhci_pci_port_route;
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sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
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/* FALLTHROUGH */
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default:
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usedma32 = 0;
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break;
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}
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if (xhci_init(sc, self, usedma32)) {
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device_printf(self, "Could not initialize softc\n");
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bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
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@ -261,20 +274,6 @@ xhci_pci_attach(device_t self)
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goto error;
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}
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/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
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switch (pci_get_devid(self)) {
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case 0x0f358086: /* BayTrail */
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case 0x9c318086: /* Panther Point */
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case 0x1e318086: /* Panther Point */
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case 0x8c318086: /* Lynx Point */
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case 0x8cb18086: /* Wildcat Point */
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sc->sc_port_route = &xhci_pci_port_route;
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sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
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break;
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default:
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break;
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}
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xhci_pci_take_controller(self);
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err = xhci_halt_controller(sc);
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