Add support for MSI-X interrupts in the virtio block device and make that
the default. The current behavior of advertising a single MSI vector can be requested by setting the environment variable "BHYVE_USE_MSI" to "yes". The use of MSI is not compliant with the virtio specification and will be eventually phased out. Submitted by: Gopakumar T Obtained from: NetApp
This commit is contained in:
Neel Natu
parent
dd6035234a
commit
445e089e21
@ -55,7 +55,7 @@ __FBSDID("$FreeBSD$");
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#define VTBLK_CFGSZ 28
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#define VTBLK_R_CFG VTCFG_R_CFG0
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#define VTBLK_R_CFG VTCFG_R_CFG1
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#define VTBLK_R_CFG_END VTBLK_R_CFG + VTBLK_CFGSZ -1
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#define VTBLK_R_MAX VTBLK_R_CFG_END
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@ -73,6 +73,8 @@ __FBSDID("$FreeBSD$");
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( 0x00000004 | /* host maximum request segments */ \
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0x10000000 ) /* supports indirect descriptors */
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static int use_msix = 1;
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struct vring_hqueue {
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/* Internal state */
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uint16_t hq_size;
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@ -135,8 +137,25 @@ struct pci_vtblk_softc {
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uint64_t vbsc_pfn;
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struct vring_hqueue vbsc_q;
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struct vtblk_config vbsc_cfg;
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uint16_t msix_table_idx_req;
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uint16_t msix_table_idx_cfg;
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};
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/*
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* Return the size of IO BAR that maps virtio header and device specific
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* region. The size would vary depending on whether MSI-X is enabled or
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* not
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*/
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static uint64_t
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pci_vtblk_iosize(struct pci_devinst *pi)
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{
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if (pci_msix_enabled(pi))
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return (VTBLK_REGSZ);
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else
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return (VTBLK_REGSZ - (VTCFG_R_CFG1 - VTCFG_R_MSIX));
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}
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/*
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* Return the number of available descriptors in the vring taking care
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* of the 16-bit index wraparound.
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@ -290,11 +309,14 @@ pci_vtblk_qnotify(struct pci_vtblk_softc *sc)
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/*
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* Generate an interrupt if able
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*/
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if ((*hq->hq_avail_flags & VRING_AVAIL_F_NO_INTERRUPT) == 0 &&
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sc->vbsc_isr == 0) {
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if ((*hq->hq_avail_flags & VRING_AVAIL_F_NO_INTERRUPT) == 0) {
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if (use_msix) {
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pci_generate_msix(sc->vbsc_pi, sc->msix_table_idx_req);
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} else if (sc->vbsc_isr == 0) {
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sc->vbsc_isr = 1;
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pci_generate_msi(sc->vbsc_pi, 0);
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}
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}
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}
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@ -335,6 +357,7 @@ pci_vtblk_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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off_t size;
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int fd;
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int sectsz;
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const char *env_msi;
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if (opts == NULL) {
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printf("virtio-block: backing device required\n");
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@ -401,26 +424,68 @@ pci_vtblk_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
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pci_set_cfgdata16(pi, PCIR_VENDOR, VIRTIO_VENDOR);
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pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
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pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_TYPE_BLOCK);
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if ((env_msi = getenv("BHYVE_USE_MSI"))) {
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if (strcasecmp(env_msi, "yes") == 0)
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use_msix = 0;
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}
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if (use_msix) {
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/* MSI-X Support */
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sc->msix_table_idx_req = VIRTIO_MSI_NO_VECTOR;
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sc->msix_table_idx_cfg = VIRTIO_MSI_NO_VECTOR;
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if (pci_emul_add_msixcap(pi, 2, 1))
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return (1);
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} else {
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/* MSI Support */
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pci_emul_add_msicap(pi, 1);
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}
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pci_emul_alloc_bar(pi, 0, PCIBAR_IO, VTBLK_REGSZ);
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return (0);
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}
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static uint64_t
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vtblk_adjust_offset(struct pci_devinst *pi, uint64_t offset)
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{
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/*
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* Device specific offsets used by guest would change
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* based on whether MSI-X capability is enabled or not
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*/
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if (!pci_msix_enabled(pi)) {
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if (offset >= VTCFG_R_MSIX)
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return (offset + (VTCFG_R_CFG1 - VTCFG_R_MSIX));
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}
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return (offset);
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}
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static void
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pci_vtblk_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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int baridx, uint64_t offset, int size, uint64_t value)
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{
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struct pci_vtblk_softc *sc = pi->pi_arg;
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if (use_msix) {
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if (baridx == pci_msix_table_bar(pi) ||
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baridx == pci_msix_pba_bar(pi)) {
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pci_emul_msix_twrite(pi, offset, size, value);
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return;
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}
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}
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assert(baridx == 0);
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if (offset + size > VTBLK_REGSZ) {
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if (offset + size > pci_vtblk_iosize(pi)) {
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DPRINTF(("vtblk_write: 2big, offset %ld size %d\n",
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offset, size));
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return;
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}
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offset = vtblk_adjust_offset(pi, offset);
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switch (offset) {
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case VTCFG_R_GUESTCAP:
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assert(size == 4);
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@ -443,6 +508,14 @@ pci_vtblk_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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assert(size == 1);
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pci_vtblk_update_status(sc, value);
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break;
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case VTCFG_R_CFGVEC:
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assert(size == 2);
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sc->msix_table_idx_cfg = value;
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break;
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case VTCFG_R_QVEC:
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assert(size == 2);
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sc->msix_table_idx_req = value;
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break;
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case VTCFG_R_HOSTCAP:
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case VTCFG_R_QNUM:
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case VTCFG_R_ISR:
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@ -464,14 +537,23 @@ pci_vtblk_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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void *ptr;
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uint32_t value;
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if (use_msix) {
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if (baridx == pci_msix_table_bar(pi) ||
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baridx == pci_msix_pba_bar(pi)) {
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return (pci_emul_msix_tread(pi, offset, size));
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}
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}
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assert(baridx == 0);
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if (offset + size > VTBLK_REGSZ) {
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if (offset + size > pci_vtblk_iosize(pi)) {
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DPRINTF(("vtblk_read: 2big, offset %ld size %d\n",
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offset, size));
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return (0);
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}
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offset = vtblk_adjust_offset(pi, offset);
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switch (offset) {
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case VTCFG_R_HOSTCAP:
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assert(size == 4);
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@ -505,6 +587,14 @@ pci_vtblk_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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value = sc->vbsc_isr;
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sc->vbsc_isr = 0; /* a read clears this flag */
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break;
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case VTCFG_R_CFGVEC:
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assert(size == 2);
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value = sc->msix_table_idx_cfg;
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break;
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case VTCFG_R_QVEC:
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assert(size == 2);
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value = sc->msix_table_idx_req;
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break;
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case VTBLK_R_CFG ... VTBLK_R_CFG_END:
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assert(size + offset <= (VTBLK_R_CFG_END + 1));
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ptr = (uint8_t *)&sc->vbsc_cfg + offset - VTBLK_R_CFG;
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