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SMP support in n64.

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- Enable KX and UX bits on CPU startup for non-boot CPUs
- Keep the KX bit when in userspace - XTLB handler needs it to access
  PCPU data
- revert r210638 partly - we don't need to enable KX on kernel entry
  now

Reviewed by:	jmallett, imp
This commit is contained in:
jchandra 2010-08-12 11:00:45 +00:00
parent dd04fae403
commit 4478273e0a
4 changed files with 10 additions and 17 deletions
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16
sys/mips/mips/exception.S
View File

@ -434,12 +434,6 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
/*
* Save all of the registers except for the kernel temporaries in u.u_pcb.
*/
mfc0 k0, MIPS_COP_0_STATUS
HAZARD_DELAY
#ifdef __mips_n64
ori k1, k0, MIPS_SR_KX
mtc0 k1, MIPS_COP_0_STATUS
#endif
GET_CPU_PCPU(k1)
PTR_L k1, PC_CURPCB(k1)
SAVE_U_PCB_REG(AT, AST, k1)
@ -457,7 +451,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
SAVE_U_PCB_REG(t2, T2, k1)
SAVE_U_PCB_REG(t3, T3, k1)
SAVE_U_PCB_REG(ta0, TA0, k1)
move a0, k0 # First arg is the status reg.
mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg.
SAVE_U_PCB_REG(ta1, TA1, k1)
SAVE_U_PCB_REG(ta2, TA2, k1)
SAVE_U_PCB_REG(ta3, TA3, k1)
@ -656,12 +650,6 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
* Save the relevant user registers into the u.u_pcb struct.
* We don't need to save s0 - s8 because the compiler does it for us.
*/
mfc0 k0, MIPS_COP_0_STATUS
HAZARD_DELAY
#ifdef __mips_n64
ori k1, k0, MIPS_SR_KX
mtc0 k1, MIPS_COP_0_STATUS
#endif
GET_CPU_PCPU(k1)
PTR_L k1, PC_CURPCB(k1)
SAVE_U_PCB_REG(AT, AST, k1)
@ -700,7 +688,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
mflo v0 # get lo/hi late to avoid stall
mfhi v1
move a0, k0
mfc0 a0, MIPS_COP_0_STATUS
mfc0 a1, MIPS_COP_0_CAUSE
MFC0 a3, MIPS_COP_0_EXC_PC
SAVE_U_PCB_REG(v0, MULLO, k1)

7
sys/mips/mips/mpboot.S
View File

@ -36,7 +36,8 @@
.set noat
.set noreorder
#ifdef CPU_CNMIPS
/* XXX move this to a header file */
#if defined(CPU_CNMIPS)
#define CLEAR_STATUS \
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
@ -44,6 +45,10 @@
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV) ; \
and a0, a0, a2 ; \
mtc0 a0, MIPS_COP_0_STATUS
#elif defined(__mips_n64)
#define CLEAR_STATUS \
li a0, (MIPS_SR_KX | MIPS_SR_UX) ; \
mtc0 a0, MIPS_COP_0_STATUS
#else
#define CLEAR_STATUS \
mtc0 zero, MIPS_COP_0_STATUS

2
sys/mips/mips/pm_machdep.c
View File

@ -517,7 +517,7 @@ exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
#if defined(__mips_n32)
td->td_frame->sr |= MIPS_SR_PX;
#elif defined(__mips_n64)
td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX;
td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
#endif
#ifdef CPU_CNMIPS
td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX |

2
sys/mips/mips/vm_machdep.c
View File

@ -419,7 +419,7 @@ cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
#if defined(__mips_n32)
td->td_frame->sr |= MIPS_SR_PX;
#elif defined(__mips_n64)
td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX;
td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
#endif
#ifdef CPU_CNMIPS
tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX |