There's apparently a bug with Merlin (AR9280) and later chipsets where
putting descriptors (not buffers) across a 4k page boundary can cause issues. I've not seen it in production myself but it apparently can cause problems. So, in preparation for addressing this workaround, (re)-expose the particular HAL capability bit which marks whether the chipset has support for cross-4k- boundary transactions or not. A subsequent commit will modify the descriptor allocation to avoid allocating descriptor entries that straddle a 4k page boundary.
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@ -195,7 +195,8 @@ typedef struct {
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halForcePpmSupport : 1,
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halEnhancedPmSupport : 1,
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halMbssidAggrSupport : 1,
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halBssidMatchSupport : 1;
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halBssidMatchSupport : 1,
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hal4kbSplitTransSupport : 1;
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uint32_t halWirelessModes;
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uint16_t halTotalQueues;
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uint16_t halKeyCacheSize;
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@ -377,6 +377,8 @@ ar5210FillCapabilityInfo(struct ath_hal *ah)
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| HAL_INT_FATAL
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;
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pCap->hal4kbSplitTransSupport = AH_TRUE;
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ahpriv->ah_rxornIsFatal = AH_TRUE;
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return AH_TRUE;
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}
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@ -509,6 +509,8 @@ ar5211FillCapabilityInfo(struct ath_hal *ah)
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| HAL_INT_TIM
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;
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pCap->hal4kbSplitTransSupport = AH_TRUE;
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/* XXX might be ok w/ some chip revs */
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ahpriv->ah_rxornIsFatal = AH_TRUE;
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return AH_TRUE;
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@ -860,6 +860,8 @@ ar5212FillCapabilityInfo(struct ath_hal *ah)
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if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN)
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pCap->halIntrMask &= ~HAL_INT_TBTT;
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pCap->hal4kbSplitTransSupport = AH_TRUE;
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return AH_TRUE;
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#undef IS_COBRA
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#undef IS_GRIFFIN_LITE
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@ -698,9 +698,7 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
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pCap->halBtCoexSupport = AH_TRUE;
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#endif
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pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
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#if 0
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pCap->hal4kbSplitTransSupport = AH_FALSE;
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#endif
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pCap->halRxStbcSupport = 1;
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pCap->halTxStbcSupport = 1;
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@ -384,9 +384,7 @@ ar9285FillCapabilityInfo(struct ath_hal *ah)
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pCap->halBtCoexSupport = AH_TRUE;
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#endif
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pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
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#if 0
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pCap->hal4kbSplitTransSupport = AH_FALSE;
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#endif
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pCap->halRxStbcSupport = 1;
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pCap->halTxStbcSupport = 1;
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