Implement workaround for broken busfree-rev in the A4.
HP -> CPQ Rearrange IDs to better match which chips they use. Convert to uniform product description strings. Simplify 7901A setup function. Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries for the A. Add rev B bugs and features. The double write workaround for CURRSCB is only required if abort pending is set. Remove this work around and set the abort pending bug bit on the B at least until we have better confirmation that the double write is always safe. Add updated H2B identifiers Move IOCell paramters into softc and add a hook for the OSM to modify these as well as other settings prior to committing them to the chip. SLEW -> SLEWRATE PREQDIS in DEVCONFIG1 went away after the A2. Remove all code that references this bit. This is especially important since this bit was reused in the B for a different HW fix workaround. Properly set the AHD_NEW_IOCELL_OPTS and AHD_NEW_DFCNTRL_OPTS features for the B. Remove stray/random extra 7901A generic PCI table entry. Also switch the correct 7901A generic entry to use ID_ALL_MASK since we can only differentiate the 7901A from the 7902 by checking for a "type field" of 0xE. Set AHD_INTCOLLISIONT_BUG for the Rev B. Set the PREQDIS bit in DEVCONFIG1 for the B. The bit is misnamed, but seems to disable a work-around that breaks on the B on PCI busses. Add a routine for testing memory mapped register access. This will hopefully detect things like buggy via chipsets so that the OSM can fallback to using I/O mapped access when memory mapped I/O simply will not work. Approved by: re (blanket)
This commit is contained in:
scottl
parent
30b77bf780
commit
45781e3228
@ -38,7 +38,7 @@
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#44 $
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* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#54 $
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*
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* $FreeBSD$
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*/
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@ -69,21 +69,26 @@ ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
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#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
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#define ID_AIC7901 0x800F9005FFFF9005ull
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#define ID_AIC7901_IROC 0x80089005FFFF9005ull
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#define ID_AIC7901A 0x801E9005FFFF9005ull
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#define ID_AIC7901A_IROC 0x809E9005FFFF9005ull
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#define ID_AHA_29320A 0x8000900500609005ull
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#define ID_AHA_29320LP 0x8014900500449005ull
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#define ID_AHA_29320LP_IROC 0x8094900500449005ull
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#define ID_AIC7902 0x801F9005FFFF9005ull
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#define ID_AIC7902_IROC 0x80189005FFFF9005ull
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#define ID_AIC7902_IROC 0x809F9005FFFF9005ull
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#define ID_AIC7902_B 0x801D9005FFFF9005ull
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#define ID_AIC7902_B_IROC 0x809D9005FFFF9005ull
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#define ID_AHA_39320 0x8010900500409005ull
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#define ID_AHA_39320D 0x8011900500419005ull
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#define ID_AHA_39320D_CPQ 0x8011900500AC0E11ull
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#define ID_AHA_39320D_B 0x801C900500419005ull
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#define ID_AHA_39320D_HP 0x8011900500AC0E11ull
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#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
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#define ID_AHA_29320 0x8012900500429005ull
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#define ID_AHA_29320B 0x8013900500439005ull
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#define ID_AHA_29320LP 0x8014900500449005ull
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#define ID_AIC7902_PCI_REV_A4 0x3
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#define ID_AIC7902_PCI_REV_B0 0x10
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#define SUBID_CPQ 0x0E11
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#define SUBID_HP 0x0E11
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#define DEVID_9005_TYPE(id) ((id) & 0xF)
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#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
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@ -107,18 +112,23 @@ ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
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#define SUBID_9005_SEEPTYPE_NONE 0x0
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#define SUBID_9005_SEEPTYPE_4K 0x1
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static ahd_device_setup_t ahd_aic7901_setup;
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static ahd_device_setup_t ahd_aic7902_setup;
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static ahd_device_setup_t ahd_aic7901A_setup;
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static ahd_device_setup_t ahd_aic7902_setup;
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struct ahd_pci_identity ahd_pci_ident_table [] =
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{
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/* aic7901 based controllers */
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/* aic7901A based controllers */
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{
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ID_AHA_29320LP,
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ID_ALL_MASK,
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"Adaptec 29320LP Ultra320 SCSI adapter",
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ahd_aic7901A_setup
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},
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{
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ID_AHA_29320A,
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ID_ALL_MASK,
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"Adaptec 29320A Ultra320 SCSI adapter",
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ahd_aic7901_setup
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ahd_aic7901A_setup
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},
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/* aic7902 based controllers */
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{
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@ -134,9 +144,21 @@ struct ahd_pci_identity ahd_pci_ident_table [] =
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ahd_aic7902_setup
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},
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{
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ID_AHA_39320D_CPQ,
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ID_AHA_39320D_HP,
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ID_ALL_MASK,
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"Adaptec (Compaq OEM) 39320D Ultra320 SCSI adapter",
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"Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
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ahd_aic7902_setup
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},
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{
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ID_AHA_39320D_B,
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ID_ALL_MASK,
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"Adaptec 39320D Ultra320 SCSI adapter",
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ahd_aic7902_setup
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},
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{
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ID_AHA_39320D_B_HP,
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ID_ALL_MASK,
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"Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
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ahd_aic7902_setup
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},
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{
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@ -151,29 +173,17 @@ struct ahd_pci_identity ahd_pci_ident_table [] =
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"Adaptec 29320B Ultra320 SCSI adapter",
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ahd_aic7902_setup
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},
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{
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ID_AHA_29320LP,
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ID_ALL_MASK,
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"Adaptec 29320LP Ultra320 SCSI adapter",
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ahd_aic7902_setup
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},
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{
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ID_AIC7901A & ID_9005_GENERIC_MASK,
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ID_9005_GENERIC_MASK,
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"Adaptec 7901A Ultra320 SCSI adapter",
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ahd_aic7901A_setup
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},
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/* Generic chip probes for devices we don't know 'exactly' */
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{
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ID_AIC7901 & ID_9005_GENERIC_MASK,
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ID_9005_GENERIC_MASK,
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"Adaptec aic7901 Ultra320 SCSI adapter",
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ahd_aic7901_setup
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ID_AIC7901A & ID_ALL_MASK,
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ID_ALL_MASK,
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"Adaptec AIC7901A Ultra320 SCSI adapter",
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ahd_aic7901A_setup
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},
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{
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ID_AIC7902 & ID_9005_GENERIC_MASK,
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ID_9005_GENERIC_MASK,
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"Adaptec aic7902 Ultra320 SCSI adapter",
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"Adaptec AIC7902 Ultra320 SCSI adapter",
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ahd_aic7902_setup
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}
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};
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@ -266,11 +276,19 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
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int error;
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shared_scb_data = NULL;
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ahd->description = entry->name;
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/*
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* Record if this is an HP board.
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*/
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subvendor = ahd_pci_read_config(ahd->dev_softc,
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PCIR_SUBVEND_0, /*bytes*/2);
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if (subvendor == SUBID_HP)
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ahd->flags |= AHD_HP_BOARD;
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error = entry->setup(ahd);
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if (error != 0)
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return (error);
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ahd->description = entry->name;
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devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
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if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
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ahd->chip |= AHD_PCI;
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@ -281,14 +299,6 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
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}
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ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
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/*
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* Record if this is a Compaq board.
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*/
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subvendor = ahd_pci_read_config(ahd->dev_softc,
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PCIR_SUBVEND_0, /*bytes*/2);
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if (subvendor == SUBID_CPQ)
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ahd->flags |= AHD_CPQ_BOARD;
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ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
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error = ahd_pci_map_registers(ahd);
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@ -361,6 +371,64 @@ ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
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return (0);
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}
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/*
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* Perform some simple tests that should catch situations where
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* our registers are invalidly mapped.
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*/
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int
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ahd_pci_test_register_access(struct ahd_softc *ahd)
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{
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int i;
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/*
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* First a simple test to see if any
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* registers can be read. Reading
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* HCNTRL has no side effects and has
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* at least one bit that is guaranteed to
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* be zero so it is a good register to
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* use for this test.
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*/
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if (ahd_inb(ahd, HCNTRL) == 0xFF)
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return (EIO);
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/*
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* Next create a situation where write combining
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* or read prefetching could be initiated by the
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* CPU or host bridge. Our device does not support
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* either, so look for data corruption and/or flaged
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* PCI errors.
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*/
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for (i = 0; i < 16; i++)
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ahd_outb(ahd, SRAM_BASE + i, i);
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for (i = 0; i < 16; i++)
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if (ahd_inb(ahd, SRAM_BASE + i) != i)
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return (EIO);
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if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
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ahd_mode_state saved_modes;
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u_int targpcistat;
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u_int pci_status1;
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saved_modes = ahd_save_modes(ahd);
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ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
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targpcistat = ahd_inb(ahd, TARGPCISTAT);
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/* Silently clear any latched errors. */
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ahd_outb(ahd, TARGPCISTAT, targpcistat);
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pci_status1 = ahd_pci_read_config(ahd->dev_softc,
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PCIR_STATUS + 1, /*bytes*/1);
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ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
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pci_status1, /*bytes*/1);
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ahd_restore_modes(ahd, saved_modes);
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if ((targpcistat & STA) != 0)
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return (EIO);
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}
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return (0);
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}
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/*
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* Check the external port logic for a serial eeprom
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* and termination/cable detection contrls.
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@ -745,63 +813,6 @@ ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
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ahd_restore_modes(ahd, saved_modes);
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}
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static int
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ahd_aic7901_setup(struct ahd_softc *ahd)
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{
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ahd_dev_softc_t pci;
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pci = ahd->dev_softc;
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ahd->channel = 'A';
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ahd->chip = AHD_AIC7901;
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ahd->features = AHD_AIC7901_FE;
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return (0);
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}
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static int
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ahd_aic7902_setup(struct ahd_softc *ahd)
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{
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ahd_dev_softc_t pci;
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u_int rev;
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u_int devconfig1;
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pci = ahd->dev_softc;
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rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
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if (rev < ID_AIC7902_PCI_REV_A4) {
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printf("%s: Unable to attach to unsupported chip revision %d\n",
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ahd_name(ahd), rev);
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ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1);
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return (ENXIO);
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}
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if (rev < ID_AIC7902_PCI_REV_B0) {
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/*
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* Pending request assertion does not work on the A if we have
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* DMA requests outstanding on both channels. See H2A3 Razors
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* #327 and #365.
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*/
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devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
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ahd_pci_write_config(pci, DEVCONFIG1,
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devconfig1|PREQDIS, /*bytes*/1);
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devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
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/*
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* Enable A series workarounds.
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*/
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ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
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| AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
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| AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
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| AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
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| AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
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| AHD_PCIX_CHIPRST_BUG|AHD_PKTIZED_STATUS_BUG
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| AHD_PKT_LUN_BUG|AHD_MDFF_WSCBPTR_BUG
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| AHD_REG_SLOW_SETTLE_BUG|AHD_SET_MODE_BUG
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| AHD_BUSFREEREV_BUG;
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}
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ahd->channel = ahd_get_pci_function(pci) + 'A';
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ahd->chip = AHD_AIC7902;
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ahd->features = AHD_AIC7902_FE;
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return (0);
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}
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static int
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ahd_aic7901A_setup(struct ahd_softc *ahd)
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{
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@ -814,3 +825,71 @@ ahd_aic7901A_setup(struct ahd_softc *ahd)
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return (0);
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}
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static int
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ahd_aic7902_setup(struct ahd_softc *ahd)
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{
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ahd_dev_softc_t pci;
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u_int rev;
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pci = ahd->dev_softc;
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rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
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if (rev < ID_AIC7902_PCI_REV_A4) {
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printf("%s: Unable to attach to unsupported chip revision %d\n",
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ahd_name(ahd), rev);
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ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1);
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return (ENXIO);
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}
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ahd->channel = ahd_get_pci_function(pci) + 'A';
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ahd->chip = AHD_AIC7902;
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ahd->features = AHD_AIC7902_FE;
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if (rev < ID_AIC7902_PCI_REV_B0) {
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/*
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* Enable A series workarounds.
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*/
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ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
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| AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
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| AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
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| AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
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| AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
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| AHD_PCIX_CHIPRST_BUG|AHD_PKTIZED_STATUS_BUG
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| AHD_PKT_LUN_BUG|AHD_MDFF_WSCBPTR_BUG
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| AHD_REG_SLOW_SETTLE_BUG|AHD_SET_MODE_BUG
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| AHD_BUSFREEREV_BUG|AHD_NONPACKFIFO_BUG
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| AHD_PACED_NEGTABLE_BUG;
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/*
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* IO Cell paramter setup.
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*/
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AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
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if ((ahd->flags & AHD_HP_BOARD) == 0)
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AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
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} else {
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u_int devconfig1;
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ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
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| AHD_NEW_DFCNTRL_OPTS;
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ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG
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| AHD_INTCOLLISION_BUG;
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/*
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* IO Cell paramter setup.
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*/
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AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
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AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
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AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
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/*
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* Set the PREQDIS bit for H2B which disables some workaround
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* that doesn't work on regular PCI busses.
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* XXX - Find out exactly what this does from the hardware
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* folks!
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*/
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devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
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ahd_pci_write_config(pci, DEVCONFIG1,
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devconfig1|PREQDIS, /*bytes*/1);
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devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
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}
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return (0);
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}
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