From 46d854bbdb2c3705d7e0ccf5a837719c14b28df7 Mon Sep 17 00:00:00 2001
From: Warner Losh <imp@FreeBSD.org>
Date: Sun, 5 Jul 2009 15:19:28 +0000
Subject: [PATCH] The SB1 needs a special value for the cache field of the pte.

Submitted by:	Neelkanth Natu
---
 sys/mips/include/pte.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sys/mips/include/pte.h b/sys/mips/include/pte.h
index aa7e839c4393..db26cbb0929d 100644
--- a/sys/mips/include/pte.h
+++ b/sys/mips/include/pte.h
@@ -105,7 +105,11 @@ typedef pt_entry_t *pd_entry_t;
 #define PTE_ODDPG       0x00001000 
 /*#define	PG_ATTR		0x0000003f  Not Used */
 #define	PTE_UNCACHED	0x00000010
+#ifdef CPU_SB1
+#define	PTE_CACHE	0x00000028	/* cacheable coherent */
+#else
 #define	PTE_CACHE	0x00000018
+#endif
 /*#define	PG_CACHEMODE	0x00000038 Not Used*/
 #define	PTE_ROPAGE	(PTE_V | PTE_RO | PTE_CACHE) /* Write protected */
 #define	PTE_RWPAGE	(PTE_V | PTE_M | PTE_CACHE)  /* Not wr-prot not clean */