Fix the same race condition on 32-bit AIM CPUs that was fixed for 64-bit
ones in r211967 involving VSID allocation.
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212ac5b8db
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@ -203,6 +203,7 @@ extern struct pmap ofw_pmap;
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* Lock for the pteg and pvo tables.
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*/
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struct mtx moea_table_mutex;
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struct mtx moea_vsid_mutex;
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/* tlbie instruction synchronization */
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static struct mtx tlbie_mtx;
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@ -819,6 +820,7 @@ moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
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*/
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mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
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MTX_RECURSE);
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mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
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mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
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@ -1589,6 +1591,7 @@ moea_pinit(mmu_t mmu, pmap_t pmap)
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}
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mtx_lock(&moea_vsid_mutex);
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/*
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* Allocate some segment registers for this pmap.
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*/
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@ -1623,9 +1626,11 @@ moea_pinit(mmu_t mmu, pmap_t pmap)
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moea_vsid_bitmap[n] |= mask;
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for (i = 0; i < 16; i++)
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pmap->pm_sr[i] = VSID_MAKE(i, hash);
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mtx_unlock(&moea_vsid_mutex);
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return;
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}
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mtx_unlock(&moea_vsid_mutex);
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panic("moea_pinit: out of segments");
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}
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@ -1737,10 +1742,12 @@ moea_release(mmu_t mmu, pmap_t pmap)
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if (pmap->pm_sr[0] == 0)
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panic("moea_release");
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mtx_lock(&moea_vsid_mutex);
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idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
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mask = 1 << (idx % VSID_NBPW);
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idx /= VSID_NBPW;
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moea_vsid_bitmap[idx] &= ~mask;
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mtx_unlock(&moea_vsid_mutex);
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PMAP_LOCK_DESTROY(pmap);
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}
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