Always disable ASPM L0s and enable L1 before entering into WOL
suspend state. Also disable master clock after PHY power down, this is supposed to save more power. The master clock should be enabled if WOL is active.
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@ -1673,19 +1673,14 @@ static void
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alc_setwol(struct alc_softc *sc)
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{
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struct ifnet *ifp;
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uint32_t cap, reg, pmcs;
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uint32_t reg, pmcs;
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uint16_t pmstat;
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int base, pmc;
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int pmc;
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ALC_LOCK_ASSERT(sc);
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if (pci_find_extcap(sc->alc_dev, PCIY_EXPRESS, &base) == 0) {
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cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP);
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if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
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cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL);
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alc_disable_l0s_l1(sc);
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}
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}
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alc_disable_l0s_l1(sc);
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ifp = sc->alc_ifp;
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if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) != 0) {
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/* Disable WOL. */
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CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
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@ -1694,6 +1689,8 @@ alc_setwol(struct alc_softc *sc)
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CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
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/* Force PHY power down. */
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alc_phy_down(sc);
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CSR_WRITE_4(sc, ALC_MASTER_CFG,
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CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
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return;
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}
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@ -1701,9 +1698,8 @@ alc_setwol(struct alc_softc *sc)
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if ((ifp->if_capenable & IFCAP_WOL) != 0) {
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if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
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alc_setlinkspeed(sc);
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reg = CSR_READ_4(sc, ALC_MASTER_CFG);
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reg &= ~MASTER_CLK_SEL_DIS;
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CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
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CSR_WRITE_4(sc, ALC_MASTER_CFG,
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CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS);
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}
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pmcs = 0;
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@ -1725,6 +1721,8 @@ alc_setwol(struct alc_softc *sc)
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if ((ifp->if_capenable & IFCAP_WOL) == 0) {
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/* WOL disabled, PHY power down. */
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alc_phy_down(sc);
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CSR_WRITE_4(sc, ALC_MASTER_CFG,
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CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
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}
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/* Request PME. */
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pmstat = pci_read_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, 2);
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