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Handle instruction access mmu miss faults in kernel mode. These can only

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be generated by non-preloaded klds.
This commit is contained in:
jake 2001-10-27 07:06:15 +00:00
parent 33a3c39de3
commit 48d949bee1
3 changed files with 95 additions and 2 deletions
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48
sys/sparc64/sparc64/exception.S
View File

@ -388,6 +388,7 @@ ENTRY(tl0_sfsr_trap)
stx %g4, [%g3 + KTR_PARM1]
ldx [%sp + SPOFF + CCFSZ + MF_TAR], %g4
stx %g4, [%g3 + KTR_PARM1]
9:
#endif
rdpr %pil, %o2
add %sp, SPOFF + CCFSZ, %o1
@ -1107,9 +1108,54 @@ ENTRY(intr_enqueue)
END(intr_enqueue)
.macro tl1_immu_miss
wrpr %g0, PSTATE_ALT, %pstate
ldxa [%g0] ASI_IMMU_TAG_TARGET_REG, %g1
sllx %g1, TT_VA_SHIFT - (PAGE_SHIFT - STTE_SHIFT), %g2
set TSB_KERNEL_VA_MASK, %g3
and %g2, %g3, %g2
ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g4
sllx %g4, STTE_SHIFT - TTE_SHIFT, %g4
add %g2, %g4, %g2
/*
* Load the tte, check that it's valid and that the tags match.
*/
ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 /*, %g5 */
brgez,pn %g5, 2f
cmp %g4, %g1
bne %xcc, 2f
andcc %g5, TD_EXEC, %g0
bz %xcc, 2f
EMPTY
/*
* Set the refence bit, if its currently clear.
*/
andcc %g5, TD_REF, %g0
bnz %xcc, 1f
or %g5, TD_REF, %g1
stx %g1, [%g2 + ST_TTE + TTE_DATA]
/*
* Load the tte data into the TLB and retry the instruction.
*/
1: stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG
retry
/*
* Switch to alternate globals.
*/
2: wrpr %g0, PSTATE_ALT, %pstate
wr %g0, ASI_IMMU, %asi
ldxa [%g0 + AA_IMMU_TAR] %asi, %g1
tl1_kstack
sub %sp, MF_SIZEOF, %sp
stx %g1, [%sp + SPOFF + CCFSZ + MF_TAR]
rdpr %pil, %o2
add %sp, SPOFF + CCFSZ, %o1
b %xcc, tl1_trap
mov T_IMMU_MISS | T_KERNEL, %o0
.align 128

48
sys/sparc64/sparc64/exception.s
View File

@ -388,6 +388,7 @@ ENTRY(tl0_sfsr_trap)
stx %g4, [%g3 + KTR_PARM1]
ldx [%sp + SPOFF + CCFSZ + MF_TAR], %g4
stx %g4, [%g3 + KTR_PARM1]
9:
#endif
rdpr %pil, %o2
add %sp, SPOFF + CCFSZ, %o1
@ -1107,9 +1108,54 @@ ENTRY(intr_enqueue)
END(intr_enqueue)
.macro tl1_immu_miss
wrpr %g0, PSTATE_ALT, %pstate
ldxa [%g0] ASI_IMMU_TAG_TARGET_REG, %g1
sllx %g1, TT_VA_SHIFT - (PAGE_SHIFT - STTE_SHIFT), %g2
set TSB_KERNEL_VA_MASK, %g3
and %g2, %g3, %g2
ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g4
sllx %g4, STTE_SHIFT - TTE_SHIFT, %g4
add %g2, %g4, %g2
/*
* Load the tte, check that it's valid and that the tags match.
*/
ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 /*, %g5 */
brgez,pn %g5, 2f
cmp %g4, %g1
bne %xcc, 2f
andcc %g5, TD_EXEC, %g0
bz %xcc, 2f
EMPTY
/*
* Set the refence bit, if its currently clear.
*/
andcc %g5, TD_REF, %g0
bnz %xcc, 1f
or %g5, TD_REF, %g1
stx %g1, [%g2 + ST_TTE + TTE_DATA]
/*
* Load the tte data into the TLB and retry the instruction.
*/
1: stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG
retry
/*
* Switch to alternate globals.
*/
2: wrpr %g0, PSTATE_ALT, %pstate
wr %g0, ASI_IMMU, %asi
ldxa [%g0 + AA_IMMU_TAR] %asi, %g1
tl1_kstack
sub %sp, MF_SIZEOF, %sp
stx %g1, [%sp + SPOFF + CCFSZ + MF_TAR]
rdpr %pil, %o2
add %sp, SPOFF + CCFSZ, %o1
b %xcc, tl1_trap
mov T_IMMU_MISS | T_KERNEL, %o0
.align 128

1
sys/sparc64/sparc64/trap.c
View File

@ -253,6 +253,7 @@ trap(struct trapframe *tf)
#endif
case T_DMMU_MISS | T_KERNEL:
case T_DMMU_PROT | T_KERNEL:
case T_IMMU_MISS | T_KERNEL:
error = trap_mmu_fault(td, tf);
if (error == 0)
goto out;