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MFC r275833:

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The iret instruction may generate #np and #ss fault, besides #gp.
When returning to usermode, the handler for that exceptions is also
executed with wrong gs base.  Handle all three possible faults in the
same way, checking for iret fault, and performing full iret.
This commit is contained in:
kib 2014-12-19 09:36:59 +00:00
parent bf07138622
commit 492a1d38b5
1 changed files with 7 additions and 2 deletions
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9
sys/amd64/amd64/exception.S
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@ -154,9 +154,13 @@ IDTVEC(xmm)
IDTVEC(tss)
TRAP_ERR(T_TSSFLT)
IDTVEC(missing)
TRAP_ERR(T_SEGNPFLT)
subq $TF_ERR,%rsp
movl $T_SEGNPFLT,TF_TRAPNO(%rsp)
jmp prot_addrf
IDTVEC(stk)
TRAP_ERR(T_STKFLT)
subq $TF_ERR,%rsp
movl $T_STKFLT,TF_TRAPNO(%rsp)
jmp prot_addrf
IDTVEC(align)
TRAP_ERR(T_ALIGNFLT)
@ -319,6 +323,7 @@ IDTVEC(page)
IDTVEC(prot)
subq $TF_ERR,%rsp
movl $T_PROTFLT,TF_TRAPNO(%rsp)
prot_addrf:
movq $0,TF_ADDR(%rsp)
movq %rdi,TF_RDI(%rsp) /* free up a GP register */
leaq doreti_iret(%rip),%rdi