Fix a problem seen when a new process was returning to userland
through fork_trampoline. This was caused because we were clearing the SR_INT_IE and setting SR_EXL bits of the status register at the same time. This meant that if an interrupt happened while this MTC0 was making its way through the pipeline the exception processing would see the status register with SR_EXL bit set. This in turn would mean that the COP_0_EXC_PC would not be updated so the return from exception would be to an incorrect address. It is easy to verify this fix by a program that forks in a loop and the child just exits: while (1) { pid_t pid = vfork(); if (pid == 0) _exit(0); if (pid != -1) waitpid(pid, NULL, 0); } Also remove two instances where we set SR_EXL bit gratuitously in exception.S. Approved by: imp (mentor)
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@ -106,7 +106,11 @@
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#elif defined(CPU_SB1)
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#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
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#else
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#define COP0_SYNC /* nothing */
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/*
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* Pick a reasonable default based on the "typical" spacing described in the
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* "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
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*/
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#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop
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#endif
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#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
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@ -519,9 +519,6 @@ NNON_LEAF(MipsUserGenException, STAND_FRAME_SIZE, ra)
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and t0, t0, ~(MIPS_SR_INT_IE)
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mtc0 t0, COP_0_STATUS_REG
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ITLBNOPFIX
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or t0, t0, SR_EXL
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mtc0 t0, COP_0_STATUS_REG # set exeption level
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ITLBNOPFIX
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/*
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* The use of k1 for storing the PCB pointer must be done only
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@ -751,9 +748,6 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra)
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and t0, t0, ~(MIPS_SR_INT_IE)
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mtc0 t0, COP_0_STATUS_REG
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ITLBNOPFIX
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or t0, t0, SR_EXL
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mtc0 t0, COP_0_STATUS_REG # set exeption level
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ITLBNOPFIX
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GET_CPU_PCPU(k1)
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lw k1, PC_CURPCB(k1)
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@ -171,13 +171,9 @@ LEAF(fork_trampoline)
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1:
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mfc0 v0, COP_0_STATUS_REG # set exeption level bit.
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or v0, SR_EXL
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and v0, ~(SR_INT_ENAB)
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mtc0 v0, COP_0_STATUS_REG # set exeption level bit.
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nop
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nop
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nop
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nop
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COP0_SYNC
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.set noat
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move k1, a1
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RESTORE_U_PCB_REG(t0, MULLO, k1)
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