Simplify code a little, prefer PCI?_FOO registers where possible.
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@ -325,7 +325,7 @@ decode_tuple_bar(device_t cbdev, device_t child, int id,
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}
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/* Convert from BAR type to BAR offset */
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bar = CARDBUS_BASE0_REG + (bar - 1) * 4;
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bar = PCIR_BAR(bar - 1);
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if (type == SYS_RES_MEMORY) {
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if (reg & TPL_BAR_REG_PREFETCHABLE)
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@ -491,8 +491,10 @@ cardbus_read_tuple_init(device_t cbdev, device_t child, uint32_t *start,
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uint32_t testval;
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uint32_t size;
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struct resource *res;
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uint32_t space;
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switch (CARDBUS_CIS_SPACE(*start)) {
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space = CARDBUS_CIS_SPACE(*start);
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switch (space) {
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case CARDBUS_CIS_ASI_TUPLE:
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/* CIS in PCI config space need no initialization */
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return ((struct resource*)~0UL);
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@ -502,21 +504,14 @@ cardbus_read_tuple_init(device_t cbdev, device_t child, uint32_t *start,
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case CARDBUS_CIS_ASI_BAR3:
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case CARDBUS_CIS_ASI_BAR4:
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case CARDBUS_CIS_ASI_BAR5:
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*rid = CARDBUS_BASE0_REG + (CARDBUS_CIS_SPACE(*start) - 1) * 4;
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*rid = PCIR_BAR(space - CARDBUS_CIS_ASI_BAR0);
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break;
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case CARDBUS_CIS_ASI_ROM:
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*rid = CARDBUS_ROM_REG;
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#if 0
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/*
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* This mask doesn't contain the bit that actually enables
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* the Option ROM.
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*/
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pci_write_config(child, *rid, CARDBUS_ROM_ADDRMASK, 4);
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#endif
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break;
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default:
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device_printf(cbdev, "Unable to read CIS: Unknown space: %d\n",
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CARDBUS_CIS_SPACE(*start));
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space);
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return (NULL);
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}
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@ -546,13 +541,12 @@ cardbus_read_tuple_init(device_t cbdev, device_t child, uint32_t *start,
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return (NULL);
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}
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pci_write_config(child, *rid,
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rman_get_start(res) | ((*rid == CARDBUS_ROM_REG)?
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CARDBUS_ROM_ENABLE : 0),
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4);
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rman_get_start(res) | ((*rid == CARDBUS_ROM_REG) ?
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CARDBUS_ROM_ENABLE : 0), 4);
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PCI_ENABLE_IO(cbdev, child, SYS_RES_MEMORY);
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/* Flip to the right ROM image if CIS is in ROM */
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if (CARDBUS_CIS_SPACE(*start) == CARDBUS_CIS_ASI_ROM) {
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if (space == CARDBUS_CIS_ASI_ROM) {
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bus_space_tag_t bt;
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bus_space_handle_t bh;
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uint32_t imagesize;
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