Import a rewrite of p4tcc for the cpufreq(4) framework. This includes
a bugfix of clearing the On-Demand flag when going back to 100%. It has been tested and works on an IBM R32. Note original work done by Ted Unangst and sobomax@.
This commit is contained in:
njl
parent
4a56299b7e
commit
4a038de7ac
@ -1,7 +1,5 @@
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/* $OpenBSD: p4tcc.c,v 1.1 2003/12/20 18:23:18 tedu Exp $ */
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/*-
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* Copyright (c) 2003 Ted Unangst
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* Copyright (c) 2004 Maxim Sobolev <sobomax@FreeBSD.org>
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* Copyright (c) 2005 Nate Lawson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -25,246 +23,256 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Restrict power consumption by using thermal control circuit.
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* This operates independently of speedstep.
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* Found on Pentium 4 and later models (feature TM).
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* Throttle clock frequency by using the thermal control circuit. This
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* operates independently of SpeedStep and ACPI throttling and is supported
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* on Pentium 4 and later models (feature TM).
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*
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* References:
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* Intel Developer's manual v.3 #245472-012
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* Reference: Intel Developer's manual v.3 #245472-012
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*
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* On some models, the cpu can hang if it's running at a slow speed.
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* Workarounds included below.
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* The original version of this driver was written by Ted Unangst for
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* OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson
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* for use with the cpufreq framework.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/power.h>
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#include <sys/sysctl.h>
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#include <sys/types.h>
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#include <sys/module.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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static u_int p4tcc_percentage;
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static u_int p4tcc_economy;
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static u_int p4tcc_performance;
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static struct sysctl_ctx_list p4tcc_sysctl_ctx;
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static struct sysctl_oid *p4tcc_sysctl_tree;
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#include "cpufreq_if.h"
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static struct {
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u_short level;
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u_short rlevel;
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u_short reg;
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} tcc[] = {
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{ 88, 100, 0 },
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{ 75, 88, 7 },
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{ 63, 75, 6 },
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{ 50, 63, 5 },
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{ 38, 50, 4 },
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{ 25, 38, 3 },
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{ 13, 25, 2 },
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{ 0, 13, 1 }
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struct p4tcc_softc {
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device_t dev;
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int set_count;
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int lowest_val;
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int auto_mode;
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};
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#define TCC_LEVELS sizeof(tcc) / sizeof(tcc[0])
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#define TCC_NUM_SETTINGS 8
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static u_short
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p4tcc_getperf(void)
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{
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u_int64_t msreg;
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int i;
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#define TCC_ENABLE_ONDEMAND (1<<4)
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#define TCC_REG_OFFSET 1
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#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS)
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msreg = rdmsr(MSR_THERM_CONTROL);
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msreg = (msreg >> 1) & 0x07;
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for (i = 0; i < TCC_LEVELS; i++) {
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if (msreg == tcc[i].reg)
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break;
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}
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static void p4tcc_identify(driver_t *driver, device_t parent);
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static int p4tcc_probe(device_t dev);
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static int p4tcc_attach(device_t dev);
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static int p4tcc_settings(device_t dev, struct cf_setting *sets,
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int *count);
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static int p4tcc_set(device_t dev, const struct cf_setting *set);
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static int p4tcc_get(device_t dev, struct cf_setting *set);
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static int p4tcc_type(device_t dev, int *type);
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return (tcc[i].rlevel);
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}
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static device_method_t p4tcc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, p4tcc_identify),
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DEVMETHOD(device_probe, p4tcc_probe),
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DEVMETHOD(device_attach, p4tcc_attach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, p4tcc_set),
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DEVMETHOD(cpufreq_drv_get, p4tcc_get),
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DEVMETHOD(cpufreq_drv_type, p4tcc_type),
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DEVMETHOD(cpufreq_drv_settings, p4tcc_settings),
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{0, 0}
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};
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static driver_t p4tcc_driver = {
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"p4tcc",
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p4tcc_methods,
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sizeof(struct p4tcc_softc),
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};
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static devclass_t p4tcc_devclass;
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DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0);
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static void
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p4tcc_setperf(u_int percentage)
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p4tcc_identify(driver_t *driver, device_t parent)
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{
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int i;
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u_int64_t msreg;
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if (percentage > tcc[0].rlevel)
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percentage = tcc[0].rlevel;
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for (i = 0; i < TCC_LEVELS - 1; i++) {
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if (percentage > tcc[i].level)
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break;
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}
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msreg = rdmsr(MSR_THERM_CONTROL);
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msreg &= ~0x1e; /* bit 0 reserved */
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if (tcc[i].reg != 0)
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msreg |= tcc[i].reg << 1 | 1 << 4;
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wrmsr(MSR_THERM_CONTROL, msreg);
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}
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static int
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p4tcc_perf_sysctl(SYSCTL_HANDLER_ARGS)
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{
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u_int percentage;
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int error;
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p4tcc_percentage = p4tcc_getperf();
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percentage = p4tcc_percentage;
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error = sysctl_handle_int(oidp, &percentage, 0, req);
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if (error || !req->newptr) {
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return (error);
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}
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if (p4tcc_percentage != percentage) {
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p4tcc_setperf(percentage);
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}
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return (error);
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}
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static void
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p4tcc_power_profile(void *arg)
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{
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u_int new;
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switch (power_profile_get_state()) {
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case POWER_PROFILE_PERFORMANCE:
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new = p4tcc_performance;
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break;
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case POWER_PROFILE_ECONOMY:
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new = p4tcc_economy;
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break;
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default:
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if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM))
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return;
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}
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if (p4tcc_getperf() != new) {
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p4tcc_setperf(new);
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}
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if (BUS_ADD_CHILD(parent, 0, "p4tcc", -1) == NULL)
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device_printf(parent, "add p4tcc child failed\n");
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}
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static int
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p4tcc_profile_sysctl(SYSCTL_HANDLER_ARGS)
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p4tcc_probe(device_t dev)
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{
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u_int32_t *argp;
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u_int32_t arg;
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int error;
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argp = (u_int32_t *)oidp->oid_arg1;
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arg = *argp;
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error = sysctl_handle_int(oidp, &arg, 0, req);
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/* error or no new value */
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if ((error != 0) || (req->newptr == NULL))
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return (error);
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/* range check */
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if (arg > tcc[0].rlevel)
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arg = tcc[0].rlevel;
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/* set new value and possibly switch */
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*argp = arg;
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p4tcc_power_profile(NULL);
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*argp = p4tcc_getperf();
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if (resource_disabled("p4tcc", 0))
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return (ENXIO);
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device_set_desc(dev, "CPU Frequency Thermal Control");
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return (0);
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}
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static void
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setup_p4tcc(void *dummy __unused)
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static int
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p4tcc_attach(device_t dev)
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{
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int nsteps, i;
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static char p4tcc_levels[(3 * TCC_LEVELS) + 1];
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char buf[4 + 1];
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struct p4tcc_softc *sc;
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if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) !=
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(CPUID_ACPI | CPUID_TM))
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return;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->set_count = TCC_NUM_SETTINGS;
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/*
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* On boot, the TCC is usually in Automatic mode where reading the
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* current performance level is likely to produce bogus results.
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* We record that state here and don't trust the contents of the
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* status MSR until we've set it ourselves.
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*/
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sc->auto_mode = TRUE;
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nsteps = TCC_LEVELS;
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switch (cpu_id & 0xf) {
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case 0x22: /* errata O50 P44 and Z21 */
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case 0x22:
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case 0x24:
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case 0x25:
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case 0x27:
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case 0x29:
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/* hang with 12.5 */
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tcc[TCC_LEVELS - 1] = tcc[TCC_LEVELS - 2];
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nsteps -= 1;
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/*
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* These CPU models hang when set to 12.5%.
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* See Errata O50, P44, and Z21.
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*/
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sc->set_count -= 1;
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break;
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case 0x07: /* errata N44 and P18 */
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case 0x0a:
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case 0x12:
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case 0x13:
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/* hang at 12.5 and 25 */
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tcc[TCC_LEVELS - 1] = tcc[TCC_LEVELS - 2] = tcc[TCC_LEVELS - 3];
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nsteps -= 2;
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break;
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default:
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/*
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* These CPU models hang when set to 12.5% or 25%.
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* See Errata N44 and P18l.
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*/
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sc->set_count -= 2;
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break;
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}
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sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1;
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p4tcc_levels[0] = '\0';
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for (i = nsteps; i > 0; i--) {
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sprintf(buf, "%d%s", tcc[i - 1].rlevel, (i != 1) ? " " : "");
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strcat(p4tcc_levels, buf);
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cpufreq_register(dev);
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return (0);
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}
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static int
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p4tcc_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct p4tcc_softc *sc;
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int i, val;
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sc = device_get_softc(dev);
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < sc->set_count)
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return (E2BIG);
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/* Return a list of valid settings for this driver. */
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memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count);
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val = TCC_NUM_SETTINGS;
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for (i = 0; i < sc->set_count; i++, val--) {
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sets[i].freq = TCC_SPEED_PERCENT(val);
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sets[i].dev = dev;
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}
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*count = sc->set_count;
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p4tcc_economy = tcc[TCC_LEVELS - 1].rlevel;
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p4tcc_performance = tcc[0].rlevel;
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return (0);
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}
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static int
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p4tcc_set(device_t dev, const struct cf_setting *set)
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{
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struct p4tcc_softc *sc;
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uint64_t mask, msr;
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int val;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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/*
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* Since after the reboot the TCC is usually in the Automatic
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* mode, in which reading current performance level is likely to
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* produce bogus results make sure to switch it to the On-Demand
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* mode and set to some known performance level. Unfortunately
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* there is no reliable way to check that TCC is in the Automatic
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* mode, reading bit 4 of ACPI Thermal Monitor Control Register
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* produces 0 regardless of the current mode.
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* Validate requested state converts to a setting that is an integer
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* from [sc->lowest_val .. TCC_NUM_SETTINGS].
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*/
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p4tcc_setperf(p4tcc_performance);
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val = set->freq * TCC_NUM_SETTINGS / 10000;
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if (val * 10000 != set->freq * TCC_NUM_SETTINGS ||
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val < sc->lowest_val || val > TCC_NUM_SETTINGS)
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return (EINVAL);
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p4tcc_percentage = p4tcc_getperf();
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printf("Pentium 4 TCC support enabled, %d steps from 100%% to %d%%, "
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"current performance %u%%\n", nsteps, p4tcc_economy,
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p4tcc_percentage);
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/*
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* Read the current register and mask off the old setting and
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* On-Demand bit. If the new val is < 100%, set it and the On-Demand
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* bit, otherwise just return to Automatic mode.
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*/
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msr = rdmsr(MSR_THERM_CONTROL);
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mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET;
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msr &= ~(mask | TCC_ENABLE_ONDEMAND);
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if (val < TCC_NUM_SETTINGS)
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msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND;
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wrmsr(MSR_THERM_CONTROL, msr);
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sysctl_ctx_init(&p4tcc_sysctl_ctx);
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p4tcc_sysctl_tree = SYSCTL_ADD_NODE(&p4tcc_sysctl_ctx,
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SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, "p4tcc", CTLFLAG_RD, 0,
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"Pentium 4 Thermal Control Circuitry support");
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SYSCTL_ADD_PROC(&p4tcc_sysctl_ctx,
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SYSCTL_CHILDREN(p4tcc_sysctl_tree), OID_AUTO,
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"cpuperf", CTLTYPE_INT | CTLFLAG_RW,
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&p4tcc_percentage, 0, p4tcc_perf_sysctl, "I",
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"CPU performance in % of maximum");
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SYSCTL_ADD_PROC(&p4tcc_sysctl_ctx,
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SYSCTL_CHILDREN(p4tcc_sysctl_tree), OID_AUTO,
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"cpuperf_performance", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
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&p4tcc_performance, 0, p4tcc_profile_sysctl, "I",
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"CPU performance in % of maximum in Performance mode");
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SYSCTL_ADD_PROC(&p4tcc_sysctl_ctx,
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SYSCTL_CHILDREN(p4tcc_sysctl_tree), OID_AUTO,
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"cpuperf_economy", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
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&p4tcc_economy, 0, p4tcc_profile_sysctl, "I",
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"CPU performance in % of maximum in Economy mode");
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SYSCTL_ADD_STRING(&p4tcc_sysctl_ctx,
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SYSCTL_CHILDREN(p4tcc_sysctl_tree), OID_AUTO,
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"cpuperf_levels", CTLFLAG_RD, p4tcc_levels, 0,
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"Perormance levels supported by the Pentium 4 Thermal Control "
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"Circuitry");
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/*
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* Record whether we're now in Automatic or On-Demand mode. We have
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* to cache this since there is no reliable way to check if TCC is in
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* Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of
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* the ACPI Thermal Monitor Control Register produces 0 no matter
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* what the current mode.
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*/
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if (msr & TCC_ENABLE_ONDEMAND)
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sc->auto_mode = TRUE;
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else
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sc->auto_mode = FALSE;
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/* register performance profile change handler */
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EVENTHANDLER_REGISTER(power_profile_change, p4tcc_power_profile, NULL, 0);
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return (0);
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}
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static int
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p4tcc_get(device_t dev, struct cf_setting *set)
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{
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struct p4tcc_softc *sc;
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uint64_t msr;
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int val;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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/*
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* Read the current register and extract the current setting. If
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* in automatic mode, assume we're at TCC_NUM_SETTINGS (100%).
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*
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* XXX This is not completely reliable since at high temperatures
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* the CPU may be automatically throttling to 50% but it's the best
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* we can do.
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*/
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if (!sc->auto_mode) {
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msr = rdmsr(MSR_THERM_CONTROL);
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val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1);
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} else
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val = TCC_NUM_SETTINGS;
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memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
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set->freq = TCC_SPEED_PERCENT(val);
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set->dev = dev;
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return (0);
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}
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static int
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p4tcc_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_RELATIVE;
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return (0);
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}
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SYSINIT(setup_p4tcc, SI_SUB_CPU, SI_ORDER_ANY, setup_p4tcc, NULL);
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