Remove old lnc files.
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paul
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/*
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* Am7990, Local Area Network Controller for Ethernet (LANCE)
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*
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* Copyright (c) 1994, Paul Richards. This software may be used,
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* modified, copied, distributed, and sold, in both source and binary
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* form provided that the above copyright and these terms are retained.
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* Under no circumstances is the author responsible for the proper
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* functioning of this software, nor does the author assume any
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* responsibility for damages incurred with its use.
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*
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* $FreeBSD$
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*/
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/*
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* The LANCE has four Control and Status Registers(CSRs) which are accessed
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* through two bus addressable ports, the address port (RAP) and the data
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* port (RDP).
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*
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*/
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#define CSR0 0
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#define CSR1 1
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#define CSR2 2
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#define CSR3 3
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#define CSR88 88
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#define CSR89 89
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#define BCR49 49
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#define BCR32 32
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#define BCR33 33
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#define BCR34 34
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/* Control and Status Register Masks */
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/* CSR0 */
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#define ERR 0x8000
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#define BABL 0x4000
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#define CERR 0x2000
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#define MISS 0x1000
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#define MERR 0x0800
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#define RINT 0x0400
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#define TINT 0x0200
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#define IDON 0x0100
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#define INTR 0x0080
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#define INEA 0x0040
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#define RXON 0x0020
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#define TXON 0x0010
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#define TDMD 0x0008
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#define STOP 0x0004
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#define STRT 0x0002
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#define INIT 0x0001
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/*
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* CSR3
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*
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* Bits 3-15 are reserved.
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*
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*/
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#define BSWP 0x0004
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#define ACON 0x0002
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#define BCON 0x0001
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/* Initialisation block */
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struct init_block {
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u_short mode; /* Mode register */
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u_char padr[6]; /* Ethernet address */
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u_char ladrf[8]; /* Logical address filter (multicast) */
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u_short rdra; /* Low order pointer to receive ring */
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u_short rlen; /* High order pointer and no. rings */
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u_short tdra; /* Low order pointer to transmit ring */
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u_short tlen; /* High order pointer and no rings */
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};
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/* Initialisation Block Mode Register Masks */
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#define PROM 0x8000 /* Promiscuous Mode */
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#define DRCVBC 0x4000 /* Disable Receive Broadcast */
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#define DRCVPA 0x2000 /* Disable Receive Physical Address */
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#define DLNKTST 0x1000 /* Disable Link Status */
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#define DAPC 0x0800 /* Disable Automatic Polarity Correction */
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#define MENDECL 0x0400 /* MENDEC Loopback Mode */
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#define LRT 0x0200 /* Low Receive Threshold (T-MAU mode only) */
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#define TSEL 0x0200 /* Transmit Mode Select (AUI mode only) */
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#define PORTSEL 0x0180 /* Port Select bits */
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#define INTL 0x0040 /* Internal Loopback */
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#define DRTY 0x0020 /* Disable Retry */
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#define FCOLL 0x0010 /* Force Collision */
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#define DXMTFCS 0x0008 /* Disable transmit CRC (FCS) */
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#define LOOP 0x0004 /* Loopback Enabl */
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#define DTX 0x0002 /* Disable the transmitter */
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#define DRX 0x0001 /* Disable the receiver */
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/*
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* Message Descriptor Structure
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*
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* Each transmit or receive descriptor ring entry (RDRE's and TDRE's)
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* is composed of 4, 16-bit, message descriptors. They contain the following
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* information.
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*
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* 1. The address of the actual message data buffer in user (host) memory.
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* 2. The length of that message buffer.
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* 3. The status information for that particular buffer. The eight most
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* significant bits of md1 are collectively termed the STATUS of the
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* descriptor.
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*
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* Descriptor md0 contains LADR 0-15, the low order 16 bits of the 24-bit
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* address of the actual data buffer. Bits 0-7 of descriptor md1 contain
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* HADR, the high order 8-bits of the 24-bit data buffer address. Bits 8-15
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* of md1 contain the status flags of the buffer. Descriptor md2 contains the
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* buffer byte count in bits 0-11 as a two's complement number and must have
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* 1's written to bits 12-15. For the receive entry md3 has the Message Byte
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* Count in bits 0-11, this is the length of the received message and is valid
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* only when ERR is cleared and ENP is set. For the transmit entry it contains
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* more status information.
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*
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*/
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struct mds {
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u_short md0;
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u_short md1;
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short md2;
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u_short md3;
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};
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/* Receive STATUS flags for md1 */
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#define OWN 0x8000 /* Owner bit, 0=host, 1=Lance */
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#define MDERR 0x4000 /* Error */
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#define FRAM 0x2000 /* Framing error error */
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#define OFLO 0x1000 /* Silo overflow */
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#define CRC 0x0800 /* CRC error */
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#define RBUFF 0x0400 /* Buffer error */
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#define STP 0x0200 /* Start of packet */
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#define ENP 0x0100 /* End of packet */
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#define HADR 0x00FF /* High order address bits */
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/* Receive STATUS flags for md2 */
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#define BCNT 0x0FFF /* Size of data buffer as 2's comp. no. */
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/* Receive STATUS flags for md3 */
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#define MCNT 0x0FFF /* Total size of data for received packet */
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/* Transmit STATUS flags for md1 */
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#define ADD_FCS 0x2000 /* Controls generation of FCS */
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#define MORE 0x1000 /* Indicates more than one retry was needed */
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#define ONE 0x0800 /* Exactly one retry was needed */
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#define DEF 0x0400 /* Packet transmit deferred -- channel busy */
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/*
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* Transmit status flags for md2
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*
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* Same as for receive descriptor.
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*
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* BCNT 0x0FFF Size of data buffer as 2's complement number.
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*
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*/
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/* Transmit status flags for md3 */
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#define TBUFF 0x8000 /* Buffer error */
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#define UFLO 0x4000 /* Silo underflow */
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#define LCOL 0x1000 /* Late collision */
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#define LCAR 0x0800 /* Loss of carrier */
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#define RTRY 0x0400 /* Tried 16 times */
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#define TDR 0x03FF /* Time domain reflectometry */
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File diff suppressed because it is too large
Load Diff
@ -1,215 +0,0 @@
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/*-
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* Copyright (c) 1994-1998
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* Paul Richards. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* verbatim and that no modifications are made prior to this
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* point in the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Paul Richards.
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* 4. The name Paul Richards may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY PAUL RICHARDS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL PAUL RICHARDS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <i386/isa/ic/Am7990.h>
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/*
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* Initialize multicast address hashing registers to accept
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* all multicasts (only used when in promiscuous mode)
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*/
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#define MULTI_INIT_ADDR 0xff
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#define NORMAL 0
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#define NRDRE 3
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#define NTDRE 3
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#define RECVBUFSIZE 1518 /* Packet size rounded to dword boundary */
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#define TRANSBUFSIZE 1518
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#define MBUF_CACHE_LIMIT 0
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#define MEM_SLEW 8
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/* LNC Flags */
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#define LNC_INITIALISED 1
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#define LNC_ALLMULTI 2
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/* BICC port addresses */
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#define BICC_IOSIZE 16
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#define BICC_RDP 0x0c /* Register Data Port */
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#define BICC_RAP 0x0e /* Register Address Port */
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/* NE2100 port addresses */
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#define NE2100_IOSIZE 24
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#define PCNET_RDP 0x10 /* Register Data Port */
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#define PCNET_RAP 0x12 /* Register Address Port */
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#define PCNET_RESET 0x14
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#define PCNET_BDP 0x16
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#define PCNET_VSW 0x18
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/* DEPCA port addresses */
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#define DEPCA_IOSIZE 16
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#define DEPCA_CTRL 0x00 /* NIC Control and status register */
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#define DEPCA_RDP 0x04 /* Register Data Port */
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#define DEPCA_RAP 0x06 /* Register Address Port */
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#define DEPCA_ADP 0x0c
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/* DEPCA specific defines */
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#define DEPCA_ADDR_ROM_SIZE 32
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#ifdef PC98
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/* C-NET(98)S port addresses */
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#define CNET98S_RDP 0x400 /* Register Data Port */
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#define CNET98S_RAP 0x402 /* Register Address Port */
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#define CNET98S_RESET 0x404
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#define CNET98S_IDP 0x406
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#define CNET98S_EEPROM 0x40e
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/*
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* XXX - The I/O address range is fragmented in the C-NET(98)S.
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* This is the number of regs at iobase.
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*/
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#define CNET98S_IOSIZE 16 /* # of i/o addresses used. */
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#endif
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/* Chip types */
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#define LANCE 1 /* Am7990 */
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#define C_LANCE 2 /* Am79C90 */
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#define PCnet_ISA 3 /* Am79C960 */
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#define PCnet_ISAplus 4 /* Am79C961 */
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#define PCnet_ISA_II 5 /* Am79C961A */
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#define PCnet_32 6 /* Am79C965 */
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#define PCnet_PCI 7 /* Am79C970 */
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#define PCnet_PCI_II 8 /* Am79C970A */
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#define PCnet_FAST 9 /* Am79C971 */
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#define PCnet_FASTplus 10 /* Am79C972 */
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#define PCnet_Home 11 /* Am79C978 */
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/* CSR88-89: Chip ID masks */
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#define AMD_MASK 0x003
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#define PART_MASK 0xffff
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#define Am79C960 0x0003
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#define Am79C961 0x2260
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#define Am79C961A 0x2261
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#define Am79C965 0x2430
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#define Am79C970 0x0242
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#define Am79C970A 0x2621
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#define Am79C971 0x2623
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#define Am79C972 0x2624
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#define Am79C978 0x2626
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/* Board types */
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#define UNKNOWN 0
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#define BICC 1
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#define NE2100 2
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#define DEPCA 3
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#define CNET98S 4 /* PC-98 */
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/* mem_mode values */
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#define DMA_FIXED 1
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#define DMA_MBUF 2
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#define SHMEM 4
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#define MEM_MODES \
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"\20\3SHMEM\2DMA_MBUF\1DMA_FIXED"
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#define CSR0_FLAGS \
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"\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\12TINT\11IDON\
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\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT"
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#define INIT_MODE \
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"\20\20PROM\07INTL\06DRTY\05COLL\04DTCR\03LOOP\02DTX\01DRX"
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#define RECV_MD1 \
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"\20\10OWN\7ERR\6FRAM\5OFLO\4CRC\3BUFF\2STP\1ENP"
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#define TRANS_MD1 \
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"\20\10OWN\7ERR\6RES\5MORE\4ONE\3DEF\2STP\1ENP"
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#define TRANS_MD3 \
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"\20\6BUFF\5UFLO\4RES\3LCOL\2LCAR\1RTRY"
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struct nic_info {
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int ident; /* Type of card */
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int ic; /* Type of ic, Am7990, Am79C960 etc. */
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int mem_mode;
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int iobase;
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int mode; /* Mode setting at initialization */
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};
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struct host_ring_entry {
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struct mds *md;
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union {
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struct mbuf *mbuf;
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char *data;
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}buff;
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};
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#ifdef LNC_KEEP_STATS
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#define LNCSTATS_STRUCT \
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struct lnc_stats { \
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int idon; \
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int rint; \
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int tint; \
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int cerr; \
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int babl; \
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int miss; \
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int merr; \
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int rxoff; \
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int txoff; \
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int terr; \
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int lcol; \
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int lcar; \
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int tbuff; \
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int def; \
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int more; \
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int one; \
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int uflo; \
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int rtry; \
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int rerr; \
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int fram; \
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int oflo; \
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int crc; \
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int rbuff; \
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int drop_packet; \
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int trans_ring_full; \
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} lnc_stats;
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#define LNCSTATS(X) ++(sc->lnc_stats.X);
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#else
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#define LNCSTATS_STRUCT
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#define LNCSTATS(X)
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#endif
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#define NDESC(len2) (1 << len2)
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#define INC_MD_PTR(ptr, no_entries) \
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if (++ptr >= NDESC(no_entries)) \
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ptr = 0;
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#define DEC_MD_PTR(ptr, no_entries) \
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if (--ptr < 0) \
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ptr = NDESC(no_entries) - 1;
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#define RECV_NEXT (sc->recv_ring->base + sc->recv_next)
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#define TRANS_NEXT (sc->trans_ring->base + sc->trans_next)
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