allwinner: a83t: Fix PLL_CPU clocks
The PLL_CPU clocks formula is 24Mhz * N and not 24Mhz / N Fix it by using a NKMP clock with fixed factor values for the one unused.
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@ -206,24 +206,29 @@ FIXED_CLK(osc12m_clk,
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2, /* div */
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0); /* flags */
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/* CPU PLL are 24Mhz * N / P */
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static const char *pll_c0cpux_parents[] = {"osc24M"};
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static const char *pll_c1cpux_parents[] = {"osc24M"};
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NM_CLK(pll_c0cpux_clk,
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NKMP_CLK(pll_c0cpux_clk,
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CLK_PLL_C0CPUX, /* id */
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"pll_c0cpux", pll_c0cpux_parents, /* name, parents */
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0x00, /* offset */
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8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
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0, 0, /* mux */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
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0, 0, /* lock */
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31, /* gate */
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AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */
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NM_CLK(pll_c1cpux_clk,
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NKMP_CLK(pll_c1cpux_clk,
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CLK_PLL_C1CPUX, /* id */
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"pll_c1cpux", pll_c1cpux_parents, /* name, parents */
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0x04, /* offset */
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8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
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0, 0, /* mux */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */
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0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
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0, 0, /* lock */
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31, /* gate */
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AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */
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@ -689,8 +694,8 @@ static struct aw_ccung_clk a83t_clks[] = {
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{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_hsic_clk},
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{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_de_clk},
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{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_video1_clk},
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{ .type = AW_CLK_NM, .clk.nm = &pll_c0cpux_clk},
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{ .type = AW_CLK_NM, .clk.nm = &pll_c1cpux_clk},
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{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_c0cpux_clk},
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{ .type = AW_CLK_NKMP, .clk.nkmp = &pll_c1cpux_clk},
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{ .type = AW_CLK_NM, .clk.nm = &apb2_clk},
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{ .type = AW_CLK_NM, .clk.nm = &nand_clk},
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{ .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
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