Add initial support for the Marvell 88SX[56]0[48][01] series of SATA chips.
Hardware donated by: Matthew Jacob Hardware donated by: Y!
This commit is contained in:
Søren Schmidt
parent
8ec96d7b8d
commit
4b55f0c7c7
@ -98,6 +98,12 @@ static void ata_intel_old_setmode(device_t dev, int mode);
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static void ata_intel_new_setmode(device_t dev, int mode);
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static int ata_ite_chipinit(device_t dev);
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static void ata_ite_setmode(device_t dev, int mode);
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static int ata_marvell_chipinit(device_t dev);
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static int ata_marvell_allocate(device_t dev);
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static void ata_marvell_intr(void *data);
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static void ata_marvell_dmainit(device_t dev);
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static int ata_marvell_command(struct ata_request *request);
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static void ata_marvell_reset(device_t dev);
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static int ata_national_chipinit(device_t dev);
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static void ata_national_setmode(device_t dev, int mode);
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static int ata_nvidia_chipinit(device_t dev);
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@ -2080,6 +2086,440 @@ ata_ite_setmode(device_t dev, int mode)
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}
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/*
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* Marvell chipset support functions
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*/
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#define ATA_MV_HOST_BASE(ch) \
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((ch->unit & 3) * 0x0100) + (ch->unit > 3 ? 0x30000 : 0x20000)
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#define ATA_MV_EDMA_BASE(ch) \
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((ch->unit & 3) * 0x2000) + (ch->unit > 3 ? 0x30000 : 0x20000)
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int
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ata_marvell_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_M88SX5040, 0, 4, MV5XXX, ATA_SA150, "88SX5040" },
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{ ATA_M88SX5041, 0, 4, MV5XXX, ATA_SA150, "88SX5041" },
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{ ATA_M88SX5080, 0, 8, MV5XXX, ATA_SA150, "88SX5080" },
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{ ATA_M88SX5081, 0, 8, MV5XXX, ATA_SA150, "88SX5081" },
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{ ATA_M88SX6041, 0, 4, MV6XXX, ATA_SA300, "88SX6041" },
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{ ATA_M88SX6081, 0, 8, MV6XXX, ATA_SA300, "88SX6081" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (pci_get_class(dev) != PCIC_STORAGE ||
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pci_get_vendor(dev) != ATA_MARVELL_ID)
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return ENXIO;
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if (!(idx = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "Marvell %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ctlr->chipinit = ata_marvell_chipinit;
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return 0;
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}
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static int
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ata_marvell_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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int rid = ATA_IRQ_RID;
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if (!(ctlr->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE))) {
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device_printf(dev, "unable to map interrupt\n");
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return ENXIO;
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}
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ctlr->r_type1 = SYS_RES_MEMORY;
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ctlr->r_rid1 = PCIR_BAR(0);
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if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
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&ctlr->r_rid1, RF_ACTIVE)))
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return ENXIO;
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/* mask all host controller interrupts */
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ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
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/* mask all PCI interrupts */
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ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
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ctlr->reset = ata_marvell_reset;
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ctlr->dmainit = ata_marvell_dmainit;
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ctlr->allocate = ata_marvell_allocate;
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ctlr->setmode = ata_sata_setmode;
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ctlr->channels = ctlr->chip->cfg1;
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if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS,
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ata_marvell_intr, ctlr, &ctlr->handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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return ENXIO;
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}
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/* clear host controller interrupts */
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ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
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if (ctlr->chip->cfg1 > 4)
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ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
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/* clear PCI interrupts */
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ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
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/* unmask PCI interrupts we want */
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ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
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/* unmask host controller interrupts we want */
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ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
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/*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
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pci_write_config(dev, PCIR_COMMAND,
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pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
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return 0;
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}
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static int
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ata_marvell_allocate(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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bus_addr_t wordp = ch->dma->work_bus;
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int i;
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/* set legacy ATA resources */
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for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
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ch->r_io[i].res = ctlr->r_res1;
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ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
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}
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ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
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ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
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ata_default_registers(dev);
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/* set SATA resources */
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switch (ctlr->chip->cfg2) {
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case MV5XXX:
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
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ch->r_io[ATA_SSTATUS].offset = 0x00100 + ATA_MV_HOST_BASE(ch);
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ch->r_io[ATA_SERROR].res = ctlr->r_res1;
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ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
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ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
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break;
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case MV6XXX:
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
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ch->r_io[ATA_SSTATUS].offset = 0x02300 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_SERROR].res = ctlr->r_res1;
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ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
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ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
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ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
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ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
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break;
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}
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ch->flags |= ATA_NO_SLAVE;
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ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
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ata_generic_hw(dev);
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ch->hw.command = ata_marvell_command;
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/* disable the EDMA machinery */
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ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
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DELAY(100000); /* SOS should poll for disabled */
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/* set configuration to non-queued 128b read transfers stop on error */
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ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
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/* request queue base high */
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ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), (wordp >> 16) >> 16);
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/* request queue in ptr */
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ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), wordp & 0xffffffff);
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/* request queue out ptr */
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ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* response queue base high */
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wordp += 1024;
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ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), (wordp >> 16) >> 16);
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/* response queue in ptr */
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ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* response queue out ptr */
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ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), wordp & 0xffffffff);
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/* clear SATA error register */
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ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
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/* clear any outstanding error interrupts */
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ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
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/* unmask all error interrupts */
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ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
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/* enable EDMA machinery */
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ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
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return 0;
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}
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static void
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ata_marvell_intr(void *data)
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_request *request;
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u_int32_t cause, icr0 = 0, icr1 = 0;
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int unit;
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cause = ATA_INL(ctlr->r_res1, 0x01d60);
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if ((icr0 = ATA_INL(ctlr->r_res1, 0x20014)))
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ATA_OUTL(ctlr->r_res1, 0x20014, ~icr0);
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if (ctlr->channels > 4) {
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if ((icr1 = ATA_INL(ctlr->r_res1, 0x30014)))
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ATA_OUTL(ctlr->r_res1, 0x30014, ~icr1);
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}
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for (unit = 0; unit < ctlr->channels; unit++) {
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u_int32_t icr;
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int shift;
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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mtx_lock(&ch->state_mtx);
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shift = unit << 1;
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if (ch->unit < 4)
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icr = icr0;
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else {
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icr = icr1;
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shift++;
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}
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/* do we have any errors flagged ? */
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if (cause & (1 << shift)) {
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/* clear SATA error register */
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ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
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/* clear any outstanding error interrupts */
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ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
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}
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/* EDMA interrupt */
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if ((icr & (0x0001 << (unit & 3))) && (request = ch->running)) {
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u_int32_t rsp_in, rsp_out;
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int slot;
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request->dmastat = ch->dma->stop(request->dev);
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ch->dma->unload(ch->dev);
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callout_stop(&request->callout);
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/* get response ptr's */
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rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
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rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
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slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
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rsp_out &= 0xffffff00;
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rsp_out += (slot << 3);
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/* XXX SOS get status and error into request */
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request->status = 0; /* XXX SOS */
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request->error = 0; /* XXX SOS */
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if (!(request->flags & ATA_R_TIMEOUT))
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request->donecount = request->bytecount;
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/* ack response */
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ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
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ch->running = NULL;
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if (ch->state == ATA_ACTIVE)
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ch->state = ATA_IDLE;
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mtx_unlock(&ch->state_mtx);
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ATA_LOCKING(ch->dev, ATA_LF_UNLOCK);
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ata_finish(request);
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}
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/* legacy ATA interrupt */
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else if (icr & (0x0100 << (unit & 3))) {
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mtx_unlock(&ch->state_mtx);
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ctlr->interrupt[unit].function(ch);
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}
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/* no device action to handle */
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else {
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mtx_unlock(&ch->state_mtx);
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}
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}
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}
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struct ata_marvell_dma_prdentry {
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u_int32_t addrlo;
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u_int32_t count;
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u_int32_t addrhi;
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u_int32_t reserved;
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};
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static void
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ata_marvell_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
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{
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struct ata_dmasetprd_args *args = xsc;
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struct ata_marvell_dma_prdentry *prd = args->dmatab;
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int i;
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if ((args->error = error))
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return;
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for (i = 0; i < nsegs; i++) {
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prd[i].addrlo = htole32(segs[i].ds_addr);
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prd[i].addrhi = 0;
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prd[i].count = htole32(segs[i].ds_len);
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}
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prd[i - 1].count |= htole32(ATA_DMA_EOT);
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}
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static int
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ata_marvell_dmastart(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(device_get_parent(dev));
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ch->flags |= ATA_DMA_ACTIVE;
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return 0;
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}
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static int
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ata_marvell_dmastop(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(device_get_parent(dev));
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ch->flags &= ~ATA_DMA_ACTIVE;
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/* get status XXX SOS */
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return 0;
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}
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static void
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ata_marvell_dmainit(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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ata_dmainit(dev);
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if (ch->dma) {
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ch->dma->start = ata_marvell_dmastart;
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ch->dma->stop = ata_marvell_dmastop;
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ch->dma->setprd = ata_marvell_dmasetprd;
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}
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}
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static int
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ata_marvell_command(struct ata_request *request)
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{
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struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
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struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
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u_int32_t req_in, req_out;
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u_int8_t *bytep;
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u_int16_t *wordp;
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u_int32_t *quadp;
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int i, tag = 0x07;
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int slot;
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/* only DMA R/W goes through the EMDA machine */
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/* XXX SOS add ATAPI commands support later */
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if (request->u.ata.command != ATA_READ_DMA &&
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request->u.ata.command != ATA_WRITE_DMA) {
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/* disable the EDMA machinery */
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if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
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ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
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return ata_generic_command(request);
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}
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req_out = ATA_INL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch));
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/* get next free request queue slot */
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req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
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slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
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bytep = (u_int8_t *)(ch->dma->work);
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bytep += (slot << 5);
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wordp = (u_int16_t *)bytep;
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quadp = (u_int32_t *)bytep;
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quadp[0] = (long)ch->dma->sg_bus & 0xffffffff;
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quadp[1] = (ch->dma->sg_bus & 0xffffffff00000000) >> 32;
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wordp[4] = (request->flags & ATA_R_READ ? 0x01 : 0x00) | (tag<<1);
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i = 10;
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bytep[i++] = (request->u.ata.count >> 8) & 0xff;
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bytep[i++] = 0x10 | ATA_COUNT;
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bytep[i++] = request->u.ata.count & 0xff;
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bytep[i++] = 0x10 | ATA_COUNT;
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bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
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bytep[i++] = 0x10 | ATA_SECTOR;
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bytep[i++] = request->u.ata.lba & 0xff;
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bytep[i++] = 0x10 | ATA_SECTOR;
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bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
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bytep[i++] = 0x10 | ATA_CYL_LSB;
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bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
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bytep[i++] = 0x10 | ATA_CYL_LSB;
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bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
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bytep[i++] = 0x10 | ATA_CYL_MSB;
|
||||
bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
|
||||
bytep[i++] = 0x10 | ATA_CYL_MSB;
|
||||
|
||||
bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
|
||||
bytep[i++] = 0x10 | ATA_DRIVE;
|
||||
bytep[i++] = request->u.ata.command;
|
||||
bytep[i++] = 0x90 | ATA_COMMAND;
|
||||
|
||||
/* enable EDMA machinery if needed */
|
||||
if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
|
||||
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
|
||||
while (!(ATA_INL(ctlr->r_res1,
|
||||
0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
|
||||
DELAY(10);
|
||||
}
|
||||
|
||||
slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
|
||||
req_in &= 0xfffffc00;
|
||||
req_in += (slot << 5);
|
||||
|
||||
/* tell EDMA it has a new request */
|
||||
ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
ata_marvell_reset(device_t dev)
|
||||
{
|
||||
struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
|
||||
struct ata_channel *ch = device_get_softc(dev);
|
||||
|
||||
/* disable the EDMA machinery */
|
||||
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
|
||||
DELAY(100000); /* SOS should poll for disabled */
|
||||
|
||||
/* clear SATA error register */
|
||||
ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
|
||||
|
||||
/* clear any outstanding error interrupts */
|
||||
ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
|
||||
|
||||
/* unmask all error interrupts */
|
||||
ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
|
||||
|
||||
/* enable channel and test for devices */
|
||||
ata_sata_phy_enable(ch);
|
||||
|
||||
/* enable EDMA machinery */
|
||||
ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* National chipset support functions
|
||||
*/
|
||||
|
||||
@ -114,6 +114,10 @@ ata_pci_probe(device_t dev)
|
||||
if (!ata_ite_ident(dev))
|
||||
return 0;
|
||||
break;
|
||||
case ATA_MARVELL_ID:
|
||||
if (!ata_marvell_ident(dev))
|
||||
return 0;
|
||||
break;
|
||||
case ATA_NATIONAL_ID:
|
||||
if (!ata_national_ident(dev))
|
||||
return 0;
|
||||
|
||||
@ -161,6 +161,14 @@ struct ata_connect_task {
|
||||
#define ATA_IT8211F 0x82111283
|
||||
#define ATA_IT8212F 0x82121283
|
||||
|
||||
#define ATA_MARVELL_ID 0x11ab
|
||||
#define ATA_M88SX5040 0x504011ab
|
||||
#define ATA_M88SX5041 0x504111ab
|
||||
#define ATA_M88SX5080 0x508011ab
|
||||
#define ATA_M88SX5081 0x508111ab
|
||||
#define ATA_M88SX6041 0x604111ab
|
||||
#define ATA_M88SX6081 0x608111ab
|
||||
|
||||
#define ATA_MICRON_ID 0x1042
|
||||
#define ATA_MICRON_RZ1000 0x10001042
|
||||
#define ATA_MICRON_RZ1001 0x10011042
|
||||
@ -326,6 +334,9 @@ struct ata_connect_task {
|
||||
#define HPT374 3
|
||||
#define HPTOLD 0x01
|
||||
|
||||
#define MV5XXX 5
|
||||
#define MV6XXX 6
|
||||
|
||||
#define PROLD 0
|
||||
#define PRNEW 1
|
||||
#define PRTX 2
|
||||
@ -395,6 +406,7 @@ int ata_cypress_ident(device_t);
|
||||
int ata_highpoint_ident(device_t);
|
||||
int ata_intel_ident(device_t);
|
||||
int ata_ite_ident(device_t);
|
||||
int ata_marvell_ident(device_t);
|
||||
int ata_national_ident(device_t);
|
||||
int ata_nvidia_ident(device_t);
|
||||
int ata_promise_ident(device_t);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user