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Convert the Zynq SoC support to the new routines for static device mapping.

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This commit is contained in:
Ian Lepore 2014-04-30 14:38:13 +00:00
parent e51fc8f90d
commit 4c05359867
2 changed files with 6 additions and 33 deletions
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33
sys/arm/xilinx/zy7_machdep.c
View File

@ -60,7 +60,7 @@ vm_offset_t
initarm_lastaddr(void)
{
return (ZYNQ7_PSIO_VBASE);
return (arm_devmap_lastaddr());
}
void
@ -79,39 +79,18 @@ initarm_late_init(void)
{
}
#define FDT_DEVMAP_SIZE 3
static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_SIZE];
/*
* Construct pmap_devmap[] with DT-derived config data.
* Set up static device mappings. Not strictly necessary -- simplebus will
* dynamically establish mappings as needed -- but doing it this way gets us
* nice efficient 1MB section mappings.
*/
int
initarm_devmap_init(void)
{
int i = 0;
fdt_devmap[i].pd_va = ZYNQ7_PSIO_VBASE;
fdt_devmap[i].pd_pa = ZYNQ7_PSIO_HWBASE;
fdt_devmap[i].pd_size = ZYNQ7_PSIO_SIZE;
fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
fdt_devmap[i].pd_cache = PTE_DEVICE;
i++;
arm_devmap_add_entry(ZYNQ7_PSIO_HWBASE, ZYNQ7_PSIO_SIZE);
arm_devmap_add_entry(ZYNQ7_PSCTL_HWBASE, ZYNQ7_PSCTL_SIZE);
fdt_devmap[i].pd_va = ZYNQ7_PSCTL_VBASE;
fdt_devmap[i].pd_pa = ZYNQ7_PSCTL_HWBASE;
fdt_devmap[i].pd_size = ZYNQ7_PSCTL_SIZE;
fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
fdt_devmap[i].pd_cache = PTE_DEVICE;
i++;
/* end of table */
fdt_devmap[i].pd_va = 0;
fdt_devmap[i].pd_pa = 0;
fdt_devmap[i].pd_size = 0;
fdt_devmap[i].pd_prot = 0;
fdt_devmap[i].pd_cache = 0;
arm_devmap_register_table(&fdt_devmap[0]);
return (0);
}

6
sys/arm/xilinx/zy7_reg.h
View File

@ -44,16 +44,13 @@
#define ZYNQ7_PLGP1_SIZE 0x40000000
/* I/O Peripheral registers. */
#define ZYNQ7_PSIO_VBASE 0xE0000000
#define ZYNQ7_PSIO_HWBASE 0xE0000000
#define ZYNQ7_PSIO_SIZE 0x00300000
/* UART0 and UART1 */
#define ZYNQ7_UART0_VBASE (ZYNQ7_PSIO_VBASE)
#define ZYNQ7_UART0_HWBASE (ZYNQ7_PSIO_HWBASE)
#define ZYNQ7_UART0_SIZE 0x1000
#define ZYNQ7_UART1_VBASE (ZYNQ7_PSIO_VBASE+0x1000)
#define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000)
#define ZYNQ7_UART1_SIZE 0x1000
@ -63,15 +60,12 @@
#define ZYNQ7_SMC_SIZE 0x05000000
/* SLCR, PS system, and CPU private registers combined in this region. */
#define ZYNQ7_PSCTL_VBASE 0xF8000000
#define ZYNQ7_PSCTL_HWBASE 0xF8000000
#define ZYNQ7_PSCTL_SIZE 0x01000000
#define ZYNQ7_SLCR_VBASE (ZYNQ7_PSCTL_VBASE)
#define ZYNQ7_SLCR_HWBASE (ZYNQ7_PSCTL_HWBASE)
#define ZYNQ7_SLCR_SIZE 0x1000
#define ZYNQ7_DEVCFG_VBASE (ZYNQ7_PSCTL_VBASE+0x7000)
#define ZYNQ7_DEVCFG_HWBASE (ZYNQ7_PSCTL_HWBASE+0x7000)
#define ZYNQ7_DEVCFG_SIZE 0x1000