a10_timer: Update the driver so we can use it on other SoC
a10_timer is currently use in UP allwinner SoC (A10 and A13). Those don't have the generic arm timer. The arm generic timecounter is broken in the A64 SoC, some attempts have been made to fix the glitch but users still reported some minor ones. Since the A64 (and all Allwinner SoC) still have this timer controller, rework the driver so we can use it in any SoC. Since it doesn't have the 64 bits counter on all SoC, use one of the generic 32 bits counter as the timecounter source. PR: 229644
This commit is contained in:
Emmanuel Vadot
parent
55f3f71ca0
commit
4ca213c07a
@ -38,7 +38,6 @@ __FBSDID("$FreeBSD$");
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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@ -46,65 +45,86 @@ __FBSDID("$FreeBSD$");
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <sys/kdb.h>
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#include <dev/extres/clk/clk.h>
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#if defined(__aarch64__)
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#include "opt_soc.h"
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#else
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#include <arm/allwinner/aw_machdep.h>
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#endif
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/**
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* Timer registers addr
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*
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*/
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#define SW_TIMER_IRQ_EN_REG 0x00
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#define SW_TIMER_IRQ_STA_REG 0x04
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#define SW_TIMER0_CTRL_REG 0x10
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#define SW_TIMER0_INT_VALUE_REG 0x14
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#define SW_TIMER0_CUR_VALUE_REG 0x18
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_ENABLE(x) (1 << x)
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#define SW_COUNTER64LO_REG 0xa4
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#define SW_COUNTER64HI_REG 0xa8
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#define CNT64_CTRL_REG 0xa0
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#define TIMER_IRQ_STA_REG 0x04
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#define TIMER_IRQ_PENDING(x) (1 << x)
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#define CNT64_RL_EN 0x02 /* read latch enable */
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/*
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* On A10, A13, A20 and A31/A31s 6 timers are available
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*/
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#define TIMER_CTRL_REG(x) (0x10 + 0x10 * x)
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#define TIMER_CTRL_START (1 << 0)
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#define TIMER_CTRL_AUTORELOAD (1 << 1)
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#define TIMER_CTRL_CLKSRC_MASK (3 << 2)
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#define TIMER_CTRL_OSC24M (1 << 2)
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#define TIMER_CTRL_PRESCALAR_MASK (0x7 << 4)
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#define TIMER_CTRL_PRESCALAR(x) ((x - 1) << 4)
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#define TIMER_CTRL_MODE_MASK (1 << 7)
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#define TIMER_CTRL_MODE_SINGLE (1 << 7)
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#define TIMER_CTRL_MODE_CONTINUOUS (0 << 7)
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#define TIMER_INTV_REG(x) (0x14 + 0x10 * x)
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#define TIMER_CURV_REG(x) (0x18 + 0x10 * x)
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#define TIMER_ENABLE (1<<0)
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#define TIMER_AUTORELOAD (1<<1)
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#define TIMER_OSC24M (1<<2) /* oscillator = 24mhz */
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#define TIMER_PRESCALAR (0<<4) /* prescalar = 1 */
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/* 64 bit counter, available in A10 and A13 */
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#define CNT64_CTRL_REG 0xa0
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#define CNT64_CTRL_RL_EN 0x02 /* read latch enable */
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#define CNT64_LO_REG 0xa4
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#define CNT64_HI_REG 0xa8
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#define SYS_TIMER_CLKSRC 24000000 /* clock source */
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#define SYS_TIMER_CLKSRC 24000000 /* clock source */
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enum a10_timer_type {
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A10_TIMER = 1,
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A23_TIMER,
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};
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struct a10_timer_softc {
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device_t sc_dev;
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struct resource *res[2];
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void *sc_ih; /* interrupt handler */
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uint32_t sc_period;
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uint32_t timer0_freq;
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struct eventtimer et;
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uint64_t timer0_freq;
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struct eventtimer et;
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enum a10_timer_type type;
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};
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int a10_timer_get_timerfreq(struct a10_timer_softc *);
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#define timer_read_4(sc, reg) \
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
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bus_read_4(sc->res[A10_TIMER_MEMRES], reg)
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#define timer_write_4(sc, reg, val) \
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
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bus_write_4(sc->res[A10_TIMER_MEMRES], reg, val)
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static u_int a10_timer_get_timecount(struct timecounter *);
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static int a10_timer_timer_start(struct eventtimer *,
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sbintime_t first, sbintime_t period);
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static int a10_timer_timer_stop(struct eventtimer *);
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static uint64_t timer_read_counter64(void);
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static uint64_t timer_read_counter64(struct a10_timer_softc *sc);
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static void a10_timer_eventtimer_setup(struct a10_timer_softc *sc);
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static int a10_timer_hardclock(void *);
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static void a23_timer_timecounter_setup(struct a10_timer_softc *sc);
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static u_int a23_timer_get_timecount(struct timecounter *tc);
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static int a10_timer_irq(void *);
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static int a10_timer_probe(device_t);
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static int a10_timer_attach(device_t);
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#if defined(__arm__)
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static delay_func a10_timer_delay;
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#endif
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static struct timecounter a10_timer_timecounter = {
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.tc_name = "a10_timer timer0",
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@ -114,7 +134,17 @@ static struct timecounter a10_timer_timecounter = {
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.tc_quality = 1000,
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};
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struct a10_timer_softc *a10_timer_sc = NULL;
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static struct timecounter a23_timer_timecounter = {
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.tc_name = "a10_timer timer0",
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.tc_get_timecount = a23_timer_get_timecount,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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/* We want it to be selected over the arm generic timecounter */
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.tc_quality = 2000,
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};
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#define A10_TIMER_MEMRES 0
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#define A10_TIMER_IRQRES 1
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static struct resource_spec a10_timer_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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@ -122,39 +152,34 @@ static struct resource_spec a10_timer_spec[] = {
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{ -1, 0 }
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};
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static uint64_t
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timer_read_counter64(void)
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{
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uint32_t lo, hi;
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/* Latch counter, wait for it to be ready to read. */
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timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
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while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
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continue;
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hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
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lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
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return (((uint64_t)hi << 32) | lo);
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}
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static struct ofw_compat_data compat_data[] = {
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{"allwinner,sun4i-a10-timer", A10_TIMER},
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{"allwinner,sun8i-a23-timer", A23_TIMER},
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{NULL, 0},
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};
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static int
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a10_timer_probe(device_t dev)
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{
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struct a10_timer_softc *sc;
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#if defined(__arm__)
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u_int soc_family;
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#endif
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sc = device_get_softc(dev);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-timer"))
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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#if defined(__arm__)
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/* For SoC >= A10 we have the ARM Timecounter/Eventtimer */
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soc_family = allwinner_soc_family();
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if (soc_family != ALLWINNERSOC_SUN4I &&
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soc_family != ALLWINNERSOC_SUN5I)
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return (ENXIO);
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#endif
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device_set_desc(dev, "Allwinner A10/A20 timer");
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device_set_desc(dev, "Allwinner timer");
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return (BUS_PROBE_DEFAULT);
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}
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@ -162,10 +187,11 @@ static int
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a10_timer_attach(device_t dev)
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{
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struct a10_timer_softc *sc;
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clk_t clk;
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int err;
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uint32_t val;
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sc = device_get_softc(dev);
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sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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@ -173,12 +199,10 @@ a10_timer_attach(device_t dev)
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}
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sc->sc_dev = dev;
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sc->sc_bst = rman_get_bustag(sc->res[0]);
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sc->sc_bsh = rman_get_bushandle(sc->res[0]);
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/* Setup and enable the timer interrupt */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
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NULL, sc, &sc->sc_ih);
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err = bus_setup_intr(dev, sc->res[A10_TIMER_IRQRES], INTR_TYPE_CLK,
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a10_timer_irq, NULL, sc, &sc->sc_ih);
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if (err != 0) {
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bus_release_resources(dev, a10_timer_spec, sc->res);
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device_printf(dev, "Unable to setup the clock irq handler, "
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@ -186,17 +210,90 @@ a10_timer_attach(device_t dev)
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return (ENXIO);
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}
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/* Set clock source to OSC24M, 16 pre-division */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val |= TIMER_PRESCALAR | TIMER_OSC24M;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0)
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sc->timer0_freq = SYS_TIMER_CLKSRC;
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else {
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if (clk_get_freq(clk, &sc->timer0_freq) != 0) {
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device_printf(dev, "Cannot get clock source frequency\n");
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return (ENXIO);
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}
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}
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#if defined(__arm__)
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a10_timer_eventtimer_setup(sc);
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arm_set_delay(a10_timer_delay, sc);
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a10_timer_timecounter.tc_priv = sc;
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a10_timer_timecounter.tc_frequency = sc->timer0_freq;
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tc_init(&a10_timer_timecounter);
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#elif defined(__aarch64__)
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a23_timer_timecounter_setup(sc);
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#endif
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if (bootverbose) {
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device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
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device_printf(sc->sc_dev, "event timer clock frequency %ju\n",
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sc->timer0_freq);
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device_printf(sc->sc_dev, "timecounter clock frequency %jd\n",
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a10_timer_timecounter.tc_frequency);
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}
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return (0);
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}
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static int
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a10_timer_irq(void *arg)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)arg;
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/* Clear interrupt pending bit. */
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timer_write_4(sc, TIMER_IRQ_STA_REG, TIMER_IRQ_PENDING(0));
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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/*
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* Disabled autoreload and sc_period > 0 means
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* timer_start was called with non NULL first value.
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* Now we will set periodic timer with the given period
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* value.
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*/
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if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
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/* Update timer */
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timer_write_4(sc, TIMER_CURV_REG(0), sc->sc_period);
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/* Make periodic and enable */
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val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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}
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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/*
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* Event timer function for A10 and A13
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*/
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static void
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a10_timer_eventtimer_setup(struct a10_timer_softc *sc)
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{
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uint32_t val;
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/* Set clock source to OSC24M, 1 pre-division, continuous mode */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
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val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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/* Enable timer0 */
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val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
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val |= TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
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sc->timer0_freq = SYS_TIMER_CLKSRC;
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val = timer_read_4(sc, TIMER_IRQ_EN_REG);
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val |= TIMER_IRQ_ENABLE(0);
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timer_write_4(sc, TIMER_IRQ_EN_REG, val);
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/* Set desired frequency in event timer and timecounter */
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sc->et.et_frequency = sc->timer0_freq;
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@ -209,25 +306,6 @@ a10_timer_attach(device_t dev)
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sc->et.et_stop = a10_timer_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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if (device_get_unit(dev) == 0) {
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arm_set_delay(a10_timer_delay, sc);
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a10_timer_sc = sc;
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}
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a10_timer_timecounter.tc_frequency = sc->timer0_freq;
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tc_init(&a10_timer_timecounter);
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if (bootverbose) {
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device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
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device_printf(sc->sc_dev, "event timer clock frequency %u\n",
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sc->timer0_freq);
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device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
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a10_timer_timecounter.tc_frequency);
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}
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return (0);
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}
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static int
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@ -250,20 +328,20 @@ a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
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count = sc->sc_period;
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/* Update timer values */
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timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
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timer_write_4(sc, TIMER_INTV_REG(0), sc->sc_period);
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timer_write_4(sc, TIMER_CURV_REG(0), count);
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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if (period != 0) {
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/* periodic */
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val |= TIMER_AUTORELOAD;
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val |= TIMER_CTRL_AUTORELOAD;
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} else {
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/* oneshot */
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val &= ~TIMER_AUTORELOAD;
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val &= ~TIMER_CTRL_AUTORELOAD;
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}
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/* Enable timer0 */
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val |= TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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val |= TIMER_IRQ_ENABLE(0);
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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return (0);
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}
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@ -277,62 +355,104 @@ a10_timer_timer_stop(struct eventtimer *et)
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sc = (struct a10_timer_softc *)et->et_priv;
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/* Disable timer0 */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val &= ~TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val &= ~TIMER_CTRL_START;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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sc->sc_period = 0;
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return (0);
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}
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int
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a10_timer_get_timerfreq(struct a10_timer_softc *sc)
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/*
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* Timecounter functions for A23 and above
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*/
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static void
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a23_timer_timecounter_setup(struct a10_timer_softc *sc)
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{
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return (sc->timer0_freq);
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uint32_t val;
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/* Set clock source to OSC24M, 1 pre-division, continuous mode */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
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val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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/* Set reload value */
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timer_write_4(sc, TIMER_INTV_REG(0), ~0);
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val = timer_read_4(sc, TIMER_INTV_REG(0));
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/* Enable timer0 */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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val = timer_read_4(sc, TIMER_CURV_REG(0));
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a23_timer_timecounter.tc_priv = sc;
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a23_timer_timecounter.tc_frequency = sc->timer0_freq;
|
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tc_init(&a23_timer_timecounter);
|
||||
}
|
||||
|
||||
static int
|
||||
a10_timer_hardclock(void *arg)
|
||||
static u_int
|
||||
a23_timer_get_timecount(struct timecounter *tc)
|
||||
{
|
||||
struct a10_timer_softc *sc;
|
||||
uint32_t val;
|
||||
|
||||
sc = (struct a10_timer_softc *)arg;
|
||||
sc = (struct a10_timer_softc *)tc->tc_priv;
|
||||
if (sc == NULL)
|
||||
return (0);
|
||||
|
||||
/* Clear interrupt pending bit. */
|
||||
timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
|
||||
|
||||
val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
|
||||
/*
|
||||
* Disabled autoreload and sc_period > 0 means
|
||||
* timer_start was called with non NULL first value.
|
||||
* Now we will set periodic timer with the given period
|
||||
* value.
|
||||
*/
|
||||
if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
|
||||
/* Update timer */
|
||||
timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
|
||||
|
||||
/* Make periodic and enable */
|
||||
val |= TIMER_AUTORELOAD | TIMER_ENABLE;
|
||||
timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
|
||||
}
|
||||
|
||||
if (sc->et.et_active)
|
||||
sc->et.et_event_cb(&sc->et, sc->et.et_arg);
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
val = timer_read_4(sc, TIMER_CURV_REG(0));
|
||||
/* Counter count backwards */
|
||||
return (~0u - val);
|
||||
}
|
||||
|
||||
u_int
|
||||
/*
|
||||
* Timecounter functions for A10 and A13, using the 64 bits counter
|
||||
*/
|
||||
|
||||
static uint64_t
|
||||
timer_read_counter64(struct a10_timer_softc *sc)
|
||||
{
|
||||
uint32_t lo, hi;
|
||||
|
||||
/* Latch counter, wait for it to be ready to read. */
|
||||
timer_write_4(sc, CNT64_CTRL_REG, CNT64_CTRL_RL_EN);
|
||||
while (timer_read_4(sc, CNT64_CTRL_REG) & CNT64_CTRL_RL_EN)
|
||||
continue;
|
||||
|
||||
hi = timer_read_4(sc, CNT64_HI_REG);
|
||||
lo = timer_read_4(sc, CNT64_LO_REG);
|
||||
|
||||
return (((uint64_t)hi << 32) | lo);
|
||||
}
|
||||
|
||||
#if defined(__arm__)
|
||||
static void
|
||||
a10_timer_delay(int usec, void *arg)
|
||||
{
|
||||
struct a10_timer_softc *sc = arg;
|
||||
uint64_t end, now;
|
||||
|
||||
now = timer_read_counter64(sc);
|
||||
end = now + (sc->timer0_freq / 1000000) * (usec + 1);
|
||||
|
||||
while (now < end)
|
||||
now = timer_read_counter64(sc);
|
||||
}
|
||||
#endif
|
||||
|
||||
static u_int
|
||||
a10_timer_get_timecount(struct timecounter *tc)
|
||||
{
|
||||
|
||||
if (a10_timer_sc == NULL)
|
||||
if (tc->tc_priv == NULL)
|
||||
return (0);
|
||||
|
||||
return ((u_int)timer_read_counter64());
|
||||
return ((u_int)timer_read_counter64(tc->tc_priv));
|
||||
}
|
||||
|
||||
static device_method_t a10_timer_methods[] = {
|
||||
@ -352,16 +472,3 @@ static devclass_t a10_timer_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
|
||||
BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
|
||||
|
||||
static void
|
||||
a10_timer_delay(int usec, void *arg)
|
||||
{
|
||||
struct a10_timer_softc *sc = arg;
|
||||
uint64_t end, now;
|
||||
|
||||
now = timer_read_counter64();
|
||||
end = now + (sc->timer0_freq / 1000000) * (usec + 1);
|
||||
|
||||
while (now < end)
|
||||
now = timer_read_counter64();
|
||||
}
|
||||
|
||||
@ -108,6 +108,9 @@ options SOC_BRCM_BCM2837
|
||||
options SOC_ROCKCHIP_RK3328
|
||||
options SOC_XILINX_ZYNQ
|
||||
|
||||
# Timer drivers
|
||||
device a10_timer
|
||||
|
||||
# Annapurna Alpine drivers
|
||||
device al_ccu # Alpine Cache Coherency Unit
|
||||
device al_nb_service # Alpine North Bridge Service
|
||||
|
||||
@ -26,6 +26,7 @@ cloudabi64_vdso_blob.o optional compat_cloudabi64 \
|
||||
|
||||
# Allwinner common files
|
||||
arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt
|
||||
arm/allwinner/a10_timer.c optional a10_timer fdt
|
||||
arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt
|
||||
arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt
|
||||
arm/allwinner/aw_nmi.c optional aw_nmi fdt \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user